GB2055233A - Data processing system including a cache store - Google Patents

Abstract

A data processing system includes a main memory system 3, a high speed buffer cache store, a central processor unit (CPU) and an Input/Output processor (IOP) all connected to a system bus. Apparatus in the cache store reads all information on the system bus into a first in, first out buffer comprising a plurality of registers, a write address counter, a read address counter and a means for selectively processing the information. The cache store is word oriented and further comprises a directory 202, a data buffer 201 and associated control logic. The CPU requests data words by sending a main memory address of the requested data word to the cache store. If the cache store does not have the requested data word, apparatus in the cache store requests the data word from the main memory system, and in addition, the apparatus requests additional data words from consecutively higher addresses. If the main memory system is busy, the cache store has apparatus to request fewer words. The cache store is organized in levels. Data from a particular portion of main memory is transferred to these levels on a first in-first out basis. Apparatus in the form of round robin logic circuitry makes the first in-first out level selection. Apparatus also exists for resetting the round robin count during the initialization procedure. Apparatus in the cache store monitors each communication between system units to determine if it is a communication from a system unit to the main memory system which will update a word location in main memory. If that word location is also stored in the cache store then the word location in the cache store will be updated in addition to the word location in main memory. <IMAGE>

Description

1 GB 2 055 233 A 1

SPECIFICATION

Improvements in or relating to data processing systems This invention relates generally to mini computing systems and more particularly to 70 storage hierarchies haing high speed low capacity storage devices and lower speed high capacity devices coupled in common to a system bus.

The storage hierarchy concept is based on the phenomena that individual stored programs under execution exhibit the behaviour that in a given period of time a localized area of memory receives a very high frequency of usage. Thus, a memory organization that provides a relatively small size buffer at the CPU interface, and the various levels of increasing capacity slower storage can provide an effective access time that lies somewhere in between the range of the fastest and the slowest elements of the hierarchy and provides a large capacity memory system that is "transparent" to the software.

Prior art systems use a large capacity main store or main memory and a small capacity high speed backing store or cache memory associated with the CPU. The cache memory includes a cache directory and a cache data store. The CPU requests a data word from both the main memory and cache. If the data word is in cache then the request of main memory is invalidated. If the data word is not in cache then the requested data word is sent to the CPU and a block of data containing the requested data word is stored in cache. In the prior art the cache is associated with a bus system. Registers in the cache are coupled to the bus system and accept address, data and control 100 signals.

Prior art was limited to storing the requested data word with its address in hardware registers.

When the need came about for expanded size, low cost buffers, the prior art utilized a block 105 organization. If a particular word was requested by the CPU, the block containing that word was stored in a high speed data buffer. This had the disadvantage of bringing into the high speed buffer words with a relatively low probability of 110 usage. Assuming a four word block, if word 4 is requested, the entire block including words 1, 2 and 3 which may have a relatively low probability of usage, are brought into the high speed buffer.

To optimize the usage of the memory hierarchy, 115 the operating system must organize memory in such a manner that software submodules and data blocks start with word 1 of the block. To overcome this difficulty, the prior art utilized a "block lookahead". When one block was in the high 120 speed buffer, a decision was made during the processing of a data word in that block to bring the next block into the high speed buffer.

U.S. Patent No. 3,231,868 issued to L. Bloom et al., entitled "Memory Arrangement for Electronic 125 Data Processing System" discloses a "look aside" memory which stores a word in a register and its main memory address in an associated register. To improve performance, U.S. Patent No.

3,588,829, issued to L. J. Boland et al., discloses an eight-word block fetch to the high speed buffer from main memory if any word in the eightword block is requested by the CPU.

An article by C. J. Conti, entitled "Concepts for Buffer Storage" published in the IEEE Computer Group News, March 1969, describes the transfer of 64-byte blocks as used on the IBM 360/85 when a particular byte of that block not currently in the buffer is requested. The IBM 360/85 is described generally on pages 2 through 30 of the IBM System Journal, Vol. 71. No. 1., 1968.

U.S. Patent No. 3,588,829 issued to Boland, et al., entitled "Integrated Memory System with Block Transfer to a Buffer Store" describes the prefetching of a block of information if a word in that block is requested.

U.S. Patent No. 3,820,078 issued to Curley et al entitled "Multilevel Storage System Having A Buffer Store With Variable Mapping Modes" describes the transfer of blocks of 32 bytes or half-blocks of 16 bytes from main memory to the high speed buffer when a word (4 bytes) of the block or half-block is requested by the CPU. U.S. Patent No. 3,896,419 issued to L2nge et al., entitled "Cache Memory Store In A Processor of A Data Processing System" describes the transfer of a four word block from main memory to the high speed buffer when a word of that block is requested by the CPU. U.S. Patent No. 3,898,624 issued to Tobias entitled "Data Processing System With Variable Prefetch and Replacement Algorithms" describes the prefetching of the next line (32 Bytes) from main memory to the ffigh speed buffer when a specific byte is requested by the CPU of the previous line.

In minicomputers, particularly those minicomputers which are organized in such a fashion that a plurality of system units are connected in common to a system bus, the prior art systems present a number of problems all having to do with reducing the throughput of the minicomputer. The prior art sends back to cache from main memory the entire block of words in which the requested word is located. This includes words with addresses preceding the requested word and words with addresses following the requested word. In most cases, the CPU will require on the following cycle the word in the next higher address. This results in words with high probability of being used as well as words with lower probability of being used being transferred into cache. To overcome this problem, the prior art requires that the programmer or the operating system optimize their programs to start sequences off with words at the first address of each block. Another problem in the prior art is that a block of words transferring from main memory to cache comes over in successive cycles, for example, a 32 byte block may be transferred in 8 cycles, 4 bytes at a time. In the minicomputer bus oriented system, this would greatly reduce the throughput of the system.

Prior art systems using the round robin type of replacement procedure have the cache store

2 GB 2 055 233 A 2 1 1 1 orqanized in levels. A round robin counter is used to indicate the next level into which replacement information is written. Also, in the prior art a full/ empty mechanism is included to indicate the status of the information in each of the levels of the store.

During the initialization operation the prior art systems clear the cache by resetting the full/empty indicators.

In the prior art, the replacement procedure included logic circuitry to ensure that valid data was stored in cache since random data might be resident in the cache store on an initialize cycle for instance.

U.S. Patent 3,840,862 issued to D. T. Ready entitled "Status Indicator Apparatus for Tag Directory in Associative Stores" and U.S. Patent 3,845,575 issued to R. E. Lange, et al, entitled "Cache Store Clearing Operation for a Multiprocessor Mode" both describe such 85 systems.

T6 disadvantage of the additional storage of the full/empty bits with the complexities of the additional logic circuitry are overcome by the approach used in this invention.

It is an object of the invention to provide an improved cache directory and cache data store system for use in a system bus oriented computing system.

According to the present invention, a data 95 processing system comprises:

a system bus; a central processing unit coupled to said bus and being operative to generate memory requests, each said memory request including a main 100 memory address; an addressable main memory coupled to said bus, said main memory including a pluraltiy of sets of locations for storing a plurality of words, each word location being designated by an address 105 coded to include a first portion and a second portion; and a cache unit coupled to said bus and to said central processing unit, said cache unit comprising:

a register which stores the main memory address received from the central processinq unit, an addressable data store having a plurality of locations which store the contents of subsets of said sets of locations in the main memory, each 115 word location being designated by said second portion of said address; an addressable directory having a plurality of locations, corresponding in number to said plurality of data store locations, which stores a plurality of said first portion of said addresses in a location designated by said second portion of said address, each address location of the directory specified by the second portion of the address having a corresponding address location in the data store storing the word specified by the second portion of the address and the first portion of the address stored in the address location of the directory specified by the second portion of the address, the cache unit and the directory receiving 130 the main memory address from the central processing unit when requesting a word from the main memory and control means coupled to said register and responsive to each memory request received from the central processing unit and coded to specify a read operation so as to indicate if the word requested by the central processing unit is stored in the data store by comparing the first portion of each main memory address received from the central processing unit with said first portion address stored in the location of said directory -read out in response to said second portion of each main memory address received from the central processing unit, and in the absence of the equal comparison requesting the word from the main memory by generating a signal which transfers signals representative of said main memory address to said register and to said main memory, said control means being operative upon receiving said word from main memory to generate signals for writing said word in the data store at the location designated by said second portion of the address stored in said register and which concurrently writes said first portion of said main memory address stored in said register in the directory in the location designated by the second portion of said main memory address. The invention also provides a data processing system comprising: an addressable main memory having a plurality of sets of locations for storing a plurality of words, each word location being designated having an address which is coded to have a first portion and a second portion; and, a cache unit cqupled to the main memory to store signals read out therefrom in response to a main memory request including a main memory address, said cache unit further comprising a register which stores the main memory address requested of the cache unit; an addressable data store having a plurality of locations which store the contents of subsets of said sets of locations in the main memory, each word location being designated by the second portion of said address; an addressable directory having a plurality of locations corresponding in number to said plurality of data store locations which stores at least a first portion of one of said addresses in a location designated by said second portion of said address, each address location of the directory specified by the second portion of the address having a corresponding address location in the data store storing the word speciftied by the second portion of the address and the first portion of the address stored in the address location of the directory specified by the second portion of the address, the cache unit and the directory receiving the main memory address requested of the main memory and control means responsive to each memory request specifying a read operation which indicates if a requested word is stored in the data store by comparing said first portion of each main 3 GB 2 055 233 A 3 memory address with the first portion address stored in the location of the directory designated by the second portion of said each main memory address, and in the absence of an eqpal comparison generating signals which transfers signals representative of the main memory address to the register and to the main memory, the control means being operative upon receiving the requested word from the main memory to generate signals for writing the word in the data store at the location designated by the second portion of the address stored in the register and which concurrently writes the first portion of the main memory address stored in the register in the directory in the location designated by the second portion of the main memory address.

The invention further provides a method of organising such a memory system comprising storing a plurality of words in a plurality of sets of the main memory locations, each word location being designated by an address coded to include a first portion and a second portion; storing the contents of subsets of said sets of main memory locations into a plurality of the data store locations; storing at least the first portion of one of 90 the addresses in one of the directory locations designated by the second portion of said one address; comparing the first portion of each main memory address with the first portion address stored in the location of the directory read out in response to the second portion of each main memory address; and generating signals in the absence of a prescribed comparison for writing a word read out from main memory in said data store at the location designated by said second portion of said address stored in the register and for concurrently writing said first portion of said main memory address stored in said register in said directory in said location designated by the second portion of the main memory address.

A preferred embodiment of the invention comprises a main memory, a central processor (CPU), a cache store adn an Input/Output Processor all connected in common to a systems bus. The cache store provides first access to information previously fetched from main memory by way of the systems bus. The CPU requests information from the cache system over a private CPU-Cache interface. If the information is in cache, it is returned immediately to the CPU over the private CPU-Cache interface. If the information is not in cache, then the cache requests the information over the system bus from main memory and the cache receives the requested information over the system bus from main memory. In order to assure that the information stored in cache is current with the information stored in main memory, apparatus in the cache reads all system bus information. If the information read from bus is to update main memory then apparatus in cache updates the information stored in cache if the address location of the information is stored in cache.

Information received by cache from the system bus to be updated in cache includes control bits 130 coded to indicate that the information contains a main memory address, that this is a main memory write operation and that the information has been accepted by main memory. If the information also includes a cache identification code then a directory search is made of the address included in the information.

The probability is high that the next information requested by the CPU is in the next higher address 7 r, location in main memory. It would therefore increase the throughput of the overall data processing system if that information from the next higher address location could be brought into cache immediately. This system provides apparatus for prefetching not only the information in the next higher address location but prefetches information from a plurality of successively higher locations in main memory to cache over the system bus. In some main memory configurations when main memory is busy processing information from other systems connected to the system bus, and the cache requests information over the system bus, main memory sends out a "busy" logic signal over the system bus. This system senses the busy signal and requests less information from main memory than if main memory were not busy.

In one embodiment, main memory is organized as an interleaved double fetch memory, that is even addresses are in one memory bank and odd addresses are in another memory bank. This allows some increase in main memory throughput. The double fetch feature provides up to 2 data words of information for each main memory request. Interleaved memories are used throughout the industry. This interleaved memory is conventional in design. Typical interleaved memories are described in U.S. Patent No.

3,796,996, issued March 12, 1974.

When the CPU requests information from cache and that requested information is not in cache, apparatus in cache sends 2 requests over the system bus to main memory for a total of 4 data words of information. if main memory responds over the system bus that main memory is busy after receiving the first request, then logic circuits in cache respond to the "busy" by repeating the first request. When the first request is accepted by main memory, cache sends the second request over the system bus to main memory. If main memory responds with a busy logic signal, then apparatus in the cache cancels the second request and awaits the 2 data words of information from main memory over the system bus.

In another embodiment, main memory is orgnized as a banked double fetch memory, that is each memory bank has consecutive address locations. When the CPU requests information from cache and that requested information is not in cache, apparatus in cache sends 1 request to main memory over the system bus for 2 data words of information. If main memory responds over the system bus with a "busy" signal, then cache responds by repeating the request to main memory over the system bus.

4 GB 2 055 233 A 4 The system uses the attributes of a word system with simplified circuitry over a block system to efficiently process data with a reasonably high hit ratio. Transferring a word at a time over the system bus between main memory and the cache data store with the cache directory mapping data store location for location increases throughput and decreases the logic circuits required for implementing this system over prior art systems. In the event that the system bus is busy, the data request of main memory by cache of words following the requested ward is cancelled.

The cache system monitors all information on the system bus. If the information is a main memory write reference, and if the address of the information to be written is stored in the directory,' then the information in the data buffer at that address is -updated- with the new information from the system bus.

The central processor sends information to the main memory over the system bus but requests information from the cache over a private CPU cache interface by sending the address of the requested information to cache. If that address is stored in the directory, then the data from the data store at that address is sent to the central processor over the private CPU-cache interfaceAf the address is not stored in the directory, then the cache unit requests this information of main memory by sending' the address of the requested information out on the system bus as a memory request.

Cache in its continuous monitoring of the 35. system bus will receive the information in 100 response to the memory request. The data received on the system bus is sent to the central processor over the private CPU-cache interface.

An 1 8-bit address is sent to the directory. The 8 high order address bits are written into the directory at the address specified by the 10 low order address bits. The data sent to the CPU is written into the data store at the address specified by the 10 low order bits. This data replaces the oldest data previously written into that address. A 110 round robin counter keeps track of, for each address, the next level of cache to receive the replacement" data.

The system bus interface unit connects the cache memory unit to the system bus enabling the 115 cache memory unit to access main memory and read out CPU required information. The system bus has been covered by U.S. Patents 3,993,891 entitled "Apparatus for Processing Data Transfer Requests in a Data Processing System- and 4,030,075 entitled--- DataProcessing System Having Distributed Priority NetworV.

The cache apparatus comprises a first in -first out buffer, a read address counter, a write address counter and control logic. The first in - first out buffer is made up of four 44 bit registers. Information from the system bus is read into one of the empty registers of the first in -first out buffer. If the information is to update main memory and is acknowledged as being received by main memory then a search is made of a cache directory for that main memory location. If the cache directory indicates that the main memory address location is stored in a cache data buffer then the data word is written into that data location in the cache data buffer. If the cache directory indicates that the main memory address location is not stored in the cache data buffer then, the information is discarded. This assures that the cache data buffer is current with main memory.

Also, if the information in the first in - first out buffer contains a cache address identification code; then the data word portion of the information is written into the cache data buffer at the address stored in a replacement address file.

Information in the first in - first out buffer is accepted by advancing the write address counter to point to the next register location in the first in - first out buffer. If the information is to be discarded then the write address counter does not advance and the next bus cycle information writes over the previous information.

The information sent over the system bus includes a control bit which indicates if the go information is representative of an update or replacement operation.

If the bit is coded to represent an update operation then it enables the address portion of the information sent over the system bus to search the directory. If the directory stores that address then the control bit initiates logic circuits to update the data word stored in the data buffer.

If the bit is coded to represent a replacement operation then the control bit enables the replacement address file to send the CPU request address to the directory. The control bit initiates logic circuits to replace the oldest information at the data buffer word location indicated by the CPU request address with the data word contained in the information sent over the system bus.

The overall system initialization procedure includes means for loading all memory locations in cache with information from main memory starting with the low order address and continuing sequentially until the entire cache is full. This eliminates the requirement for the full/empty logic circuitry by eliminating the possibility of random data in cache.

As a consequency of loading the cache during the initialization cycles, the round robin count for each level is set in such a manner that during subsequent processing the first information written into cache will be the first information replaced.

The round robin approach described herein enhances the test and diagnostic procedures by limiting the writing of information in cache to check out that level only.

Arrangements according to the invention will now be described, by way of example, with reference to the accompanying drawings, in whichFigure 1 is a block diagram of the overall system; 130 Figure 2 is a block diagram of the cache system; Figure 3 is a logic circuit diagram of Clock Control and FIFO R1W Control; Figure 4 is a logic circuit diagram of AOR and RAF Control, the RAF Write Address Counter and the RAF Read Address Multiplexer; Figure 5 is a logic circuit diagram of Cycle Control and System Bus Control; Figure 6 is a timing diagram of the replacement operation with an interleaved memory; Figure 7 is a timing diagram of the replacement operation with a banked memory; Figure 8 shows the system bus formats; Figure 9 is a flow diagram illustrating the replacement and the update operation; Figure 10 is a timing diagram of the update cycle; Figure 11 shows the layout of the address bits for main memory and cache; Figure 12 illustrates the relationship between a banked main memory and cache; Figure 13 illustrates the relationship between an interleaved main memory and cache; Figure 14 is a logic diagram of the round robin; Figure 15 is a timing diagram of the Quality Logic Test operation; and Figure 16 is a flow diagram illustrating the Quality Logic Test operation.

Figure 1 is a block diagram of a mini- computer system which comprises a central processor unit (CPU) 2, a main memory 3, an input/output multiplexer (IOM) 7, a system bus 5, a cache directory and data buffer (cache) 1 and a system support channel (SSC) 8. Not shown are the normal complement of standard peripherals connected to the system by SSC 8. With the exception of SSC 8, each unit couples to the system bus 5 via an interface signal bus 4, SSC 8 couples to the IOM 7 through input/output (1/0) bus 9. In addition, CPU 2 and cache 1 are interconnected by a private interface signal bus 6. IOM 7, 1/0 bus 9 and SSC 8 are not pertinent to the invention and will not be described in detail.

CPU 2 is designed for use as a communications network processor and is a firmware controlled 20 bits per word binary machine. Main memory 3 can 110 be added to the system in modules of 32, 768 words up to a maximum of 8 modules or 262,144 words. Main memory 3 is made up of random access MOS chips with 4,096 bits stored in each chip and has a read/write cycle time of 550 115 nanoseconds. Cache 1 provides an intermediate high speed storage with a maximum read/write cycle time of 240 nanoseconds. CPU 2 requests a data word from cache 1 over private interface 6 and obtains the data word if in cache 1 in 110 nanoseconds over private interface bus 6. If the 120 requested data is not in cache 1, then CPU 2 receives the data via main memory 3, bus 5, cache 1 and bus 6 in 960 nanoseconds. If cache 1 was not in the system, then the CPU 2/main memory 3 read access time is 830 nanoseconds. Using the 125 prefetch techniques described herein assures that in most cases over 90% of the requested data words are stored in cache 1 thereby greativ GB 2 055 233 A 5 increasing the throughouput of the system"using cache 1 over a system without cache 1. System bus 5 permits any two units on the bus to communicate with each other. To communicate, a unit must request a bus 5 cycle. When the bus 5 cycle is granted, that unit may address any other unit on bus 5. 1/0 bus 9 is identical to system bus 5 in performance and in signal makeup. IOM 7 controls the flow of data between bus 5 and the various communications and peripheral controllers of the system via 1/0 bus 9. SSC 8 is a microprogrammed peripheral controller which provides control for various devices (not shown). Other controllers (not shown) may also connect to 1/0 bus 9.

CPU 2 updates data in main memory 3 by sending the data word with its main memory 3 address and the appropriate control signals out on bus 5. Cache 1, since it reads all information on bus 5 into a register in cache 1 will be updated if that data word location is stored in cache 1. This assures that information stored at each address location in cache 1 is the same as information stored at the corresponding address location in main memory 3.

CPU 2 requests data from cache 1 by sending the requested address (PRA) over private interface 6 to, cache 1. If the data is stored in cache 1, the requested data is sent back to CPU 2 from cache 1 over private interface 6. If the requested data is not in cache 1, cache 1 requests the data of main memory 3 over bus 5 and in addition cache 1 requests three additional data words from address locations PRA+ 1, PRA+2 and PRA+3 for the - interleaved memory or one additional word of data from address location P RA+ 1 for the banked memory. When the data words are received from main memory 3 over bus 5 by cache 1, they are written into cache 1 and the requested data word is sent from cache 1 to CPU 2 over private interface 6.

CACHE SYSTEM Figure 2 shows the cache 1 system which includes a bus interface unit 10, a replacement and update unit 11, a cache directory anddata buffer unit 12, an address control unit 13 and a private cache-CPU interface unit 6. Figure 2 is made up of 4 sheets. The information flow is best seen with sheet 2 at the left, sheet 1 on the right, sheet 3 below sheet 1 and sheet 4 below sheet 3.

BUS INTERFACE UNIT 10 Figure 2, Sheet 1 Bus interface unit 10, Figure 2, comprises drivers 212, 214 and 218, receivers 213, 215 and 217, and system bus control logic unit 219.

Bus interface unit 10 connects to bus 5 through interface signal bus 4. Bus 5, interface signal bus 4 and system bus control 219 are disclosed by U.S. Patent Nos. 3,993,981 entitled "Apparatus For Processing Data Transfer Requests In A Data Processing Systern", and 4,030,075 entitled --DataProcessing Systems Having Distributed Priority NetworV and will be described herein 6 GB 2 055 233 A 6 1 1 --- only as necessary to provide continuity to the description.

The 18 address leads BSAD05-22 are connected between bus 5 and the junction of the driver 212 and the receiver 213 of bus interface unit 10.The outputof receivers 213, 215 and 217 70 connect to a First-ln-First-Out (FIFO) buffer 203.

The 20 bit data word lines BSDT A, B, 00-15, BSDP 00, 08 are connected to the junction of the driver 214 and receiver 215. A number of control signal lines are connected to the junction of the driver 218 and the receiver 217. These control logic signals Bus request BSREQT, data cycle now BSDCNN, bus acknowledge BSACKR, bus wait BSWAIT, BSAD 23, second half bus cycle BSSHBC and bus double pull BSDBPL input 80 system bus control 219 through receiver 217 and are distributed to other logic control units which will be described infra as well as being sent out on bus 5 through driver 2 18.

The My Data Cycle Now logic signal MYDCNN- 85 connects between System Bus Control 219 and drivers 212,214 and 218.

Signal bus BSAD 08-17, the output of receiver 213, connects to Cycle Control 232 of the Replacement and Update Unit 11. The output of an address register (AOR) 207, 18 bit address BAOR 05-22 in the address control unit 13 connects to the input of driver 212. Cache identification code 0002,, and function 00,, or0% are encoded on the input of a driver 214 whose output is connected to the bus 5 data lines BSDT A, B, 00-15. Logic circuit signals described infra are connected between other units of cache 1 and system bus control 219.

The receiver driver pairs 212 and 213, 214 and 100 215, and 217 and 218 are 26S10 circuits described on page 4-28 of the catalog entitled "Schottky & Low Power Schottky Bipolar Memory, Logic & Interface" Published by Advanced Micro Devices, 901 Thompson Place, 105 Sunnyvale, California 94086.

REPLACEMENT AND UPDATE UNIT 11 - Figure 2, Sheet 3 The replacement and update unit 11 Figure 2 includes the FIFO buffer 203, a local register (LR)204, buffer bypass drivers 205, FIFO R/W control 230, clock control 220 and cycle control 232.

Replacement and update unit 11 receives from 115 Bus Interface Unit 10 the 18 bit update address BSAD 05-22, the 20 bit data word BSDT A, B, 00-15 BSDP 00, 08 and control signals all of which connect between FIFO 203 and their respective receivers 213, 215 and 217. An 18 line 120 replacement address signal bus AORO 05-22 connects between the input of LOR 204 and replacement address file (RAF)206 output in address control unit 13. Signal busses FIFO 00-17, FIFO 19-38 and FIFO 18, 39-43 125 connect between the FIFO 203 output and LR 204 output. Also connected between the replacement and update unit 11 and the other units of cache 1 are control signals described infra.

A 20 bit data word signal bus DATA 00-19+ connects between the output of the buffer bypass driver 205 unit and a junction 216 in cache directory and data buffer unit 12. The 18 line update or replacement address signal bus FIFO 00-17+ connect between the output of LR 204 and one input of 2:1 MUX 208, and the 20 bit data output signal lines DATA 00-19- connect between the output of LR 204 and a ca-che data buffer 201. Read address counter output logic signal FRADDR and FRBDDR connect between FIFO R/W Control 230 and FIFO 203 as do write address counter output FWADDR and FWBDDR and Write Strobe signal FWRITE. Logic signal CYFIFO connects between FIFO R/W control 230, cycle control 232 and LR 204. Logic Signal FIFO 41 + connects between the FIFO bit position 41 output of FIFO 203 and FIFO read enable terminals for FIFO 00-17. Logic Signals FIFO 41 - connect between the FIFO bit position 41 output of FIFO 203 and the RAF 206. FIFO 18, 42 and 43 connect between a Read Address Multiplexer 233 and their respective bit position outputs of FIFO 203: Logic Signal MEMREQ connects between cycle control 232, System bus control 219 and a 2:1 MUX 209 switch. CLOCKO+ connects between Clock Control 220, cycle control 232 and other logic units described infra. Logic signal NO HIT+ connects between FIFO R/W control 230, cycle control 232 and NAND 231 of cache directory and data buffer Unit 12. Logic signal REPLACE connects between the LR 204 output, a 2:1 MUX 223 switch and a Round Robin 224 logic unit. Logic signal FEMPTY- connects between FIFO R/W control 230 and Clock Control 220. Logic signal CACHRQ connects between interface 6 and Clock Control 220 and logic signal CYCADN connects to interface 6 from cycle control 232.

FIFO N3 is organized as four 44-bit registers made up of random access memory chips 74LS 670 described on page 7-526 of the TTL Data Book for Design Engineers, second edition, copyright 1976 by Texas Instruments of Dallas, Texas. LR 204 is a 44 bit register made up of conventional flips using conventional design techniques. Address, data and control information are gated by logic signal busses FIFO 00-17, FIFO 19-38 and FIFO 18,39-43 respectively. FIFO 19-38, the data signal bus is gated through buffer bypass drivers 205 by logic signal INTERG+ going high. Buffer bypass drivers 205 are made up of 74 367 circuits described on page 5-69 of the aforementioned TTL Data Book. FIFO R/W control 230 provides read address counter signals FRADDR and FRBDDR, write address counter signals FWADDR and FWBDDR, and a write strobe FWRITE to select the FIFO 203 registers for reading and writing. A FEMPTY- signal going high indicating that the FIFO buffer is not empty stars CLOCKO+ cycling in clock control 220. A FIFO 41 + signal low indicates that the LR 204 18 bit address field LR 0-17 will be filled from RAF 206 over the 18 line AOR 05-22 signal bus.

The replacement cycle is operative in response 7 GB 2 055 233 A 7 to the CPU 2 memory request logic signal 65 CACHRQ. If the requested information is not in cache 1, a request for the information is sent by cache 1 to main memory 3 over bus 5. The requested information coming back from main memory 3 over bus 5 is sent to CPU2 and written 70 into data buffer 201. This operation is called replacement.

Cache 1 reads all information on bus 5 into FIFO 203. If that information was to update main memory 3, then cache 1 cheeks to see if that main memory 3 address location is stored in the data buffer 201. If the information address location is stored in the data buffer 201, then the data word in that location is updated with new information data word. This operation is called update. 80 CACHE STORE AND DATA BUFFER 12 Figure 2, sheet 4 The cache directory and data buffer 12 comprises the data buffer 201, the directory 202, 4 comparators 221 a-d, the 2:1 MUX 208, a round robin 224 logic unit, a 2:1 MUX 223, 18 inverters 225, NOR gates 260 and 261, NAND gates 262 and 263, 10 NAND gates each of 266a-j through 273a-j, a NAND gate 231 and junction 216. Data Buffer 201 further comprises a data buffer 264 for storing left bytes and a data buffer 265 for storing right bytes.

Signal busses are coded as follows in the specificiation and figures. For example, for row address ADDR 00-07-10, ADDR is the signal name. ADDR 00-07 refers to the 8 signal leads labelled ADDR 00, ADDR 01... ADDR 07. ADDR 00-07- indicates that the signals are low if they indicate a---1 " and high if they indicate a "0". ADDR 00-07-10 indicates that this is signal bus 10 of 8 bit row address ADDR 00-07, Main memory 3 address BAOR 05-22+ signal lines connect between bus 6 and one input of 2:1 MUX 208 of the cache directory and data buffer 12. Address signal lines FIFO 00-18+, connect between the output of LR 204 and the other input of 2:1 MUX 208.2:1 MUX 208 output signal bus ADDR 00-17+ connects to 18 inverters 225 whose output ADDR 00-17-10 splits into row address ADDR 00-07-10 and column address ADDR 08-17-10. Row Address ADDR 00-07-10 connects to directory 202 and to one input each of 4 comparators 221 a-d. Column address ADDR 08-17-10 connects to the data buffer 201, directory 202 and round robin 224. Row addresses ADDR 00--07-20,-21,-22 and -23 connect to the second input each of 4 comparators 221 a-d respectively. The 4 outputs of comparators 221 a-d, logic signals HITO-3+ connect to an input of 2:1 MUX 223. HITO+ connects to 10 NAND 226a-j and 10 NAND 270a-j inputs. HIT1 + connects to 10 NAND 267a j and 10 NAND 271 a-j inputs. HIT2+ connects to 10 NAND 268a-j and 10 NAND 272a-j inputs. 125 HIT3+ connects to 10 NAND 269a-j and NAND 273a-j inputs.

The round robin 224 output, LEVEL 0-3+ connects to the second input of 2:1 MUX 223.

The output of 2:1 MUX 223, logic signals WRITE 0-3 connect to the inputs of 4 NAND 262 and 4 NAND 263 circuits. The output of the 4 NAND 262 circuits, logic signals WRITEO-1A, WRITE2-1 A and WRITE 3-1 A respectively connect to Levels 0-3 respectively of data buffer 264. The output of the 4 NAND 263 circuits, logic signals WRITEO-1 B, WRITE1 -1 B, WRITE2-1 B and WRITE3-1 B respectively connect to levels 0-3 respectively of data buffer 265. Logic signals WRITEO-3 are connected to inputs of 4 OR 275a-d, logic signal WRITEO-3-1 B connect to the other input of 4 OR 274a-d. The output of NOR 274a-d connects to LEVEL 0 through LEVEL 3 of directory 202.

Logic signal FIFO 18+ connects between the output of LR 204 bit position F/F 18 and an input to NOR 260. Logic signal FIFO 18- connects between the output of LR 204 bit position F/F 18 and an input to NOR 26 1. Logic signal BYTEMOD connects between the output of LR 204 bit position F/F 39 and the other inputs of NOR 260 and 261 whose outputs connect to the inputs of 4 NAND 262 and 4 NAND 263 circuits. The left byte signals DATA 00-09- connect to the input Levels 0-3 of data buffer 264 and the right byt signals DATA 10-1 g- connect to the input levels 0-3 of data buffer 265. The outputs of levels 0-3 of data buffer 264, 10 signal line busses CADP 00-09,-10,-11,-12 and -13 connect to the respective inputs of NAND 266a-j, 267a-j, 268aJ and 269a-j respectively. The outputs of levels 0-3 of data buffer 265, 10 signal line busses CADP 10-19-10, -11, -12 and -13 connect to the respective inputs of NAND 270a-j, 271a-j, 272a-j and 273a-j. Logic signal iNTERG- connects to the 3rd input of NAND 266a-j through 273a-j whose outputs connect to junction 216. Data word signal bus CADP 00-19+ connects between junction 216 and interface 6. The output signals HIT 0-3+ connect to the 4 inputs of NAND 23 1, the output of which connects to cycle control 232 and FIFO R/W control 230.2:1 MLIX's 208 and 223 are switched by logic signals ADDRSO+ and REPLACE respectively. Logic signal REPLACE connects to round robin 224.

Data buffer 201 is organized into data buffer 264 which stores the left byte DATA 00-09and data buffer 265 which stores the right byte DATA 10-19-. Each data buffer 264 and 265 is organized in 4 levels,each level storing 1,024 bytes in 1,024 byte.Jocations address by 10 bit column address ADDR 08-17-10. 8 bytes are read out of data buffer 201 when data buffer 20.1 is addressed. Either a byte or a word is written into data buffer 201 depending on the control signal BYTEMOD (FIFO 39). If logic signal BYTEMOD is low then the outputs of NOR 260 or 261 are high, which gates the selected logic signal WRITEO, 1, 2 or 3 through the appropriate NAND 262 and 263 to write the left byte of the data word in data buffer 264 and the right byte of the data word in data buffer 265. If logic signal BYTEMOD is high then either the output of NOR 260 or 261 goes 8 high depending on the logic signal FIFO 18 inputs to NOR 260 or 26 1, thereby selecting one of the WRITE 0-3-1 A or one of the WRITE 0-3-1 B logic signals to write the selected byte in data buffer 201. Directory 202 is also organized in four levels of 1,024 memory locations in each level. Each memory location stores an 8 bit row address. When 10 bit column address ADDR 08-17-10 inputs to director 202, four 8 bit row addresses ADDR 00-07-20,-21,-22 and -23 are read out of the four levels of directory 202 to four comparators 221 a-d. These row addresses are compared with the input row address ADDR 00-17-10 and if there is an equal, that "hit" line HIT 0+, HIT 1 +, HIT 2+ or HIT 3+ goes high gating the selected output of data buffer 201 through the appropriate 266a-j through 273a-j circuits through junction 216 to CPU2.

If a data word in data buffer 201 is to be replaced, round robin 224 selects the directory 202 and data buffer 201 level for replacement by setting 85 one of the level signals LEVEL 0-3+ high. 2:1 MUX selects this signal since logic signal REPLACE is high and logic signal WRTPLS- enables 2:1 MUX 223.

In an update mode the selected hit line 90 HITG-3+ is switched through 2:1 MUX 223 and inverted by inverter 255 to enable the selected level of data buffer 201 to write the data word DATA 00-19- into the selected column address ADDR 08-17-10.2:1 MUX 223 is enabled by logic signal WRTPLS-.

Round robin 224 has two, one bit by 1024 address random access memories (RAM). For each address location, there is stored 2 bits in each RAM which when decoded selects the next level of that column address to be replaced.

The directory 202 and data buffer 201 are designed using random access memory chips 93 LS 425 and round robin 224 is designed using random access memory chips 93 415, described on pages 7-119 and 7-70 respectively in the Bipolar Memory Data Book, copyright 1977, by Fairchild Camera and instrument Co. of Mountain View, California. Comparator 221 a-d logic circuits are made up of Fairchild TTL/MSI 93S47 high speed 6 bit identity comparator circuits. 2:1 MUX 208 and 223 are 75S1 57 logic circuits described on page 7-181 of the aforementioned TTL Data Book.

ADDRESS CONTROL UNIT 13 Figure 2, Sheet 2 Address control unit 13 includes the address register AOR 207, the replacement address file RAF206, an adder21 1, an AND gate 236, an AND gate 240, a NAND gate 241, an EXCLUSIVE OR gate 237, a 2:1 MUX 209, the read address multiplexer 233, a write address counter 234, and an AOR and RAF control unit 235. CPU2 address signal lines BAOR 05-22+ connect between interface 6 and one input of 2:1 MUX 209. Logic signal MEMREQ connects between NAND gate 241 and the select terminal of 2:1 MUX 209. Logic signal MEMREQ- and CYIDLTO- connect GB 2 055 233 A 8 between cycle control 232 and inputs to the NAND gate 241. The output of adder 211 signal lines AOR 05-22+ connects to the other input of 2:1 MUX 209 whose output signal lines BAOR 05-22 connects to the inputs of AOR 207 and RAF 206. Signal bus BAOR 05-22 +10 connects between the output of AOR 207 and the inputs to adder 211 and driver 212. AOR 207 is organized as an 18 bit register made up of conventional flops. RAF 206 is organized as four 18 bit registers and is designed using the aforementioned random access memory chips 75 LS 670. The logic signals ADDRRO and ADDRR1 connect between the write address counter 234 and RAF 206, AOR and RAF control 235, AND gate 236 and EXCLUSIVE OR gate 237. Logic signal CY12LTO- connects between cycle control 232 and an input to AND 236. The output of AND 236 connects to the +2 terminal of ADDER 211. The output of EXCLUSIVE OR 237 connects to the input of AND 240 whose output connects to the + 1 terminal of ADDER 211. Logic signal CY101-TO+ connects between cycle control 232 and the other input of AND 240. Logic signals ADDRWD+OB and ADDRWD+OA connect between the read address multiplexer 233 and RAF 206. The AORCNT logic signal connects between AOR and RAF control 235 and write address counter 234. Logic signals BAWRIT and BAORCK connect between AOR and RAF control 235 and RAF 206 and AOR 207 respectively.

For the interleaved memory operation the address control unit 13 logic loads AOR 207 with PRA, the CPU memory request address to send out on bus 5 to main memory 3 in a format 8b of Figure 8 during a first memory request cycle. AOR 207 is then loaded with PRA+1 which is the memory request address sent out on bus 5 to main memory 3 in the format 8b of Figure 8 during the second memory request cycle. RAF 206 is loaded with PRA, PRA+t PRA+2 and PRA+3 in successive locations under control of write address counter 234, adder 211 and AOR and RAF control 235. These addresses are supplied to the address field of LR 204 when information in the format 8c of Figure 8 are sent from main memory 3 to cache 1 over bus 5. For the banked memory operation, the address control unit 13 logic loads AOR 207 with PRA, the CPU2 memory request address, which is sent out on bus 5 to main memory.3 in the format 8b of Figure 8 during the memory request cycle. RAF 206 is loaded with PRA and PRA+ 1 in successive locations under control of the write address counter 234. These addresses are supplied to the address field of

LR204 when information in the format of Figure 8c are sent from main memory 3 to cache 1 over bus 5. The read address multiplexer 233 selects the RAF 206 address location to be read out of LR 204 for each main memory 3 response over bus 5 to the read request of cache 1. The adder 211 output signal lines AORO 05- 22+ provide the address stored in AOR 207 incremented by +1 or +2 under control of AND 236 and 237. If the write address counter 234 is set at location 03, logic c 9 GB 2 055 233 A 9 1. 1. 1 signals ADDRF10+ and ADDRR 1 + are high, therefore AND 236 enables the +2 input of adder 60 211. If the write address counter is set at locations 0 1 or 02 then the output of EXCLUSIVE OR 237 enables the + 1 input to adder 211. The adder 211 is a 75 283 logic circuit described on page 7- 415 of the aforementioned TTL Data Book.

During the QLT mode of the logic signal MLTO- input to AND 236 is low keeping the +2 input to ADDER 211 Low. Logic signal CY1ULTO+, the input to AND 240 enables the + 1 input to ADDER 211.

CACHE CPUE INTERFACE UNIT 6 Cache CPU Interface Unit 6 includes an 18 line address signal bus BAOR 05-22, a 20 line data signal bus CADPOO-1 9 and a control signal bus containing a number of signal lines. Two of the control signal lines, CACHRO, the CACHE request logic signal, and CYCADN, the cache done logic signal, are described herein.

SYSTEM BUS 5 CONTROL SIGNALS The signals listed below are the bus 5 control signals necessary to describe the invention.

Memory Reference (BSMREF) 13SMREF high indicates that the address leads 13SAD 05-22 contain a memory 3 word address.

BSMREr low indicates that the address leads 13SAD 08-23 contain a channel address and a function code.

Bus Write (BSWRIT) BSWRIT high indicates that a master unit is requesting a slave unit to execute a write cycle.

Second Half Bus Cycle (13SSHBC) 13SSHI3C high indicates that main memory 3 is 90 sending to cache 1 information previously requested by cache 1.

Double Pull (13SDI3PL) 13SDI3PI--- is high when sent from cache 1 to 95 main memory 3 to signal main memory 3 to read data in double pull mode. 13SDI3PI--- is high when sent from main memory 3 to cache 1 with the first word of a two word response to a memory request. 45 BSDBPL is low when sent from main memory 3 to cache 1 with the second word of a two word response io- the memory request. This enables main memory 3 to send one or two words to cache. If, for example, PRA is the high order address of a memory bank then 13SDI3PI--- will be low indicating that only one word will be transferred in response to the memory request.

My Acknowledge (MYACKR) MYACKR when high is sent by cache 1 to system bus 5 to indicate that cache 1 is accepting a system bus 5 data word transfer from main memory 3.

My Bus Request (MYREQT) MYREQT when high is set by cache 1 to system bus 5 to inaicate that cache 1 is requesting a system bus 5 cycle.

My Data Cycle Now (MYDC MYDCNN high indicates that cache 1 is transferring information over system bus 5 to. main memory 3.

Data Cycle Now (13SDCNN) 13SDCNN high indicates that main memory 3 has placed information on the bus 5 for use by cache 1 Acknowledge (13SACKR) 13SACKR high indicates to cache 1 that main memory 3 has accepted the memory request sent by cache 1.

Wait (BSWAIT) BSWAIT high indicates to cache 1 that main memory 3 is busy and cannot accept the memory request at this time.

Bus Request (BSREQT) BSREQT high indicates to cache 1 that a system coupled to bus 5 has requested a bus cycle.

Byte Mode (BSBYTE) BSBYTE high indicates a byte transfer rather than a word transfer.

Master Clear (CLEAR-) CLEAR- low initializes the cache by resetting the logic. When CLEAR- rises the QLT operation is started.

CLOCK CONTROL 220 - li;gure 3, Sheet 2 The cache request logic signal CACHRQ, Figure 3, connects to a RESET terminal of a FLOP 301 and to an input terminal of a NAND 302. A clock signal CLOCKO+ connects to the-CLK terminal of flop 301. The U output of flop 301 connects to the second input of NAND 302. THE CP-UREQ+OA output of a NAND 306 connects to the third input of NAND 302 whose output connects to an input of 30 ns delay line 303 and an input of NAND 304. The output of delay line 303 connects to the other input of NAND 304. The Q output of flop 301, logic signal BLKREQ+ connects to a D and RESET input of flop 305. The logic---1---signal connects to the SET intput of flop 305. A MYACKR logic signal connects to the CLK input of flop 305. The Q output signal INTERG+ connects to buffer bypass drivers 205 and the U-output signal INTERGconnects to the input of the IHTO-3+ NAND gates 266a-j to 273a-j in the cache directory and data buffer unit 12. Logic signal FEMPTY-20 connects to an input of AND 324 and'to the input of inverter 307. A logic signal MEIVIREQ connects to an input of NAND 306. A logic signal ADDRSO-, the U output of flop 309 1 j 7 1 1 GB 2 055 233 A 10 connects to another input of NAND 306. Logic signal CYQLTO+ connects between cycle control 232 and the third input of NAND 306. Logic signal ADDRSO+, the Q output of flop 309, connects to the select inpi!t of 2:1 MUX 208 in cache directory and data buffer unit 12. The output of NAND 308 connects to the SET terminal, CLOCKO+ connects to the CLK terminal and a general clear CLEAR signal connects to the reset terminal of flop 309.

Logic signals CYFIFO+OA and CYWRIT+OA connect to respective inputs of NAND 3081 A CPUREO, logic signal connects the NAND 304 output to a SFT terminal of flop 313. An FEMPTY- logic signal connects to a RESET terminal of flop 313 from an inverter 319 output.

Alioutput terminal logic signal FEMPTY+20 and a Q output logic signal FEMPTY-20 of flop 313 connect to the respective input of a NOR 310. A CYREAD logic signal connects between the Q output of a flop 330 and the third input of NOR 310 and CLOCKO+ connects to the fourth input of NOR 310. The output of NOR 310 connects to an input of NOR 311. The CLOCKO+ connects to an inverter 312 input. A CLOCKO- input signal of inverter 312 connects to an input of NAND 315.

Clock control 220 provides a timing signal CLOCKO+ to time the logic circuits of cache 1.

CLOCKO+ starts cycling on either a CPU2 memory request or by FIFO 203 being loaded with information from bus 5. In the case of the CPU2 memory request, logic signal CACHRQ, the input to NAND 302 is forced high, which sets the output low. The other two inputs to NAND 302 BLI(REQand CPUREQ+OA are high at this time. Flop 301 is not set so the Uoutput is high and both inputs to 100 NAND 306 are low so the output is high. When the output of NAND 302 goes low, one input of NAND 304 goes low and 30 nanoseconds later the other input goes low due to the delay in delay line 303. The delayed signal low sets logic signal 105 CPUREO. high. Logic signal CPUREG the SET input of flop 313 high sets the Q output FEMPTY-20 low. Flop 313 is a 74S74 logic circuit which has both the Q and CY outputs high when both the SET and PRESET inputs are low. Flop 74S74 is described on page 5-22 of the aforementioned 110 TTL Data Book.

The logic signal FEMPTY-20 low sets the output of NOR 310 high forcing the timing signal CLOCKO+ output of NOR 311 low. Fifty nanoseconds later, the output of delay line 314 115 forces the other input of NOR 311 low forcing timing signal CLOCKO+ high. Timing signal CLOCKO+ going high sets flop 301 setting the output logic signal BLKREQ- low, this forces the output of NAND 302 high forcing the NAND 304 120 output logic signal CPUREQ, the SET input to flop 313, low. This sets flop 313 and logic signal FEMPTY-20 is forced high keeping the timing signal CLOCKO+ output of NOR 311 high. Timing signal CLOCKO+ remains high as long as logic signal CACHRQ remains high. Logic signal CACHRQ will remain high until CP112 receives the requested data word and the cache done logic signal CYCADN is sent to CPU2.

Flop 313 which controls the start of cycling of CLOCKO+ is also controlled by the loading FIFO 205. The read address counter flops 316 and 317 in FIFO R/W control 230 advance to the next location after receiving acknowledged information from bus 5 (BSACKR high). This sets the output of comparator 318, logic signal FEMPTY+ low, setting the inverter 319 output logic signal FEMPTY- high. With the RESET input logic signal FEMPTY- of flop 313 high, the Q output logic signal FEMPTY+20 goes low starting the timing signal CLOCKO+ cycling as before. In this case, timing signal CLOCKO+ cycles as long as there is information in FIFO 203, and logic signal FEMTPY- keeps going low and logic signal CYREAD the input to NOR 310 is low. CPUREQ+OA output logic signal from NAND 306 stays low as long as the MEMREQ or ADDRSOinputs to NAN D 306 are high. This prevents a second CPL12 memory request cycle if logic signal CACHRQ is again high until the responses to the main memory 3 requests as a result of a previous CPU2 memory request is sent to cache 1. MYACKR logic signal going high at the start of the main memory 3 response to the CPL12 memory request sets flop 305, setting logic signal INTERG+ high to gate buffer bypass drivers 205 to send the CPU2 requested data (PRA) directly out on interface 6. INTERG- when high gates NAND 266a-j through 273a-j in cache directory and data buffer 12 to allow the selected word from data buffer 201 to be sent to CPU2 if the data word was stored in data buffer 201 when logic signal CACHRQ was set high. The logic signal FEMPTY+30 input to the SET terminal of flop 301 assures that the flop 301 does not set when logic signal CACHRQ comes high during a FIFO 203 cycle. Flops 301, 305 and 313 are 74S74 logic circuits described on page 5-22 of the aforementioned TTL Data Book. Flop 309 is a 74S 17 5 logic circuit described on page 5--46 of the TTL Data Book.

DETAILED DESCRIPTION OF FIFO R/W CONTROL 230 - Figure 3, Sheets 1 & 2

In Figure 3, the output of a NAND 324 connects to the SET input, a general clear signal CLEAR connects to the RESET input and timing signal CLOCKO+ connects to the CLK input of a flop 323. The Q output logic signal CYFI FO connects to a NAND 315 input. Timing signal CLOCKOconnects between the inverter 312 output and the other input of NAND 315. The Q output, logic signal CYFIFO also connects to cycle control 232. TheTI output connects to the input of AND 324. Logic signal FEMPTY-20 connects to the other input of AND 324. Logic signal FEMPTY-20 connects to the other input of AND 324. A BUMPUP logic signal output of NAND 315 connects to the CLK inputs, and CLEAR connects to the RESET inputs of flops 316 and 317. The logic - 1 signals connect to the J, K and PRESET inputs of flop 316, and the PRESET input of flop 317. The Q output of flop 316 connects to the J :i X 11 I GB 2 055 233 A 11 1 and K inputs of flop 317 and to a comparator 318 input.The Q output of flop 317 connects to comparator 318. The U outputs of flop 316 and 317 connect to the read address select terminals 5 of FIFO 203. A MYACKR+ logic signal and a BSSHBC logic signal connect to NAND 322 whose output, logic signal F plus 1 connects to the CLK inputs of flops 320 and 321. CLEAR logic signals connect to the RESET inputs of flops 320 and 321. Logic '1 -signals connect to the J, K and PRESET inputs of flop 320 and the PRESET input of flop 32 1. The Q output of flop 320 connects to comparator 318 and the J and K input of flop 32 1. The Q output of flop 321 connects to comparator 318. The Uoutputs of flops 320 and 321 connect to the write address select terminals of FIFO 203. FIFO 41 + logic signal connects to the read enable terminals of address field FIFO bit positions 60-17 of FIFO 203. A ground signal connects to the read enable terminals of the data and control field FIFO bit positions 18-43 of FIFO 203. FIFO 41 + connects to the SET input of LR 204 replaceupdate bit position 41 flop. Logic signals CYFIFO and REPLACE connect to input terminals of NOR

325 whose output connects to a NOR 327, whose output logic signal CYWRIT+ DA connects to the SET input of flop 330 and an input of NAND 308. Timing signal CLOCKO+ connects to the CLK terminal, and CLEAR connects to the RESET terminal of flop 330 whose Q output, logic signal CYWRIT, connects to 2:1 MUX 223 and whose output logic signal CYREAD connects to round robin 224 and an input to NOR 310. Logic signal BSDCNN+ connects to the input of an inverter 326 whose output connects to the inputs of delay lines 328 and 329. Delay line 328 output connects to an input of inverter 331 whose output connects to an input of NAND 332. The output of delay line 329 connects to the other input of NAND 332 whose output logic signal FWRITE connects to the write enable terminal of FIFO 203.

Logic signal NOHIT+ connects to an input of inverter 334 whose output logic signal NOHIT connects to an input of a NOR 340 and to an input of NOR 333 whose output connects to the other 110 input of NOR 327. Logic signals CYFIFO and UPDATE connect to the other inputs of NOR 333.

Logic signal CY01-TO- connects between cycle control 232 and the input to NOR 340 whose output connects to an input of NOR 325.

Bus 5 logic signals 13SACKR, BSWRIT and 13SIVIREF connect between receiver 217 and a NAND 337 whose output connects to a NOR 336 whose output logic signal FPLUS 'I connects to the CLK inputs of flops 320 and 32 1. The output of NAND 322 connects to the other input of NOR 336.

Logic signal BSDCNN+ goes high at the start of every main memory 3 to cache 1 data transfer cycle, is inverted by inverter 326, is delayed 10 nanoseconds by delay line 328, and is again inverted by inverter 331 appearing at the first input of NAND 332 as a delayed positive logic signal. The output of delay line 329 is a negative going logic signal appearing at the second input of NAND 332 delayed 40 nanoseconds. The 2 inputs to NAND 332 are positive for 30 nanoseconds forcing the FWRITE write enable input to a negative going pulse 30 nanoseconds wide, delayed 10 nanoseconds from the rise of BSDCNN +. This strobes the bus 5 information at the output of receivers 213, 215 and 217 into a location of FIFO 203 defined by the Q outputs of the write address flops 320 and 321 logic signals FWADDR- and FW13DDR, MYACKR goes high, if a cache identificati on AND 546 output, figure 5, goes high indicating that cache ID 0002. was received from bus 5 through receiver 213 and that this is not a main memory 3 write operation.

When BSI)MN+ delayed 60 nanoseconds by delay line 522 goes high, flop 516 sets and logic signal MYACKR, the input to NAND 322 goes high. Since this is a response to a memory request, BSSHBC is high forcing the output of NAND 322 logic signal F PLUS 1 low. Forcing the CLK inputs of flops 320 and 321 low increments the write address counter flops 320 and 32 1. Since the output logic signals FWADDR+ and FWI3DDR+, of the write address counter flops 320 and 321 and logic signals FRADDR+ and FR13DDR+, outputs of the rebd address counter flops 316 and 317 are no longer equal, logic signal FIEMPTY+, the output of comparator 318 goes low, starting CLOCKO+ cycles as previously described in Clock Control 220.

Write address counter flops 320 and 321 and read address counter flops 316 and 317 are conventional X flops 74S l 12 described on page 5-24 of the aforementioned TTL Data Book and they operate in the following manner. Assume flops 320 and 321 are both reset, that is the (7 outputs FWADDRand FW13DDR- are high. When FPLUS 1 goes low, flop 320 sets on the fall of logic signal FPLUS 1. The Q output of flop 320 being low kept flop 321 reset. With flop 320 set and its Q output high, flop 320 resets and flop 321 sets on the next fall of logic signal FPLUS 1. On the next fall of logic signal FPLUS 1, both flops 320 and 321 are set and on the fourth fall of logic signal FPLUS 1, both flops are reset. The rise of CLOCKO+ sets flop 323 and its Q output, logic signal CYFIFO goes high. When CLOCKO+ next goes low, both logic signals CYFIFID and CLOCKO- input to NAND 315, go high forcing the output logic signal BUMPUP low, advancing the read address counter flops 316 and 317. The inputs to comparator 318 signals FWADDR+ and M13DDR+ are equal to FRADDR+ and FR13DDR+ thereby setting FEMPTY+ high. This prevents timing signal CLOCKO+ from cycling if no bus 5 cycle logic signal BSDCNN+ is present. Logic signal FEMPTY+ is inverted by inverter 319 and the output logic signal FEMPTY- going low sets the FEMPTY+20 output of flop 313 high, forcing the output of NOR 310 low, forcing the CLOCKO+.output of NOR 311 high. Logic signal CYFIFO, Figure 2, going high sets the FIFO 203 output of the location indicated by the read address counter flops 316 and 317 (FRADDR- and FRBDDR-) into LR 204. If the information in FIFO 203 is a 12 GB 2 055 233 A 12 response to a memory request, FIFO 41 + is high. This sets LR 204, F/F 41, Figure 3, so that its Q output, logic signal REPLACE is high. The output of NOR 340 is high during the OLT mode since the logic signal CYOLTO- is low. This sets the output of NOR 325 low and the output of NOR 327 high, so that at the next rise of CLOCKO+, flop 330 sets and the Q output logic signal CYWRIT goes high and continues cycling under control of the logic signal CYFIFO input to NOR 325 for the remainder of the OLT operation.

During normal operation, logic signal CYQLTO-, the input to NOR 340 is high. Therefore, in a replacement mode with logic signals REPLACE and CYFIFO high if the directory 202 search results in a "NO HIT", then-the 3 inputs to NOR 325 are high, its output is low setting the output of inverter 327 high, so that at the next rise of CLOCKO+, flop.330 sets and the Q output logic signal CYWRIT goes high indicating that this is a cache write cycle. Flop 309 of clock control 220 was previously set since CYWRIT+OA 85 and CYFIFO+OA were low in previous cycles setting the Q output ADDRSO+ high, switching 2:1 MUX 208 Figure 2, to receive memory address BAOR 05-22+. At the rise of CLOCKO+, logic signal CYFIFO+OA is high, since flop 323 is not set and the-U output which is high inputs AND 324. The FEMPTY-20 input to AND 324 is also high, forcing the CYFI FO+OA input to NAN D 308 high, setting the output low. Since the SET input to flop 309 is low, the Q output ADDRSO+ goes low, switching 2:1 MUX 208, Figure 2, to receive the FIFO 00-17+ address output from LR 204. 5 Flop 323 when set is reset on the next rise of CLOCKO+ since the ?!output which inputs AND 324 is low, forcing the SET input of flop 323 low, resetting flop 323 and the Q output logic signal CYFIFO goes low.

During an update operation logic signal UPDATE, an input to NOR 333 is high. If the directory 202 indicates a "hit" then the output of 105 inverter 334, logic signal NO HIT- is high. When logic signal CYFIFO is high, the 3 inputs to NOR 333 are high forcing the output low forcing the output of NOR 327 high. At the next rise of timing signal CLOCKO+, flop 330, sets as before indicating a cache write cycle.

Flops 323 and 330 are 74S175 logic circuits described on page 5-46 of the aforementioned TTL Data Book.

DETAILED DESCRIPTION OF AOR AND RAF

CONTROL235 FIGURE 4, SHEET 1 READ ADDRESS MULTIPLEXER 233 AND WRITE ADDRESS COUNTER 234 FIGURE 4, SHEET 2 The outputs of a NAND 417 and 418 connects to NOR 419 inputs. Logic signal BLOCKF+ connects between a NAND 417 and cycle control 125 232. Logic signal FEMPTY-20 connects between clock control 220 and an input to a NOR 442 whose output connects to the 3rd input of NOR 419. The output of NOR 419, logic signal AORCNT, connects to the inputs of delay lines 420 and 421, an input of a NAND 424 and an input to a NAND 416. Logic signals MEMREQand CYQ1-TO+ connect between cycle control 232 and inputs to a NAND 441. Logic signal CYFIFO connects between FIFO R/W control 230 and another input of NAND 441 whose output connects to an input of NOR 442. Logic signals CYQLTO-1 A and CYGLTO-013 connect between cycle control 232 and inputs to a NAND 443 whose output connects to an input of NOR 419.

The output of NAND 424, logic signal BAORCK connects to the AOR 207. The delay line 421 output connects to an inverter 423 input whose output logic signal AORCNT-30 connect to the CLK inputs of flip 426 and 427. The delay line 420 output connects to an inverter 422 input whose output connects to inputs of NAND 416 and NAND 424. Logic signal BAWRIT connects between the output of NAND 416, the input of NAND 425, and the WRITE strobe terminal of RAF 206. Logic signal MEMREQ connects to NAND 425 input, the RESET input flops 412 and 413 and cycle control 232. The output of NAND 425 connects to the reset terminals of flops 426 and 427 and the J and K inputs of flop 427. The Q output of flop 426, logic signal ADDRRO+ connects to the Write Address terminal 2 of RAF 206 and connects to the input of NAND 418. Logic signa.1 MYACKR connects between another input of NAND 418 and cycle control 232. TheU output of flop 426 logic signal ADDRRO- connects to the inputs of NAND 417 and NAND 424. The Q output of flop 427, logic signal ADDRRI+ connects to the Write Address terminal 1 of RAF 206 and the input of NAND 417. Logic signal 13SDCND+ connects between cycle control 232 and the CLK terminal of a flop 409. Logic signal BSAD 23+ connects to the SET input of flop 409 and the output of Receiver 217. Logic signal MYACKI) connects between cycle control 232 and input of NAND 410 and 411. The Q output of flop 409, logic signal BSAD 23+10, connects to the other input of NAND 410. The Cl output of flop 409, logic signal BSAD 23-10, connects to the other input of NAND 411. The output of NAND 410 connects to the CLK terminal of flop 412 and the output of NAND 411 connects to the CLK terminal of flop 413. Logic---1---signal connects to the PRESET, J and K terminals of flops 412 and 413.

The Q output of flop 412, logic signal FCHONE+ connects to the input of FIFO bit position 43 of FIFO 203, figure 4. The Q output of flop 413, logic signal FCO+, connects to the input of the FIFO bit position 42 of FIFO 203. Logic signal 13SAD23+ connects to the input of the FIFO bit position 18 of FIFO 203. The output of the FIFO bit position 18 connects to a select terminal 1 of MUX 414 and 415. The MUKs are 74 S '153 dual 4 lines to 1 line Data Selectors/Multiplexers described on page 5-42 of the aforementioned TTL Data Book. Terminal 1 of a Banked interleaved select switch 407 is connected to ground. Terminal 2 is connected to logic '1 ".

13 GB 2 055 233 A 13 Logic signal BANKED+00 connects between terminal 3 and an input to inverter 408 whose output logic signal ADDRWD+ connects to select terminal 2 of 4:1 MUX 414 and 415. Logic signal BANKED+00 also connects to cycle control 232. The enable input and the terminal 2 input of 4:1 MUX 414 are connected to ground as is the enable input and the terminal 0 input of 4:1 MUX 415. Input 3 of 4:1 MUX 414 and input 1 of 4:1 MUX 415 are connected to logic "'I". Input 0 of 4:1 MUX 414 and input 2 of 4:1 MUX 415 connect to the FIFO bit position 42 output of FIFO 203 and input 1 of 4:1 MUX 414 and input 3 of 4:1 MUX 415 connect to the FIFO bit position 42 output of FIFO 203. The outputs of MUX 414 and 415, logic signals ADDRWD+ OB and ADDRWD+OA connect to the Read Address terminals 1 and 2 respectively of RAF 206 and also connect to cycle control 232. Logic signal FIFO 41 - connects to the read enable input of RAF 206. Logic signal BSDCNB+ connects between the RESET input of flop 409 and cycle control 232.

During normal operation for both banked and interleaved memories the first memory request is sent to main memory 3 over bus 5 and an acknowledge signal BSACKR returned by main memory 3 to cache 1 over bus 5 sets logic signal BLOCKF+ high, figure 5. When BLOCKF+ goes high the 3 inputs to NAND 417, figure 4, are high setting the output low. This sets the output of NOR 419 logic signal AORMT high which sets logic signal BAWRIT, the RAF 206 write strobe, and logic signal BAORCK the AOR 207 strobe low, as described supra. This sets PRA+1 into AOR 207 and location 0 1 of RAF 206. Logic signal AORCNT-30 going low as before advances the write address counter 234 to location 02. For location 01 logic signal ADDRRI+ is high and logic signal ADDRO+ is set low. The fall of logic signa Is AORCNT-30 sets logic signal ADDRRO+ high and sets ADDRRI+ low and the Write Address Counter 234 addresses location 02. The banked memory system now awaits the main memory 3 response to ihe first memory request whereas the When CACHRQ, Figure 3, goes high indicating interleaved memory system sends a second that CPU2 is requesting a data word and CPU2 memory request.

also sends the main memory 3 address location 90 At the end of the second memory request cycle BAOR 05-22+, Figure 2, of the requested data logic signal MYACKR+, figure 4, goes high to start word, the address BAOR 05-22 (PRA) appears at the first main memory 3 to cache 1 data response the inputs of AOR 207 and location 00 of RAF cycle. Since logic signal ADDRRO+ is also high the 206. In addition, the address is sent to directory output of NAND 418 goes low setting logic signal 202 and data buffer 201 as row address 95 AORCNT, the output of NOR 419 high. As ADDROO-07-1 0 and column address ADDR previously described, logic signal DAWRIT goes 08-17-10.2:1 MUX 208 is switched by low setting PRA+2 into location 02 of RAF. In ADDRSO+ high to input BAOR 05-22+ and a figure 2, PRA+1 remains stored in AOR 207.

directory 202 search is started. When When the Write Address Counter 234 is set at FEMPTY-20, the output of flop 313, Figure 3, 100 location 02 the output logic signals ADDRRO+ goes low the AORMT output of NOR 419, Figure high and ADDFIR 1 + low results in the + 1 output 4, goes high, one input to NAND 416 and 424 from EXCLUSIVE OR 236. Since PRA+1 is applied high. Since the other inputs to NAND 416 and to the input of ADDER 211 the output of ADDER 424 are high logic signals BAWRIT and BAORCK 211 puts PRA+2 on the address signal lines, go low. 50 nanoseconds later the output of delay 105 AORO 05-22+ and BAOR 05-22, the output of line 420 goes high setting the output of inverter 2:1 MUX 200. Note that logic signal BAORCK the 422 low, setting the outputs of NAND 416 and write strobe for AOR 207 is not set low since the 424 logic signals BAWRIT and BAORCK high. PRA logic signal ADDRRO- input to NAND 424 is low.

is strobed into AOR 207 and into location 00 of The Write Address Counter 234 is advanced to RAF 206 when BAWRIT and BAORCK are low. 110 location 03 when AORCNT-30 goes low as Logic signal AORMT going high is delayed 70 described supra and logic signal ADDRRO+ and nanoseconds by delay line 421 and is inverted by ADDRR 'I + are both set high. This results in the +2 inverter 423. Inverter 423 output logic signal output of AND 236, figure 2, going high which AORCNT-30 going low advances Write Address sets the output of ADDER 211 to PRA+3. Logic Counter 234to location 01. The Write Address 115 signal MYACKR again comes high at the start of Counter is made up of JK flops 426 and 427 the second main memory 3 to cache 1 data word whose operation bias been described supra. Logic cycle in response to the first memory request signal ADDRRI+ is now high and ADDRRO+ is low again forcing logic signal AORMT high. This setting the Write Address in RAF 206 to location 'forces logic signal BAWRIT low and forces PRA+3 01. Assuming the data requested by CPU2 of 120 into location 03 of RAF 206 and advances the Cache 1 is not stored in Cache 1 then MEMREG+, Write Address Counter 234 to location 00.

figure 5, is forced high. In figure 2 logic signal For an interleaved memory 4 data words are MEMREQ- low forces the output of NAND 241 transferred from main memory 3 to cache 1 over high which transfers 2:1 MUX 209 to receive the bus 5 on 4 separate bus 5 cycles. Figure 8c shows AOR005-22+ output of ADDER 211. Since logic 125 the format of the responses. The low order bit signal ADDRRI+ is high and logic signal ADDRO+ BSAD23 of the Function Code identifies whether is low, the +1 output of EXCLUSIVE OR 237 is the data word is in response to the first memory high forcing PRA+ 1 on the address signal lines request or the second memory request for data AOR005-22+ and on the 2:1 MUX 209 output words. Logic signal 13SAD 23+ and the Function signal lines BAOR 05-22. 130 Code history flops 412 and 413 identify the 14 GB 2 055 233 A 14 location of RAF 206 that stores the main memory 3 address for the data word being transferred. The first data word is at the PRA main memory 3 location and transfers from main memory 3 cache 1 with the Function Code wet to 00, BSAD 23+ the low order bit of Function Code 00, is low and sets into FIFO bit position 18 of FIFO 203 figure 2, when the FIFO strobe FWRITE- goes low. Also, at this time the function history flops 412 and 413 are not set and the output logic signals FCHZRO+ and FCHONE+ are low setting the FIFO 42 and FIFO 43 bit positions low. With Switch 407 set to interleaved, the input to inverter 408 logic signal BANKED is low setting the output logic signal ADDRWD+ high, setting the SELECT terminal 2 high. This sets the 2 and 3 input terminals of 4:1 MUX 414 and 415 active. FIFO 18 sets SELECT terminal 1 of 4:1 MUX 414 and 415 low setting input 2 active. Since FIFO 42 is low the outputs of 4:1 MUX 414 and 415 logic signals ADDRWD+OB and ADDRWD+OA are low which set the read address of RAF 206 to location 00 and PRA appears of address signal lines AORO 05-22, figure 2, and is strobed into LR 204 when logic signal CYFIFO goes high. BSAD 23+ is low the G output of flop 409 which inputs NAND 411 goes high. Since BSAD 23+ is low the G output which inputs NAND 411 goes high, when logic signal BSDCND+ goes high. When logic signal MYACKD, the input of NAND 411 goes high the output of NAND 411 goes low setting flop 413 with the 0 output signal FCHZRO+ high.

On the next bus 5 cycle the data word PRA+2- location in main memory 3 is transferred to cache 1 and the Function Code on bus 5 signal lines BSAD 18-23 is still 00 and BSAD 23+ the low order bit is low. In this case, in figure 4, FIFO bit position 18 of FIFO 203 is set low and FIFO bit position 42 is high, since flop 413 is set with the Q output logic signal FCHRZO+ high. The outputs of 4:1 MUX 414 and 415, logic signal ADDRWD+OB is low and logic signal ADDRWD+OA is high since the 2 input terminal of 4:1 MUX 414 is -0- and the 2 input terminal of 110 4:1 MUX 415 is a -1 ", thereby resulting in that reading out location 02 qf RAF 206 which has the PRA+2 address stored.

The third data word transfer cycle over bus 5 brings the data word from the PRA+ 1 main memory 3 location with a Function Code or 018- In this case, BSAD 23+ is high and FIFO bit position 18 of FIFO 203, figure 4, is high setting the 3 input terminal of 4:1 MUX 414 and 415 active.

FIFO bit position 43 is low and FIFO bit position 42 is a "don't care". In this case with FIFO 18 high the ADDRWD+OB output of flop 414 is high and the ADDRWD+OA output of flop 415 is low reading out from RAF 206 location 0 1 which contains PRA+1. BSAD 23 high causes flop 409 125 to set when logic signal BSDCND+ goes high, setting the Q output logic signal BSAD23+1 0 high forcing the output of NAND 410 low when logic signal MYACKD+ goes high. This sets flop 412 and its Q output logic signal FCHONE+ goes high. 130 The 4th bus 5 cycle bringing the data word from the PRA+3 location in main memory 3 has a Function Code of 01. BSAD 23 high as before sets FIFO bit position 18 high and FIFO bit position 43 is set high since logic signal FCHONE+ is high.

The output of 4:1 MUX 414 and 415 logic signals ADDRWD+OB and ADDR+0A are high reading out RAF 206 location 03 which stores PRA+3. Flops 412 and 413 are reset when logic signal MEIVIREQ+ goes low.

For a banked memory, two data words are tranferred from main memory 3 to cache 1 over bus 5 on two separate bus 5 cycles. In this case, switch 407 is set io terminal 2 (banked), setting the input of inverter 408 high, forcing the output logic signal ADDRWD+ low. Also for the banked memory, the function code is 00. as the response to the memory request. Therefore, BSAD23+ is low for both data words sent to cache 1 from main memory 3 over bus 5. FIFO bit position 18 of FI FO 203 is therefore low for both data words. The select inputs of 4:1 MUX 414 and 415 of terminals 1 and 2 are both low thereby acti ' vatipg input termina10, When the first data word is read into FIFO 203 from bus 5, logic signals ADDRWD+OB and ADDRW13+0A are both low and PRA stored in location 00 is read out of RAF 206. Then, when logic signal MYACKD is forced high, the output of NAND 411 goes low, -95 setting flop 413. BSAD23-1 O-Tthe output of flop 409 is high at this time. The Q output FCHMO+ flop 413 high is stored in FIFO bit position 42 on the next FWRITE enable pulse of -FIFU 203. This forces the output of 4:1 MUX 414 ADDRW13+013 high, so that the address in RAF 206 location 01 (PRA+1) is transferred to LR 204 with the second data word in response to the memory request.

Flops 412,413,426 and 427 are 74S1 12 logic circuits described on page 5-34 and flop 409 is a 74S1 75 logic circuit described on page 5-46 of the aforementioned TTL Data Book.

In the initialization mode, the CLEAR- logic.signal initialises the contents of AOR 207 to all zeros. This forces the adder 211 output to all, zeros. Therefore, when the strobe signals BAOROCK and BAWRIT are forced low the adder 211 output of all zeros is written into AOR 207 and RAF 206 location 00.

In the Q1t mode the RAF write strobe BAWRIT and the AOR write strobe BAORCK are forced low when the 2 inputs to NAND 443 are forced low when the 2 inputs to NAND 443, logic signal CYQLTO-1 A and CYQLT0+013 are high. This forces the output of NAND 443 low, forcing the output of NOR 419, logic signal AORMT high. As previously discussed, write strobes BAWRIT and BAORCK are forced low. This sets PRA address location 0000 into AOR 207 and location 00 of RAF 206. Th.e RAF Write Address Counter 234 is advanced to location 01 when logic signal AORCNT-30, the output of inverter 423 is forced low. Logic signals ADDRI1 1 +, the Q output of flop 427 and ADDRRO-, the Q output of flop 426 are set high. This forces the +1 terminal of ADDER 4 GB 2 055 233 A 15 211, the output of EXCLUSIVE OR 237 high and signal lines AORO 05-22+, the outputs of ADDER 211 are forced to hexadecimal 0001.

When logic signal BLOCKF+, the input to NAND 417, is forced high the 3 inputs to NAND 417, figure 4, are high and the output is forced low forcing logic signal AORCNT, the output of NOR 419. This forces write strobes BAWRIT and BAORCK low setting address location 0001 into RAF 206 location 01 and AOR 207. The write address counter 234 then advances to location 02. The Q output of flop 426, logic signal ADDRRO+ is set high and logic signal ADDRR 'I +, the Q output of flop 427 is set low, in figure 2 the output of EXCLUSIVE OR 237 logic signal +1 again goes high forcing the output of ADDER 211, signal lines AORO 05-22+ to 0002.

When MYACKR+ the input to NAND 418, - figure 4, goes high, the output is forced low, forcing logic signal AORMT, the output of NOR 419 high. In this case, write strobe address BAORCK remains high since the input to NAND 424, logic signal ADDRRO- is low. Write strobe BAWRIT is forced low setting 000,002. into location 02 of RAF 206. Write address counter 234 is advanced to location 03. Logic signal MYACKR+ again goes high and address location 0002 is stored in location 03 of RAF 206 and the write address counter is advanced to location 00. 30 Locations 02 and 03 of RAF 206 are considered "dummy" locations and are not used in the QLT mode. When the inputs to NAND 41, logic signals MEMREQ-, CYQLTO+ and CYFIFO are high, the output is low forcing the output of NOR 442 low, forcing logic signal A0FICNT, the output of NOR 419 high. This sets address location 0002 into AOR 207 and RAF 206 location 00 and advances the write address counter 234 to location 01. 40 The above sequence continues until address location 4096 is set into AOR 207 and RAF 206 105 and the OLT operation is concluded. Logic signal ADDRWD+, the output of NOR 408 remains high for the QLT mode since the input, logic signal MI-TO- remains low. This forces terminals 2 of 4:1 MUX 414 and 415 high, 110 since FIFO bit position 18 of FIFO 203, figure 4, remains low. Select terminals 1 or 4:1 MUX 414 and 415 are forced low. Therefore, input terminal 2 of 4:1 MUX 414 and 415 are active since select terminal 1 is low and select terminal 2 is high.

DETAILED DESCRIPTION OF CYCLE CONTROL

232 - Figure 5, Sheets 1 & 2 Logic signals MYACKD, BS1)13PL-, BSWAIT, MYMNN+, MEIVIREQ+, BSDCND-, 13SACKR, CLEAR- and CI-FIREQ-0A connect to system bus control 219. MEMREQ- connects to AOR and RAF control 235 and address control unit 13. Logic signals CYFIFO, CYREAD+ and FEMPTY+30 connect to FIFO R/W control 230. Logic signal NO 125 HIT+ connects to directory 202. Logic signal MYACKD connects to an input of NAND 506 and BSDBPL- connects to the other input of NAND 506 whose output connects to an input of NOR 507 whose output, logic signal DATACKconnects to the CLOCK inputs of flops 508 and 509. Logic signal BSWAIT connects to an input of NAND 505 and MYMNN+ connects to another input of NAND 505 and a SET input to flop 504.

Logic signal BLOCKF+ connects between the Q output of flop 504 and a third input to NAND 505 whose output connects to the other input of NOR 507. Logic signal 13SACKFI connects to the CLOCK input of flop 504 whose iloutput logic signal BLOCKF- connects to an input to NOR 536. Logic signals CYQLTO-, NOHIT+, CYREAD+, and FEMPTY+30 connects to the inputs of NOR 501 whose output connects to an input of NOR 502 whose output connects to the D input of flop 503.

Logic signal CY13LTO+M connects between a NOR 565 output and the PRESET input of flop 503. TheU output of flop 503, logic signal MEMREQ-, connects to an input of NOR 502 and logic signal MEMI1EQ+OC connects to another input of NOR 502. The CLOCKO+ signal connects to the CLK input of flop 503 whose Q output logic signal MEMREQ+ connects to the RESET inputs of flops 508, 509 and 504. Logic---1 " connects to the SET input of flop 508 whose Q output, logic signal DATCTO, connects to the SET input of flop 509 whose Q output, logic signal DATCTI, connects to an input of NAND 510 whose output, logic signal MEMREQ RESET, connects to the input of a NOR 566 whose output connects to the RESET input of flop 503. Logic signal CLEARconnects between system bus control 219 and the other input of NOR 566.

Logic signals ADDFl+0A and ADDR+013 connect to the inputs of their respective inverters 523 and 524 whose outputs, logic signals ADDRM-0A and ADDRW13-013 connect to the inputs of AND 533 whose output connects to an input of NOR 527. FIF041 + connects to another input of NOR 527. Logic signal FEMPTY+30 connects to inputs of NOR 526 and Inverter 534 whose output logic signal FEMPTY-30 connects to another input of NOR 527. Logic signal CYREAD connects to inputs of NOR 526 and 527. Logic signal NOHIT+ connects to-an inverter 525 input whose output whose logic signal CAHIT connects to an input of NOR 526. The outputs of NOR 526 and 527 connect totheir respective inputs of NOR 528 whose output connects to the D input of flop 529. The Q output of flop 529 logic signal CYCADN+, connects to inputs of inverters 520 and 532. The output of Inverter 530 connects to the input of Delay line 531 whose output connects to the RESET terminal of flop 529. The output of Inverter 532, logic signal CYCADN- connects to cache CPU interface unit 6. CLOCKO+ connects to the CLK input of flop 529.

Logic signal BANKED+ connects between AOR and RAF control 235 and an input of a NAND 560 whose output connects to the input of NOR 5 - 36 and the PRESET input of flop 508. Logic signal CYOLTO- connects to the other input of NAND 560. CYFIFO connects to the other input of NAND 510. Logic signals CYQLTO+ and CLEAR- connect to inputs of a NAND 561 16 whose output connects to inputs of delay lines 562 and 563 and an inverter 567a. The output of delay line 562 logic signal CYQLT0+013 connects to the input of an inverter 564 and to AOR and RAF control 235. The output of inverter 564, logic 70 signal CYQLTO-1 B connects to an input of a NOR 565 whose output logic signal CYQLT0+01) connects to the PRESET input of flop 503. The output of delay line 563, logic signal CYQLTO+OC connects to the other input of NOR 565. The output of inverter 567, logic signal CYGLTO-1 A connects to AOR and RAF control 235.

Logic signals REPLACE and FIFO 17+ connect between inputs of an AND 567 and LR 204. Logic signal CYWRIT connects between FIFO RW control 230 and the 3rd input of AND 567 whose output, logic signal, MEIVIREQ+0i) connects between the input of a NOR 569 and a NAND. 570. The output of NOR 569 logic signal MEIVIREQ+OC connects to an input of a NOR 502.

Logic signal BAOR 10+ 10 connects between AOR 207, the input of an inverter 568 and the other input to NAND 570. The output of inverter 568, logic signal QLTDUN- connects to another input of NOR 569. The output of NAND 570 connects to 90 the RESET input of a flop 57 1. Logic signal 1 connects to the PRESET and D inputs and logic signal CLEAR- connects between system bus control 219 and the CLK input of flop 57 1. The Q output logic signal CYQLTO+ connects to the round robin 224 and the 3rd input of NOR 569 and the7Toutput, logic signal CYQ1-TO- connects to an input of AND 533. Logic signal CI-RI1EQ+013 connects between the output of NOR 536 and an input of NAND 535. Logic signals MYXNN+ and 13SDCNDconnect to the other inputs of NAND 535.

During the normal CPU2 request mode the first memory request cycle flop 503 sets on the rise of CLOCKO+ if the CPU2 requested address PRA is not stored in the directory 202. The output of NAND 23 1, figure 2, logic signal NO HIT+ is high forcing the output of NOR 501, figure 5 low, forcing the output of NOR 502 high setting flop 503. The Q output logic signal MEMREQ+ going high sets the cycle request flop 511 of system bus control 219 to request a bus 5 cycle. The acknowledge response from main memory 3, logic signal 13SACKR going high sets flop 504 whose Q output BLOCKF+ inputs the AOR and RAF control 115 235; this operation is described supra.

If there is a -hit- during the first memory request cycle, the logic signal NO HIT+ input to inverter 525 is low, setting the logic signal CAHIT input to NOR 526 high setting the input to NOR 528 low, setting the D input to flop 529 high. FEMPTY+30 is high at this time since FIFO 203 is empty. On the rise of timing signal CLOCKO+ flop 529 sets and the Q output logic signal CYCADN+ goes high forcing the output of inverter logic signal CYCADN- low which signals CPU2 that the requested data is available. Logic signal CYCADN+ is inverted by inverter 530, dblayed 25 ns. by delay line 531 and resets flop 529. If there was not a "hit" in the first memory request cycle GB 2 055 233 A 16 then during the cycle that sends the PRA data word from main memory 3 to cache 1 over bus 5, CYCADN+ is again set high as follows. The Read Address Multiplexer 233, figure 2, output logic signals ADDRW13+0B and ADDRW13+0A are low and are forced high by inverters 523 and 524 which set the output of AND 533 high, setting the output of NOR 527 low, setting the output of NOR 528 high, setting flop 529 as before. At this time FIFO 203 is not empty, and CYREAD is high since logic signal CYFIFO, figure 3, has not cycled high.

Flops 508 and 09 are configured as a counter. For an interleaved memory, logic signal MYACKD goes high during each bus 5 cycle where the data word is sent from main memory 3 to cache 1 over bus 5 in response to a CPU2 request. Logic signal BS1313PL- goes low for the 2nd word of the 2 word response or if only 6ne word is sent from main memory 3 to cache 1 over bus 5. Only one word may be sent to cache 1 if main memory 3 was busy to the 2nd word request from cache 1. This sets the output of NAND 506 low, forcing the output of NOR 507 logic signal DATACK- low setting flop 508 in response to the 2nd word received from main memory 3. DATACK- goes low for the 4th word since MYACKD and 13SD13PL- are again high setting flop 509 since the SET input logic signal DATCTO is high. The Q output of flop 509, logic signal DATCTI, going high sets the output of NAND 510, logic signal MEIVIREQ RESET low, resetting flop 503 through NOR 566. CLEAR- the other input to NOR 566 - going low also resets flop 503. Flop 503 was held set through the logic signal MEMREQ- input to NOR 502 set low. This kept the SET input of flop 503 high at every rise of CLOCKO+. If the main memory 3 response to the 2nd memory request was logic signal BSWAIT high then the output of NAND 505 goes low forcing DATACK-, the output of OR 507 low thereby setting flop 508. Since the 2nd memory request is aborted if the main memory 3 response is BSWAIT, the Data Counter flop 508 must be set since only 2 data words will be received from main memory 3.

For the banked memory, the input to NAND 560, logic signal BANKED+, is high setting the output low which sets the PRESET input of flop 508 low setting the Q output, logic signal DATCTO, high. Since the banked memory system only makes one memory request and cache 1 received 2 data words in response;the Zind data word in response will set flop 509 as above and reset flop 503. Logic signal MEMREQ+ going low resets flops 504, 508 and 509.

During a system initialization cycle, logic signal CLEAR- is transferred over bus 5 to receiver 217, figure 2, as a negative going pulse which sets flop 57 1, figure 2, on the rise of the trailing edge. This sets logic signal CYUTO+ high and logic signal CY01-TO-low.

The output of NOR 561 is normally high. When logic signals CLEAR- and CYQLTO+, the inputs to NOR 561 are high, the output is forced low. 160 ns. later, the output of delay line 562, logic signal CY0LT0+013 is forced low which forces the output 19 17 GB 2 055 233 A 17 1.

of inverter 564, logic signal CYQLTO-1 B high. This signal inputs NOR 565. The other input to NOR 565, logic signal CYGI-TO+OC, the output of delay line 563 is high at this thime and remains high for 40 ns. This forces the output, logic signal CYOLT0+01) low for 40 ns. setting flop 503 and the Q output MEIVIREQ+ goes high starting a main memory 3 request cycle as before.

When logic signal MEMREQ+ is high, 2 bus 5 cycle requests are made by cache 1. The first request sends the even address to main memory 3 and the second request sends the odd address to main memory 3. The first data word sent to cache 1 from the even address location of main memory 3 to cache 1 sets the data counter, flop 508, figure 5. The second data word to cache 1 cycle from the odd address location of main memory 3 sets the data counter flop 509 whose Q output logic signal DATCTI forces the output of NAND 510 low when CYFIFO is high thereby resetting the memory request flop 503 which in turn resets 85 the data counter flops 508 and 509.

During the second data cycle, the input to AND 567, logic signal FIFO 117+ , the low order address bit stored in LR 204, is high. The other inputs, logic signals CYWRIT and REPLACE going high force the output high. This forces the output of NOR 569, logic signal MEIVIREQ+OC low, forcing the output of NOR 502 high. On the next rise of CLOCKO+ flip 503 sets and the Q output, MEMREQ+, again goes high starting the next bus 5 cycle request.

The logic signal CYQLTO- input to NOR 501, which is low during the QLT mode, simulates a directory 202---nohit" condition.

When the 4096th word is requested from main memory 3 address location 7777, AOR 207, figure 2, is incremented + 1 by ADDER 211. The next address 10000. is set into AOR 207 as described supra. The output line BAOR 10+ is high and inputs NAND 570, figure 5. During the cycle when the 40961h data word is transferred from main memory 3 to cache 1 over bus 5 the inputs to AND 567, CYWRIT, REPLACE and FIF01 7+ are high forcing the output, logic signal MEMREQ+OD high. This forces the output of NAND 570 low resetting flop 571 and the Q output, logic signal CYQLTO+ goes low. The logic signal QLTDUN- high input to NOR 569 prevents flop 503 from setting after the 4096th data word is received. Logic signal CYOtTO-, the input to AND 533 low, prevents flop 529 from setting during the QLT operation.

DETAILED DESCRIPTION OF SYSTEM BUS

CONTROL 219 - Figure 5, Sheets 3 & 4 Logic signals BSAD 08-15-, 16+ and 17 connect between the receiver 213 output and an AND 546 whose output logic signal MYCHAN, connects to the SET input of flop 516. 13SIVIREF+ connects between receiver 217 and inverter 547 whose output BSMREF- connects to the AND 54.6 input. Logic signal 13SDCNN+ connects between the receiver 217 cycle control 232, a delay line 522 input, and one input of an OR 521.

The output of delay line 522 connects to the other input of OR 521 whose output logic signal BSDCNB+ connects to AOR and RAF control 235 and to the RESET terminal of flops 514, 516, 536, 574 and AOR and RAF control 235. The output of delay line 522, logic signal 13SDCND+, also connects to the CLK terminals of flops 516 and 536 and 574. Logic signal MYACKR connects between the Q output of flop 516 and the input terminals of delay lines 517, 518, AOR and RAF control 235, FIFO R/W control 230 and driver 218. The output of delay line 517 connects to an input of AND 520 whose output logic signal MYACKD connects to AOR and RAF 235 and to an input of NAND 506 in cycle control 232. The output of delay line 518 connects to an inverter 519 input whose output connects to the other input of AND 520. Logic---1 signal connects to the SET input of flop 536 whose1output, logic signal 13SDCND-, connects to an input of NAND 535 in cycle control 232. Logic---1---signal connects to the PRESET and D inputs of flop 511. The Q outputs of flop 511 logic signal CYREQ+ connects to an input of NAND 513. Logic signal BSBUSY- connects between an output of NOR 540 and the other input of NAND 513 whose output logic signal SETREQ- connects to a PRESET input of flop 515. Logic---1---signal connects to a PRESET input of flop 514. Logic signal BSDCND+ connects to the D input and the RESET input. MYXI\IN- connects between aW output of flop 541, the CLK input of flop 514 and the enabling i.nputs of drivers 212, 214 and 218. The Q output of flop 514 logic signal MYREQR+ connects to the CLK input of flop 515. The CLEARlogic signal connects to the RESET input of flop 515. Logic signals BSWAIT and BLOCKFconnect to inputs of AND 512 whose output logic signal MYREQ+ connects to the D input of flop 515 whose Q output logic signal MYREQT connects to Driver 218 and an input to AND 542.

BSDCNB+ connects to an inverter 544 input whose output connects to the input of AND 542 whose output, logic signal SETDCN- connects to the PRESET input of flop 541. Logic signals 13SACKR and BSWAIT connect between inputs of NOR 543 and Receiver 217. The NOR 543 output connects to the RESET input of flop 541. CLEAR connects between an inverter 573 output and to the input of NOR 543. CLEAR- connects between an input of inverter 573 and recei,er 217.

BSDCNB- connects between the output of inverter 544 and an input of AND 538. 13SREOT+ connects between the input of AND 538 and Receiver 217 and CLEAR connects to the input of AND 538 whose output connects to the input of delay line 539 and an input of NOR 540. The output of delay line 539 connects to the other input of NOR 540. The Q output of flop 541, logic signal MYDCNN+ connects to driver 218 and the -input of NAND 535 in cycle control 232. The output of NOR 536, logic signal BSDCNB- connects to the input of NAND,535. Priority logic signals 13SAU0K --- BSIUOK connects between AND 542 inputs and receiver 217. Logic signals MEMREQ+ and CI-RREQ-0A 18 GB 2 055 233 A 18 connect between cycle control 232 and the CLK and RESET inputs respectively of flop 511. Logic signal 13SDI3PL+ connects between the SET input of flop 574 and receiver 217. The Uoutput of flop 5 574 connects to cycle control 232.

During the first memory request cycle, if the CPU2 requested data is not in cache 1 then the MEMREQ+ CLK input to flop 511 goes high setting the Q output, logic signal CYREQ+, the input to NAND 513 high. The logic signal BSBUSY- is high if the bus 5 is not busy and the output of NAND 513, logic signal SETREG- goes low setting flop 515 whose Q output MYREOT goes high and inputs AND 542 requesting a bus 5 cycle. If bus 5 does not have a high priority request the logic signals 13SAU0K through BSIUOK are high, and if bus 5 is not transferring information then logic signal BCDCNB- is high and the logic signal SET13CN- output of AND 542 goes low setting flop 541 and the Q output MYXI\IN+ goes high gating drivers 212, 214 and 218 putting out on bus 5 information in the format 86 of figure 8. When main memory 3 receives the bus 5 information, the acknowledge logic signal BSACKR is sent back to cache 1 over bus 5 and reset flop 541 by setting the NOR 543 output low. The Q output, logic signal MYXI\IN-, going high sets flop 514 whose Q output logic signal MYREQR+ high, resets flop 515 since the D input logic signal MYREG is low. This sets the 0 output logic signal MYREQT low. A BSWAIT signal returned by main memory 3 indicating that main memory 3 is busy, resets flops 541 since the output of NAND 543 goes low. However, since the outputof AND 512 is high when flop 514sets and its Q output logic signal MYREQR+ goes high, the Q output of flop 515, logic signal MYREQT remains high and the first memory request is repeated.

In the interleaved mode when main memory 3 105 acknowledges the first memory request by sending the BSACKR logic signal, flop 511 remains set with the Q output logic signal CYREQ+ high to start the second memory request cycle. Flop 511 remains set during the interleaved mode since the output of NAND 535 remains high as does the CLK input MEIVIREQ+. The URREQ+013 input to NAND 535 is low as long as BLOCKF- input to NOR 536 is high. Logic signal BLOCKF- goes low after the first BSACKR acknowledge. When MY1)CNN+ goes high during the second memory request cycle flop 511 is set since BLOCKF- is low.

However, if the system is in the banked mode flop 511 is reset since the output of NAND 535 in cycle control 232 goes low at the end of the first memory request cycle. Logic signal CLRREQ+OB, the input to NAND 535 is high forcing the output of NAND 535, logic signal CI-RREQ-10A low when MYXI\IN+ goes high. A second memory request cycle starts when logic signal 13SREOT the input to AND 538 goes low when there is no request being made of bus 5. This forces the output of AND 538 low forcing the NOR 540 input low. 20 ns. later the other input to NOR 540 goes low forcing the output logic signal BSBUSY- high. Note that CLEAR is normally high and goes low during system initialization to reset functions. With both inputs to NAND 513 high, the output, logic signal SETREQ- going low again sets the Q output of flop 515 logic signal MYREQT high which requests a bus 5 cycle. Again the output of NAND 542 logic signal SETDCN- goes low setting flop 541 whose' Q output logic signal MYDCNN+ goes high gating drivers 212, 214 and 218 to send out the second memory request in the format 8b of figure 8 over bus 5 to main memory 3. If main memory 3 sends back the acknowledge logic signal BSACKR flop 541 is reset as before which sets flop 514 which resets flop 515 setting the Q output logic signal MYREQT low. Logic signal MY1)CNN+ the input to NAND 535 going high sets the RESET input to flop 511 low setting the Q output logic signal CYREQ+ low thereby preventing subsequent memory request bus 5 cycles. Logic signal CLEAR the input to NOR 543 also resets flop 541.

If main memory 3 were busy and sent back a BSWAIT logic signal in response to the second memory response, flop 541 resets since logic signal BSWAIT going high forces the NOR 543 output low, and the Q output of flop 541, logic signal MYXI\IN- goes high setting flop 514 whose Q output logic signal MYREQR goes high. The D input to flop 515 is low since logic signal BLOCKF+ is high at this time forcing the output.of NOR 572 low. This forces the output of AND 512, logic signal MYREQ+ low. When logic signal MYREQR+ goes high flop 515 resets setting the Q output logic signal MYREOT low. Since flop 511 was reset during the second memory request cycle as before the second memory request is aborted. However, in the QLT mode logic signal CYQLTO-, the input to NOR 572 is low forcing the output high. When the BSWAIT response is given the output of AND 512 is high setting flop 515. The Q output logic signal MYREQT high starts another memory request.

The flops 503, 504, 511, 514, 515, 529, 541 and 571 are 74S74 circuits described on page 5-22 of the aforementioned TTL Data Book. Flops 508 and 509 are 74S1 12 logic circuits described on page 5-34 and flops 516, 536 and 574 are 74S 175 logic circuits described on page 5-46 of the aforementioned TTL Data Book.

Main memory 3 sends the logic signals BSDCNN+ and the information in the format 8C of figure 8 out on bus 5 to receivers 213, 215 and 217 and the information is strobed into FIFO 203. BSAD 08-17 input AND 546 along with logic signal 13SIVIREF- which was inverted by inverter 547. If the cache 1 identification is 0002., that is BSAD '16+ is high and BSAD 00-15 and 17are high and that is not a main memory 3 write, i.e., BSMREF- is high, then the output of AND 546 logic signal MYCHAN goes high. Logic signal 13SDCNN+ high sets the outpt of OR 52 1, logic signal BSDCNB+, high which sets the RESET input of flop 516 high. Logic signal 13SDCNN+ is delayed 60 ns. by delay lines 522 and sets flop 516 whose output logic signal MYACKR going high advances 19 1 ' 1 GB 2 055 233 A 19 the FIFO Write Address Counter flops 320 and 32 1, figure 3. This operation was described supra. Logic signal MYACKR high sets flops 305, figure 3, and the Q output logic signal INTERG+ going high gates the data through buffer bypass drivers 205, figure 2, to junction 216, since this first data word from main memory 3 is in response to the CPU2 request. Logic signal MYACKR also goes out on bus 5 to acknowledge to main memory 3 l 0 that cache 1 received the information sent out by main memory 3 addressed to cache 1. In figure 5, logic signal MYACKR is delayed 20 ns. by delay line 517 and inputs AND 520 whose output, logic signal MYACKI) goes high 20 ns. after the rise of MYACKR. Logic signal MYACKR is delayed 40 ns. by delay line 518, is inverted by inverter 519 and sets the other input of AND 520 low. Logic signal MYACKD is a positive going 20 ns. _pulse delayed 20 ns. from the rise of MYACKR. Logic signal MYACKI) delays the setting of the Function Code History flops 412 and 413, figure 4, until after the data received from bus 5 is set into F] FO 203.

The above sequence is repeated in the interleaved mode for the 4 cycles in which the data words are transferred from main memory 3 to cache 1 in response to the first and second memory requests. In the banked mode the sequence is repeated for 2 cycles in response to the one memory request.

SYSTEM BUS 5 FORMATS Figure 8 shows the system bus 5 formats processed by cache 1 and/or main memory 3.

Figure 8 shows at 8a the memory address field with an 18 bit main memory 3 word address BSAD 05-22 of a 20 bit data word BSDT 00-15A, B, DSDTOO, 08. Thisformat is used by 100 CPU2 to update main memory 3 over system bus 5. Cache 1 reads the address and data in FIFO 203 from bus 5 through receivers 213 215 and 217. Cache 1 senses that logic signal 13SMREF is high, indicating that the address field contains a 105 main memory 3 address, senses that BSWRIT is high indicating this is a write operation and checks if the address location is written into cache 1. If the address is found in directory 202, figure 2, then the data word stored in data store 201 is updated. If the address is not in the directory 202, then the data is discarded. A peripheral controller may send a 19 bit byte main memory 3 address BSAD 05-23. In that case, cache 1 would update byte 0 or byte 1 if either byte is stored in 1 the data buffer 201.

Figure 8 shows at 8b the main memory 3 request sent from cache 1 to main memory 3. The address field contains the main memory 3 word address BSAD 05-22. The data field contains the 120

12 bit cache 1 identification code 0002., 13SDT A, B, 00-09 and the 6 bit function code 00, or 0 1, A function code of 00, designates the bus cycle as the first memory request cycle. The function code of 01, designates the bus 5 cycle as the second 125 meenory request cycle. 13SMREF is high since this is a request of main memory 1.

Figure 8 shows at 8c the main memory 3 response format to the memory read request of 8b. The address field contains the destination number of cache 1, 0002, and the function code 00, indicating a response to a first memory request or the function code 01 a indicating a response to a second memory request, BSWRIT indicates that main memory 3 is requesting cache 1 to write the data word in cache 1 at the address indicated by the figure 8 at 8b main memory 3 read request. 13SSHI3C high indicates that this is in response to a memory request. An interleaved memory main memory 3 request in the format 86 of figure 8 contains PPA for the first request address and PRA+ 1 for the 2nd request address. Main memory 3 responds with the PRA and PRA+2 data words in response to the first request and the PRA+1 and PRA+3 data words in response to the 2nd request.

A banked memory main memory 3 ' request in the format 8b of figure 8 contains PRA. Main memory 3 responds with the PRA and PRA+1 data words.

MAIN MEMORY 3 - DATA BUFFER 201 DIRECTORY 202 RELATIONSHIPS Figure 11 illustrates the relationships of the 18 bit address ADDR 00-17 in main memory 3, data buffer 201 and directory 202.

The 262,143 word locations in main memory are addressed by the 18 bit, ADDR 00-17 address which is made up of a row address portion ADDR 00-07 1 00a and a column address portion ADDR 07-17 100 b. Main memory 3 may therefore be considered as organized into 1,024 columns and 256 rows.

The data buffer 201, figure 12, has 4 levels, LEVEL 0-3 201 a-d. The column address ADDR 08-17 101, figure 11, locates 4 words one from each level of data buffer 201. The directory 202, figure 12, also has 4 levels, LEVEL 0-3 202a---d and the 18 bit address ADDR 00-17 102 figure 11, is made up of a column address ADDR 08-17 102b and a row address ADDR 00-07 102a. Row addresses ADDR 00-07 102a are stored in column address ADDR 0817 102b locations of directory 202.

Figure 12 shows the relationships between data buffer 201, directory 202 and main memory 3 where main memory 3 is organized in a banked configuration. In the banked configuration the data words are stored in successive address locations. This is in contrast to the interleaved configuration in figure 13 where data words in even address locations (ADDR 17 is a "0") are in one memory 3 bank and data words in odd address locations (ADDR 17 is a "11 are in the adjacent memory 3 bank.

Data buffer 201 comprises 4 levels, LEVEL 0-3 201 a-d, each level having 1,024 data word address locations. Directory 202 comprises 4 levels, LEVEL 0-3 202a-d, each level storing 1,024 row addresses. For each data word location in data buffer 20 there is a corresponding location in directory 202 that stores a row address. The combination of column address and row address GB 2 055 233 A 20 identifies the data word in data buffer 201 and 65 main memory 3.

The example below will show the relationship between the main memory 3, data buffer 201 and directory 202. Assume the 20 bit data word in main memory address location 1025 is to be stored in level 1 of data buffer 201.

The data word DATA00-1 9 n address location 1025 has the value of ADDR 00-17 as 002001, The column address ADDR 08-17 has a value of 0001.. The row address ADDR 00-07 has a value of 00%. The data word is written into the LEVEL 1 201 e location identified by column address 000 1. of data buffer 20 1. The row address 00 % is written into LEVEL 1 202e location identified by column address 0001, Figure 13 illustrates the interleaved main memory 3 with all the even address locations, address bit ADDR 17 set to -0-, in memory bank 3a and all the odd address locations, address bit ADDR 17 set to---1 -, in memory bank 3b. In 85 figures 12 and 13 the lines designated Col 1 through Col 1023 are not actual connections but rather indicate that a data word in a particular column of main memory 3 will be written into that column of data buffer 201 and the row address will be written into that column of directory 202.

DESCRIPTION OF OPERATION - REPLACEMENT

Figure 9 is a flow chart illustrating the sequence of operations that start when CPU2 makes a request of cache 1 for a data word.

The sequence starts in Block 90 1. CPU2 forces signal CACHRO. high which sets flop 313 figure 3 forcing the Q output signal FEMPTY-20 low.

Signal FEMPTY-20 low starts CLOCKO+ to cycle and sets the RAF 206 read address counter flops 426 and 427 Figure 4, to location 00. CPU2 sends the request address (PRA) signals BAOR 05-22+ through the 2:1 MUX 208, which is enabled by signal ADDRSO+, to directory 202 Figure 2 to perform the search.

The directory search is made in block 902 and PRA is loaded into AOR 207 and RAF 206 location 00 through 2:1 MUX 209. Signal FEMPTY-20 forces signal AORCNT, the output of NOR 419 figure 4 high which enable signal BAWRIT, the RAF 206 write strobe, enables signal BAORCK, the AOR 207 write strobe, and advances the RAF 206 Write Address Counter flops 426 and 427 to location 01.

In block 903 the rise of CLOCKO+ set flop 301 figure 3 whose'd output signal BLKREQ- resets flop 313. The Q output signal FEMPTY-20 is forced high keeping CLOCKO+ high.

If in block 904 PRA was found in directory 202 figure 2, then in block 905 the data word in the corresponding data buffer 201 address location, signals CADP 00-19 are sent to CPU2. Also a directory "hit" results in the setting of flop 529 figure 5 whose Q output is inverted and sent to CPL12 as signal CYCADN- where it strobes the data word into a register (not shown) and forces signal CACHRO, low.

If in block 904 PRA is not stored in directory 202 figure 2 then in block 906 flop 503 figure 5 sets and the Q output signal MEMREQ+ sets flops 511 whose Q output signal CYREQ+ goes high. Also, PPA+1 appears at the output of ADDER 211 when RAF 206 write address counter is set to location 01.

Cache 1 now requests bus 5 to send the memory request to main memory 3 for data words if main memory 3 is banked. Or if main memory 3 is interleaved 2 memory requests are sent by cache 1 for 4 data words from main memory 3.

Cache 1 requests access to bus 5 by forcing signal CYREQ+ the Q output of flop 511 high, figure 5. In block 907 when bus 5 is not busy the 2 signal inputs to NAND 513, figure 5, BSBUSY- and CYREQ+ which in block 908 sets flop 515. The Q output signal MYREQT remains high in block 909 until cache 1 has the highest priority of the system units requesting access to bus 5 then in block 910 the output of AND 542 goes low and sets flop 541. The Q output signal MYDCNN+ going high gates drivers 212, 214 and 218 to send out on bus 5 information in the format of figure 8b. PRA, cache identification 00028, Function Code 00, indicating that this is the firstrequest of main memory 3, BSMREF low indicating that the address levels BSAD 05-22 contain a main memory 3 address and BSDBPL high indicating that 2 data words are sent to main memory 3. Main memory 3 responds in block 912.

If main memory 3 is busy and cannot accept the bus 5 cycle in block 913a flop 541 the MYDCNN flop is reset, however, flop 515 remains set and signal MYREQT high requests another bus 5 cycle. When the response is an acknowledge and signal J 00 BSACKR goes high flops 5 15 and 541 are reset in block 913. Also flop 511 resets in the banked memory operation. Flop 504 sets in block 914 and the Q output logic signal BLOCKF+ goes high.

* Figure 6 is a timing chart illustrating the relative sequencing of the interleaved memory operation.

In the first memory request cycle timing signal CACHRQ 601 going high starts the cycle, causing FEMPTY-20 602 to go low. FEMPTY-20 going low forces BAWRIT 604 and BAORCK 605 low to strobe PRA into RAF 206 and AOR 207 respectively; and also advance the RAF 206 write address counter 234 by forcing AORCNT-30 609 low. If there is a directory "hit" HIT 0-3 606 goes high in the middle of the cycle (dotted line) and the data word CADP 00-19 607 (dotted line) is sent to CPU2. CYCADN- 608 is sent to CPU2 and forces CACHRO. 601 low (dotted line). If there is no "hit" MEMREQ 610 is set high by the rise of CLOCKO+ 603 which sets MYREQT 612 high. MYREQT 612 is turn sets MYDCNN+ 613 high. The BSACKR 614 response resets MYDCNN 613 which resets MYREOT 612. BSACKR 614 sets BLOCKF 611 high to start the second memory request.

Figure 7 is a timing chart illustrating the relative sequencing of the banked memory operation. The timing signals of the memory request cycle of figure 7 are the same as the corresponding timing signals of figure 6.

21 GB 2 055 233 A 21 With BLOCKF high in block 915, signal BAWRIT strobes P RA+ 1 into RAF 206 location 01. Signal BAORCK strobes PRA+1 into AOR 207 and the write address counter 234 is advanced to location 02. PRA+1 is switched from the ADDER 211 output through 2:1 MUX 209 which is enabled by signal MEMREQ, figure 2.

For the interleaved memory block 916 advances to block 917 whereas for the banked memory block 925 is processed next. For the interleaved memory blocks 917 through 920 is a repeat of blocks 907 through 910. In block 921 signal MYMNN+ is set and strobes drivers 212, 214 and 215, figure 2, sending out on bus 5, PRA+l, Cache Identification 0002,,, Function 0% 80 designating this as the second memory cycle, 13SMREF and 13SD13PI- as before.

This time the main memory 3 is busy and responds in block 922 with signal BSWAIT increments in block 923 the data counter by setting flop 508, figure 5. Now in block 924, signals BSACKR and BSWAIT reset MYREOT, MYDCNN+ and CYREQ.

BLOCKF 611, figure 6, starts the second memory request cycle by going high thereby forcing BAWRIT 604 low to strobe PRA+ 1 into location 01 of RAF 206 and forcing BAORCK 605 low to strobe PRA+1 into AOR 207. Signal AORCNT-30 609 advances RAF 206 write address counter 234 to location 02.

MYREOT 612, MY1)MN 613 and BSACKR 614 cycle as before. BSWAIT 615 resets MYREOT 612 and MY1)MN 613 and forces DATACK 616 low (dotted).

Both the Banked and interleaved operations 100 now await the bus 5 cycle which sends the PRA data word from main memory 3 to cache 1 in response to the first memory request.

When information is being transferred on bus 5, signal BSDCNN+ goes high in Block 925 forcing the output of NAND 332, figure 3, the write enable signal FWRITE low. This signal transfers the information on bus 5 through receivers 213, 215 and 217, figure 2, into FIFO 203.

For both interleaved and banked memories the flow diagram of figure 9 makes a number of passes from block 926 through 950; that is one pass for each data word transfer from main memory 3 to cache 1 over bus 5 in response to the memory request.

The information received in block 926 by FIFO 203 must be in the format of figure 8c if it is a response to the memory request. If it is not in that format then cache 1 performs a different sequence of operations.

Assuming the information received is in response to the memory request, then the PRA data word is received by cache 1 on the first bus 5 data cycle as is the cache identification 0002, function code 00. indicating that this is in response to the first memory request, 13SDI3PIhigh indicating that this is the first of the 2 data words in response to the first memory request, 13SMREF low indicating that the address field contains the cache identification and function code and BSSHBC high indicating that this bus cycle is in response to the memory request.

For the banked memory the PRA and PRA+ 1 data words are received in response to the memory request. BSDBPL will be low for the PRA+1 data word. The function code will be 00, for both the P RA and PRA+ 1 data words.

For the interleaved memory the PRA and PRA+2 data words will be sent from main memory 3 to cache 1 over bus 5 with a function code of 00, indicating this is the response to the first memory request, PRA+ 1 and PRA+3 will be sent with a function code of 01. indicating this as a response to the second memory cycle, BSDBPL will high for PRA and PRA+ 1 and low for PRA+ 2 and PRA+3.

If the cache identification is 0002,, then in block 927 signal MYCHAN is forced high as the output of AND 546, figure 5, and sets flop 516 whose 0 output MYACKR going high sends a signal back to main memory 3 acknowledging that the information was received in response to the memory request. The signal is received by main memory 3 as BSACKR.

If in block 926 the data word received by FIFO 203 is not in response to the memory request, then in block 927, signal MYCHAN does not go high and the decision block 927a exits to a series of decision blocks 927b, 927c and 927d which tests if the information in FIFO 203 is an achnowledged main memory 3 write operation. If it is a write BSWRIT is high, and if it is addressed to main memory 3, BSMREF is high and if main memory 3 acknowledged the receiving of the information BSACKR is high then in block 932a, the FIFO 203 Write Address Counter is incremented by +1.

For the interleaved memory, decision block 929 tests the RAF 206 write address counter 234. If set at location 02 then in block 930 the ADDER 211 input control signal + 1, the output of EXCLUSIVE OR 237 Figure 2 is high and PRA+2 appears at the output of ADDER 211 and is strobed into RAF 206 location 02. The write address counter 234 is then adv nced to location 03. If the write address counter 234 had been set to location 03 then the +2 control signal, the output of AND 236 is high and PRA+3 appears at the output of ADDER 211 and is strobed into RAF 206 location 03 after which the write address counter 234 advances to location 00.

Both banked and interleaved memory systems in block 932 advance the FIFO 203 write address counter flops 320 and 321 figure 3 by forcing signal FPLUS 1 low. Advancing the write address counter flops forces the output signal FEMPTY+ of comparator 318 low. This signal is inverted and sets flops 313 so that the Goutput signal FEMPTY+20 goes low and starts CLOCKO+ cycling in block 933.

Decision block 934 now tests the function code low order bit BSAD23. If BSAD23 is low indicating this is the response to the first memory request then in block 935 the FCHZRO flop 413 figure 4 sets and if BSAD23 is high the FCHONE flop 412 GB 2 055 233 A 22 of block 936 sets. Flops 412 and 413 condition the read address multiplexer 233 outputs to select the address stored in RAF 206 with the proper PRA data word received from main memory 3 in response to the memory request.

Decision block 937 tests signal BSDBPL which when low indicates the second word of a memory' response and advances the block 933 data counter flops 508 and 509 Figure 5.

Decision block 939 tests for the end of the bus 75 cycle and when signal BSDCNN+ goes low, flop 516 figure 5 sets in block 940 and the 0 output signal MYACKR goes low.

The first bus 5 information stored in FIFO 203 is read in block 941 and if the FIFO bit position 41 + is low in decision block 942 it indicates that this is update information. If the FIFO bit position 41 + is high indicating that this is a replacement operation then the read address multiplexer 233, figure 2, selects the proper location in RAF 206 to read out the address corresponding to the data word in FIFO 203 into LR 204. On the CLOCKO+ rise flop 323, figure 3, sets the Q output CYFIFO high which enables LR 204. This sets the output of the selected location of RAF 206 indicated by read address multiplexer 233 into the address flops of LR 204 and also sets the data output and control output of FIFO 203 into the respective flops of LR 204.

Decision block 945 tests the output of the read 95 address multiplexers 414 and 415, figure 4, and if set to location 00, sets flop 529, figure 5, in block 946 which results in signal CYCADN- being sent to CPU2 as before. Also flop 305, figure 3, is set and the 0 output signal INTERG+ gates the data word from signal lines FIFO 19-38 through the buffer bypass drivers 205, figure 2, to CPU2 as CADPOO-1 9. CPU2 then resets signal CACHRQ which resets flop 30 1, figure 3, which resets flop 305. If this is not the first data word cycle then the 105 read address multiplexers 233 are not set to location 00 and in block 947 a directory 202 search is made. If the data word is already in the data buffer 201 then no further action is taken on the data word. If the data word is not in data buffer 201 then in block 948, the round robin logic unit 224 selects the WRITE signal of the next level of that column address into which the data word is to be written. In block 949 the data word is written into the data buffer 201, the row address 115 is written into the directory 202 and the old level of round robin 224 is incremented by +1 the address location selected by the column address.

In decision block 950 the data counter flop 509 figure 5 if set resets the flops indicated in block 120 951 and the operation is concluded. If flop 509 is not set then the operation returns to block 925 to await the next data word from main memory 3 in response to the memory request.

Again returning to figure 6 for the PRA cycle, that is the cycle in which the first data word is sent from main memory 3 to cache 1 over bus 5 signal, BSDCNN+ 618 goes high indicating that there is a " bus 5 cycle starting_and forces the FIFO 203 write enable signal FWRITE 619 low. This loads FIFO 203 from receivers 213, 215 and 217 with the information from bus 5. If the information is in response to the memory request then signal MYACKR 620 goes high achnowledging the bus 5 transfer and advancing the FIFO 203 write address counter by forcing FPLUS 1 621 low. Advancing the counter indicates that FIFO 203 has information stored in it. This forces FEMPTY+ 20 621 low which starts CLOCKO+ 603 cycling. The data word output of FIFO 203 is sent through the buffer bypass drivers 205 during the time indicates by INTERG 625 as CADPOO-1 9 607. Signal CYCADN- 608 strobes the data word CADPOO-1 9 607 into CPU2 and resets CACHRO, 601.

Signal ADDRSO+ switches 2:1 MUX 208 so that when signal CYFIFO 627 comes high and strobes the outputs of RAF 206 and FIFO 203 into LR 204, the output of LR 204 can start the directory search by transferring the address signals ADDROO-1 7+ through the switch. Signal REPLACE comes high to switch 2:1 MUX 223 to receive the selected WRITE 629 signal for the directory 202 and data buffer 201 replacement write operation. Signal CYREAD 628 low gates the selected signal WRITE 0- 3 629.

Local Register 632 shows information transferring into LR 204 when signal CYFIFO goes high.

Signal BUMPUP 630 advances the read address counter of FIFO 203 by going low. LR 632 is already loaded with the FIFO 203 at this time. The RAF read address multiplexer 631 when high, gates the output of the location indicated by the ADDRWD+OB and ADDRWD+OA signals to LR 204. BAWRIT 604 loads PRA+2 into location 02 and PRA+3 into location 03 on successive MYACKR 620 pulses. AORCNT-30 609 advances the write address counter after each loading of PRA+2 and PRA+3 into RAF 206.

In the PRA+2, PRA+1 and PRA+3 cycles if the data word is stored in data buffer 201 then HIT 0-3 606 will go high (dotted) for that data word, suppressing the fall of CYREAD 628 which in term suppresses the WRITE 0-3 629 pulse. The data word will therefore not be written into the data buffer 201.

As previously stated, if the response to the second memory request was the BSWAIT signal then the request is not repeated. Since 2 data words instead of 4 data words will be sent from main memory 3 to cache 1 over bus 5 the data counter is incremented when signal DATACK 616 pulses (dotted) in the second memory request cycle. Then in the PRA+2 cycle when the second data word is sent over bus 5 to cache 1, the signal DATACK 616 again pulses which sets DATCTI high (dotted). This resets MEMREQ 610 (dotted) which resets BLOCKF 611 (dotted) and DATCTI 617 and the prefetch operation is completed.

Normally signal DATACK is pulsed by the second data word and the fourth data word (BSDBPL high) and the operation completed after the fourth data word cycle when signal DATCTI 617 comes high and resets MEMREQ 610 which 23 GB 2 055 233 A 23 resets BLOCKF 611 and DATCTI 617.

Now returning to figure 7 illustrating the timing of the banked main memory 3 and cache 1 operation, in many respects the timing signals of figure 6 illustrating the interleaved operation is similar to their respective timing signals in figure 7. The basic difference is that figure 7 illustrates the banked timing which requires 2 data cycles, the PRA and PRA+1 data cycles compared to figure 6 which illustrates the interleaved timing which requires 4 data cycles, PRA, PRA+l, PRA+2 and PRA+3. Therefore, many of the figure 6 timings show 4 cycles as compared to the figure 7 timings which show 2 cycles of operation. Also, since the data counter is forced to + 1 in the banked operation only 1 DATACK 716 pulse is needed to set DATCTI 717 which resets ME[VIREO, 716 pulse is needed to set DATCTI 717 which resets MEMREG 710 which in turn, resets BLOCKF 711 and DATCTI 717 as before.

DESCRIPTION OF OPERATION - UPDATE

In block 925 logic signal BSDCNN goes high indicating a bus 5 cycle is started. In figure 3, logic signal BSDCNN going high generates the FWRITE strobe as the output of NAND 332. This loads FIFO 203 with the bus 5 information.

Block 926, in this case, receives the bus 5 information and tests in decision block 927a if MYCHAN is high, that is, if the cache identification 0002,, was received with BSMREF high. In the update, in figure 5, the output of AND 515, logic signal MYCHAN is low therefore testing blocks 927b-d. In the update mode the 3 inputs to NAND 337, figure 3, logic signals BSACKR, BSMREF and BSWRIT are high forcing the blocks 100 932a, logic signal F PLUS 1 low advancing FIFO 203 Write Address Cou nter flops 320 and 321 to the next location. In block 941, FIFO 203 bit position FIFO 41 + is read and in decision block 942 FIFO 41 + is low iqdicating an update operation in block 962! Logic signal CYFIFO, the Q output of flop 323, figure 3, is set high when the write address counter flops 320 and 321 advance to the next location forcing the FEMPTY+ output of comparator 318 low. This sets flop 313 and starts 110 CLOCKO+ cycling. CYFIFO going high transfers, in figure 2, the output of FIFO 203 to LR 204 and advances the FIFO 203 read address flops 316 and 317 by forcing the logic signal BUMP UP low.

The 18 bit address signals FIFO 00-17+ 115 transfers through 2:1 MUX 208 to start a directory 202 search. Also, F/F 41 of LR 204, figure 3, resets and the-ZYoutput UPDATE goes high.

Column Address ADDR 08-17-10 reads out 4 locations, one in each level, to the 4 comparator 120 221 a-d inputs. These outputs ADDR 00-07-20,-21,-22 and 023 are compared with row address ADDR 00-07-10.

In block 955, if there is no hit, that is, all 4 CYREAD goes low thereby enabling the selected WRITE 0-3 write lines. REPLACE, the 2:1 MUX 223 switch signal is low allowing the selected HIT 0- 3+ logic signal to force the corresponding WRITE 0-3 logic signal lines high provided the 2:1 MUX 223 enabling signal CYREAD is low. If a byte is to be updated logic signals BYTE MOD and FIFO 18+ or FIFO 18- select the data buffer 264 or 265 for updating. If logic signal BYTE MOD is low then the data word in the column address location ADDR 08-17-10 in data buffers 264 and 265 are updated and the operation is completed.

The timing diagram, figure 10, illustrates the update cycle. Logic signal BSDCNN+70 high indicates the start of the bus 5 cycle. This forces FIFO 203 strobe FWRITE 72 low, loading FIFO 203 from the receivers 213,215 and 217. When. BSMREF 71, BSWRITE 72 and BSACKR are all high, logic signal F PLUS 1 advances the FIFO 203 write address counter forcing FEMPTY+20 76 low. This starts CLOCKO+ 77 which forces CYFIFO 70 high transferring information from FIFO 203 to LR 204. The directory 202 search is made and if there is a hit, one of the HIT 0-3 78 signals going high forces CYREAD 81 low enabling the data buffer 201 and directory 202 write. If no HIT 0-3 78 signal goes high indicating that the information is not in data buffer 201 then, CYRAD 8 1 remains high, suppressing the last (dotted) CLOCKO+ 77 cycle and preventing a write cycle. The FIFO 203 Read Address Counter is advanced by logic signal BUMPUP going low. If there is no additional information in FIFO 203 logic signal FEMPTY+20 76 goes high.

If there was a hit the rise of CLOCKO+ 77 at point B concludes the cycle. If there was no hit then the rise at Point A concludes the operation.

ROUND ROBIN 224 - Figure 14 Logic signal CYWRIT connects between F] FO R/W Control 230, the inputs to delay lines 603 and 605 and the CLK inputs of flops 610 and 611.

The output of delay line 603 connects to the input of an AND 604. The output of delay line 605 connects to an input of an inverter 614 whose output connects to the other input of AND 604.

The output of AND 604 connects to inputs of an inverter 606 and a NAND 607. The output of inverter 606, logic signal WFITPI-S- connects to the ENABLE terminal of 2:1 MUX 223. Logic signal REPLACE connects between LR 204, the other input of NAND 607 and the SELECT terminal of 2:1 MUX 223. The outputs of AND 613a-d, logic signals LEVELO-3+ connect to the '1 input terminals of 2:1 MUX 223. The output of NAND 607, logic signal F[NDWRT- connects to the Write Enable terminals of Random Access Memory RAM 601 and 602, the Read Enable terminals are connected to ground.

Signal lines ADDR 08-17 + connect between outputs HIT 0-3+ remain low, no further action 125 2:1 MUX 208 and the ADDRESS select terminals is taken on the data. If there is a hit, that is, one of of RAM 601 and 602. Logic signal RNDADD+ the 4 outputs HIT 0-3+ goes high, then in block connects between NOR/AND 612 and the data 956, flop 330, figure 3, sets and the U-output input of RAM 601 whose data output 24 GB 2 055 233 A 24 ROUNDO+OA connects to the D input of a flop 610. Logic signals BAOR 11 + 10 and BAOR 12+10 connect between AOR 207 and inputs to a NOR 608 whose output logic signal ROUNDR- connects to the D input of a flop 609. Logic signal CYFIFO connects between FIFO R/W control 230 and the CLK input of flop 609. The troutput of logic signal ROUNDO-OR connect to the CLR inputs of flops 610 and 611. Logic signal CYQLTO+ connects between cycle control 232 75 and the CLR input of flop 609.

The Q output of flop 610, logic signal ROUNDO+ connects to inputs of NOR 1/AND 612, AND 613c and AND 613d. The Uoutput, logic signal ROUNDOconnects to the inputs of NOR2/AND 612, AND 613a and AND 613b. The Q output of flop 611, logic signal ROUND1 +, connects to inputs of NOR 1/AND 612, AND 613b and AND 613d. The Z1 output, logic signal ROUND 1 -,connects to inputs of NOR2/AND 612, AND 613a, AND 613c and the data input of RAM 602. The data output of RAM 602 logic signal ROUND 1 + OA connects to the D input of flop 611.

Signal lines HITO-3+ connect between the COMPARE 221 a-d outputs and the 0 terminal of 2:1 MUX 223. Signal lines WRITEO-3 connect between the 2 terminal of 2:1 MUX 223 and data buffer 201 and directory 202.

Round robin 224 selects the next level of data buffer 201 and directory 202, figure 2, into which new information is written. Round robin 224 points to the oldest information for that column address ADDR 08-17. That is the information for replacement.

The two 1 bit by 1024 RAM 601 and 602 are set to level 0 for each column address; that is, the 1024 addresses in RAM 601 and the 1024 addresses in RAM 602 are set to 0 during the QLT mode.

Initially, logic signal CYQLTO+, the CLR input to 105 flop 609 is high. Both inputs to NOR 608, logic signals BAOR 11 + 10 and BAOR 12+10 are low forcing the output logic signal ROUNDR- high. When logic signal CYFIFO goes high flop 609 sets and the -G output, logic signal ROUNDO-OR goes low preventing flop 610 and 611 from setting.

Logic signals ROUNDO- and ROUND 1 - are high forcing the output of AND 613a, logic signal LEVELO+ high.

The 2 inputs to NOR2/AND 612, logic signals ROUNDO- and ROUND 1 - are high forcing the output logic signal RNDADD+ low. The data input to RAM 601 therefore is low. Since the _Joutput of flop 611, logic signal ROUND 1 is high, the data input to RAM 602 is high.

During the QLT mode, the first 4096 data words in main memory 3 are written into the data buffer 201 and their respective row addresses ADDR 00-07-10 are written into directory 202. The first 1024 data words with their row addresses are written into level 0, the second 1024 data words with their row addresses are written into level 1, the third 1024 data words with their row addresses are written into level 2 and the last 1024 data words with their row 130 addresses are written into level 3. The levels are selected by the round robin RAM 601 and 602.

For each of the first 1024 write cycles, logic signal CYWRIT the input to delay lines 603 and 605 goes high. 20 ns. later the output of delay lines 603 goes high. Both inputs to AND 604 are high and the output logic signal WRITPLS+ is high. REPLACE is high in the QLT mode. This forces the output of NAND 607, logic signal RNDWRT- low enabling the write function of RAM 601 and 602. The output of inverter 606, logic signal WRTPLS- goes low enabling 2:1 MUX 223. 50 ns. later the output of delay line 605 goes high forcing the output of inverter 614 low.

This forces the output of AND 604 low forcing the output of inverter 606, logic signal WRTPLShigh. Logic signal RNDWRT-, the output of NAND 607 goes high terminating the write enable pulse.

All zeros are forced into the 1024 successive addresses of RAM 601 and all ones are forced into the 1024 successive addresses (0-1023) of RAM 602.

When address 1024 (2000,) is stored in AOR 207, BAOR 12+10 is high forcing the output of NOR 608, logic signal ROUNDR- low. When logic signal CYFIFO goes high, flop 609 resets and the G output logic signal ROUNDO-OR goes high. Flops 610 and 611 are now activated. ADDR 08-18+ selects address 0000, of RAM 601 and 602. The data output, logic signal ROUNDO+OA is low and logic signal ROUND1 +OA is high. When logic signal CYWRIT goes high flop 611 sets and the Q output logic signal ROUND1 + is high. Logic signals ROUND1 + high and ROUNDO- high select the output of AND 613b, logic signal LEVEL 1 +. Also, the output of NOR/AND 612 is forced high writing a " 1 " in RAM 601 and a "0" in RAM 602 at address 000., This sequence continues until 1024 level 1 locations in data buffer 201 and directory 202 are filled and RAM 601 stores all---1's- and RAM 602 stores all "O's".

Logic signal BAOR 11 + 10 is high for the transfer of data words in addresses 2048 to 4096 keeping flop 609 reset. Flop 610 is set and flop 611 is reset for the 3 rd 1024 data words with their row addresses to be written into data buffer 201 and directory 202. In this case, the output of AND 613c, logic signal LEVEL 2+ is high. During this 3rd sequence "1's" are written into all addresses of RAM 601 and 602.

During the 4th sequence flops 610 and 611 are set selecting the output of AND 613d, logic signal LEVEL 3+ high. This results in all O's being written into RAM 601 and 602. During the sequence when the 4096th data word is transferred from main memory 3 and written into cache 1, logic signal CYQLTO+ goes low resetting flop 609 thereby enabling flops 610 and 611 for subsequent replacement operation.

Flop 609 is a 74S74 logic circuit described on page 5-22. Flops 610 and 611 are 74S 175 logic circuits described in page 5-46 and NOR/AND 612 is a 74LS51 logic circuit described.on page 5-16. The above are described in the aforementioned TTL Data Book.

DESCRIPTION OF OPERATION

Figure 16 is a flow diagram illustrating the Quality logic test (QLT) mode. As a result of system initialization, a negative going CLEARsignal is sent over bus 6 to cache 1. As a consequence of receiving the CLEARsignal, the contents of the first 4096 address locations in main memory 3 are stored in the 4 levels of data 10buffer 201, figure 2. The directory 202 is loaded with the respective row addresses of the first 4096 address locations and the round robin RAMs are set to point to Level 0 as the first level in data buffer 201 and directory 202 to be replaced.

Figure 15 is a timing diagram of the QLT operation and will be used with figure 16 in the description of the overall operation.

START 901 designates a bus 5 transfer cycle. Cache 1 receives all bus 5 transfers for possible updating or replacement.

In the QLT operation logic signal CLEAR- is received by cache 1 over bus 5. This is indicated by START 900.

The decision block 901 selects the QLT mode 902 and in block 903, flop 57 1, figure 5, sets on the rise of logic signal CLEAR- and the Q output logic signal CYQLTO+ goes high. This forces the output of NOR 561 low and logic signal CYQ1-TO-1 A, the output of inverter 567 is forced high. Logic signal CYQLTO+OB the output of delay line 562 remains high for 160 ns. In figure 4 the output of NAND 443 goes low forcing the output of NOR 419, logic signal AORMT, high.

In block 904 the output of ADDER 211, figure 2, signal lines AORO 05-22+ are at 000000, The output of NAND 241 is high switching 2:1 MUX'.

209 to allow lines AORO 05-22+ through to input AOR 207.

Logic signal AORCNT, figure 4, forces logic signals BAWRIT, the output of NAND 416 low, and 105 BAORCK, the output of NAND 424 low writing the PRA 000000, into AOR 207, figure 2, and location 00 into RAF 206. 70 ns. later logic signal AORCNT-30 the output of inverter 423, goes low advancing the RAF write address counter 234 to 110 location 01.

ns. after logic signal CYOLTO+ rises, logic signal CYOLT0+00, the output of NOR 565, figure 5, goes low setting flop 503. This forces the Q output MEMREQ+ high, block 905, setting flop 511. This forces the Q output, logic signal CYCREG+ high in block 906, requesting a bus 5 mple in block 907.

In figure 15, timing signal CLEAR- 701 goes high at 0 ns. of the first bus 5 cycle request forcing 120 CY01-TO+ 702 high. This results in BAWRIT 710 and BAORCK 711 going low strobing 000000, into AOR 207 and RAF 206. AORCNT-30 713 advances the RAF write address counter 234 to location 01. 160 ns. after the rise of MLTO+ 702, MLT0+01) 703 fails forcing MEIVIREQ+ 704 high which forces CYCREQ+ 705 high.

In decision block 907a logic signal BSBUSY-, the input to NAND 513, figure 5, goes high. Since GB 2 055 233 A 25 1 logic signal CYCREQ+ is high, flop 513 sets and the Q output MYREQT goes high in block 907b.

In block 907c, if there is no higher priority request on bus 5 then the output of NAND 542 goes low setting flop 541. The Q output logic signal MYMNN+ going high, blok 907d enables drivers 212, 214 and 218 which sends out on bus in block 907c the output of AOR 207, 000000 the cache 1 identification and function code, BSDBPL and BSIVIREF.

The response from main memory 3 in decision block 907f 13SACKR,acknowledging the information sent from cache 1 is sent back over bus 5. Signal BSACKR is applied to the input of NOR 543, figure 5 thereby forcing the output low.

This results in flop 541 resetting, flop 514 setting and flop 515 resetting. This is shown in block 907, figure 9. The Q outputs MYMNN+ and MYREOT are now low and in block 907k, the Bus cycle Request is concluded.

If the main memory 3 response was BSWAIT in decision block 907f then in decision block 907g the output of NOR 543, figure 5 goes low, resetting flop 541 and the Q output, logical signal MYMNN+ goes low. In blocks 907h and 907j the output of NOR 572, figure 5, is high forcing the output of AND 5 12 high keeping flop 515 set with the Q output logic signal MYREQT high, requesting another bus 5 cycle.

P RA+ 1 address (000000.) now appears at the output of ADDER 211, figure 3, in block 908.

The BSACKR response to the first bus 5 cycle request sets flop 504, figure 5, and the Q output BLOCKF+ is high. Since the write address counter 234 is set to location 01, the output of NOR 417, figure 4, goes low forcing the output of NOR 419, logic signal AORCNT high. This loads in block 909 00000 1. into AOR 707 and location 0 1 of RAF 206. When logic signal AORCNT-30 goes low the RAF write address counter advances to location 02.

if figure 15, MYREQT 706 goes high forcing MY1)MN+ 707 high when the bus 5 is available, MY13MN- strobes the cache 1 information onto bus 5 and when main memory 3 receives the information it sends back BSACI(R 708 which resets MY1)MN+ 707 and sets BLOCKF 709. MY1)MN+ going low causes MYREQT 706 to reset. When the bus 5 is no longer busy MYREQT 706 goes high requesting another bus 5 cycle.

When Block F 709 goes high to start the 2nd bus 5 cycle request BAWRIT 710 and BAORCK 711 strobe the address appearing at the output of ADDER 211, figure 2, into AOR 207 and RAF 206. AORCNT-30 713 then advances the RAF write address counter 234 to location 02.

Since CYCREQ+ 705 is still high in the 2nd bus 5 cycle request MYREQT 706 again goes high requesting the bus 5 cycle.

Block 907-1, figure 16, sheet 2, reqeusts the 2nd bus 5 cycle and blocks 907-i as repeated to send the next address in sequence out on bus 5 with the cache identification 0002, the function code, BS1313PI- and BSIVIREF.

In figure 15, MYREQT 706 high starts the 2nd GB 2 055 233 A 26 912-1 is activated since the data word is from an odd address location in main memory 3. information out on bus 5 as before. When main memory 3 receives the information, BSACKR 708 5 is sent to cache 1 over bus 5 and resets MYDCNN+ 707 which results in MYREOT 706 resetting.

In block 910, cache 1 waits for the first data word from main memory 3. In block 900, information is on bus 5. In decision block 901 CLEAR is not set selecting decision block 911 where BSDCNN+ is high indicating that information on bus 5 is to be written into FIFO 203 in block 912. In block 912a logic signal' FWRITE, the output of NAND_332, figure 3, forces the write enable terminal of FIFO 203 low and in figure 2 the output of receivers 213, 215 and 217 are strobed into FIFO 203. As shown in block 912b FIFO 203 is loaded with the data word in response to the first bus 5 cycle request whereby PRA 000000,, was sent to main memory 3. Also loaded into FIFO 203 are the octal Cache I.D. (0002,,) and the function code (00.) signals, as well as logic signals BSDBPL high, BSMREF low qnd BASSHBC high.

Decision block 912c tests the cache identification code for 00028 and that BSIVIREF is low. In that case in figure 5 the output of AND 546, logic signal MYCHAN goes high starting the second half bus cycle of block 913.

In block 913e with logic signal MYCHAN high, the CLK input of flop 516, logic signal BSDCND+ goes high, flop 516 sets and the Q output, logic signal MYACKR goes high and acknowledges to main memory 3 that the information was received. 100 In block 913b the output of NAND 322, figure 3, logic signal FPLUS 1 sets the FIFO 203 write address counter flop 320 thereby advancing the counter. This forces the output of comparator 318 low resulting in flop 313 setting. The U output logic signal FEMPTY+20 going low starts timing signal CLOCKO+ the output of NOR 311 to cycle in block 913c.

Since the function code is 00, BSAD23 is low 4ndecision block 913d, then in block 913f the 110 FCHZRO, flop 413, figure 4, sets and a -11 - is forced into FIFO 203 bit position 42.

Decision block 913g tests for BSDBPL high. In the OLT mode BSDBPL is low and flop 574, figure 5, remains reset and th-Q output, logic signal BSDBPL- is high forcing the output of NAND 506 low setting the output of NOR 507, logic signal DATACK- low setting the data counter flop 508 in block 913h.

Decision block 9 1:I. is tested for flop 509, 120 figure 5, set. In this case flop 509 is not set and the output of NAND 510 remains high. In decision block 913j, logic signal BSDCNN+ is tested and ns. after it goes low in block 913 k, flop 516 resets and the Q output logic signal MYACKR falls 125 and cache 1 goes into an idle cycle waiting in start block 900.

The second data word in response to the 2nd Bus Cycle Request 907-1 is transferred to cache 1. When BSDCNN+ is high FIFO write block 130 bus 5 cycle request by forcing MYDCNN+ 707 high which resets CYCREQ+ 705 and strobes the The FIFO write sequence described above is repeated through blocks 912a-c to second half bus cycle block 913-1. The second half bus cycle sequence of blocks 913a- g is repeated. In block 91 3h data counter flop 509, figure 5, is set and the Q output logic signals CYFIFO and DATCTI high in decision block 91 3i forces the output of NAND 510 low resetting flop 503 in block 913n.and the Q output logic signal MEREQ+ falls.

The MYACKR flop 516 in block 913m is reset when in decision block 913 1, logic signal BSDCNN+ goes low. In block 913n, logic signal MEMREQ+ going low resets flops 508, 509, 504, figure 5 and 413, figure 4. This forces logic signals DATCTO, DATCTI, BLOCKF+ and FCHZRO low in block 913o.

Cache 1 returns to START 900 for the first FIFO 203 read cycle.

In figure 15 BSDCNN+ 714 is high to start the FIFO write cycle in which the first data word from the even address location in main memory 3 is transferred to cache 1. FWRITE 715 strobes the bus 5 information into FIFO 203. MYACKR 716 is forced high when FIFO 203 contains the Cache I.D. 0002,, and BSIVIRLF is low. MYACKR 716 high advances the FIFO write address counter by forcing F PLUS 1 717 low. FIFO 203 is now not empty and FEMPTY+20 goes low starting - CLOCKO+ 719 to cycle to start the first FIFO 203 read cycle.

During the first w - ord to cache cycle BSDBPL low forced the data counter clock pulse DATACK 728 low. During the 2nd FIFO write cycle BSDBPL is again low and DATACK 728 is again forced low forcing DATCTI 729 high. This resets MEMREQ+ 704 which resets BLOCK F 709 and DATCTI 729.

In block 913b of the second half bus cycle, the FIFO write address counter is incremented. This sets the output of comparator 318, figure 3, logic signal FEMPTY+ low, indicating in decision block 916 that FIFO 203 is not empty, starting the clock cycling by setting flop 313 in block 913c and starting a FIFO read operation in block 914.

The FIFO read address counterflops 316 and 317 select in block 914a the FIFO address from which information is transferred from FIFO 203 to LR 204.

Since the output of decision block 914b is high, that is the bit position 41 of FIFO 203 is high, the replacement block 915 is selected. The update block 914c is not active in the QLT operation.

RAF 206 stores the address for the data word stored in the selected FIFO 203 address location. In block 91 5a the RAF read address multiplexer 4:1 MUX 414 and 415, figure 4, select location 00. Logic signal CYQLTO- is low forcing the output of NOR 440 high forcing select terminal 2 of 4:1 MUX 414 and 415 high. Since bit position 18 of FIFO 203 is low, select terminal 1 of 4:1 MUX 414 and 415 are low; therefore input terminal 2 is enabled. 4:1 MUX 414 input terminal 2 is low as is input terminal 2 of 4:1 MUX 415.

In block 915b, the address from location 00 of 27 GB 2 055 233 A 27 RAF 206 and the data word and controls from FIFO 203 are transferred to LR 204 on the rise of logic signal CYFIFO. The output of AND 324, figure 3, is high and on the rise of timing signal CLOCKO+ flop 323 sets and the Q output, logic signal CYFIFO goes high loading LR 204.

Decision block 91 5c tests BAOR1 1 and BAOR 12. If both are low indicating that the first 1024 data words are being transferred then in block 91 5d the Round Robin Register is held reset 75 selecting level 0 of the data buffer 201 and directory 202. In figure 14 the output of NOR 608 logic signal ROUNDR- is high. When logic signal CYFIFO goes high flop 609 sets and the 5 output, logic signal ROUND-OR goes low holding flops 610 and 611 reset. In block 91 5c therefore the outputs logic signals ROUNDO- and ROUND 1 - are high forcing the output of AND 613a logic signal LEVEL 0+ high.

In block 91 5h at the selected column address, the data word is written into the data buffer 201, the row address is written into the directory 202 -and the round robin RAM's are incremented +1.

The output of NOR 340, figure 3, is high forcing the output of NOR 325 low when logic signal CYFIFO is high, forcing the output of NOR 327 high. This sets flop 330 and the Q output CYWRIT goes high. In figure 14 logic signal CYWRIT high develops a 30 ns. negative going pulse delayed 20 ns. to the enable input of 2:1 MUX 223. This forces logic signal WRITEO high, writing the data word into level 0 of data buffer 201 and writing the row address into directory 202 at the selected column address. The output of NAND 607 goes low enabling the write input of RAM 601 and 602 100 forcing a " 1 " in RAM 602 and a "0" in RAM 601 at the selected column address ADDR 08-17+ since logic signal ROUNb 1 - is high and RNDADD+ is low.

In decision block 91 5c, address locations between 1024 and 4095 have bit position BAOR 11 + 10 and/or BAOR 12+10, the output of AOR 207, figure 2, high. In block 91 5f normal round robin 224 operation takes place, i.e., in figure 14, the output of RAM 601 and 602 at the column address location ADDR 08-17+ is loaded into flops 610 and 611 at the rise of logic signal CYWRIT. The outputs of flops 610 and 611 are decoded by AND 613a-d in block 91 5g to select the level in directory 202 and data buffer 201 into 115 which the data word is written. This was described supra.

the FIFO Read timing is shown in figure 15 by F PLUS 1 717 advancing the FIFO 203 write address counter flops 320 and 321, figure 3. This 120 results in flop 313 setting the ffoutput FEMPTY+20 718 going low starting - CLOCKO+ 719, loading the data word and a control bits from FIFO 203 and the address location from RAF 206 in LR 204. LR 726 shows the timing.

CYREAD 721 and CYWRITE 722, the Q and Q outputs respectively of flop 330, figure 3, switch on the rise of CLOCKO+ 719 when CYFIFO 720 is high. REPLACE 723 is high since FIFO bit position 41 is high for the OLT operation. Replace 723 130 comes high at the rise of CYFIFO 720 and remains high for the 4096 data word OLT transfer.

WRITE 0-3 727 is generated in round robin 224, figure 14. Logic signal CYWRIT outputs AND 604 as a positive going pulse 30 ns. wide, delayed 20 ns. which is inverted by inverter 606 and enables 2:1 MUX 223. Since the select input logic signal REPLACE is high, the 1 input terminal is activated. The rise of logic signal CYWRIT sets the selected output of RAM's 601 and 602 into flops 610 and 611 forcing one of the outputs of AND 613a-d, logic signals LEVEL 0-3+, high. This selected signal inputs terminal 1 of 2:1 MUX 223 and exits terminal 2, is inverted by inverter 255, figure 2 and enables the writing into data buffer 201 and directory 202 as the negative going 30 ns. wide pulse WRITE 0-3-.

The FIFO read address counter is advanced by BUMP UP 724 which causes FEMPTY+20 718 to go high and stop CLOCKO+ 719 from cycling. However, the odd word is being received by cache 1 from main memory 3 so that F PLUS 1 717 again advances the FIFO write address counter, forcing FEMPTY+20 718 low keeping CLOCKO+ 719 cycling to store the odd word in the data buffer 201, and its row address in the directory 202. After the odd word is stored FEMPTY+20 718 stays high and CLOCKO+ 720 remains high at the completion of the cycle which stores the data word from the odd address location into cache 1.

in figure 16, decision block 915i is tested for the 4096th word. If the last word was not received then in block 91 5j the address at the ADDER 211 output, figure 2 is incremented + 1 and the RAF write address counter 234 is advanced.

Decision block 91 5k is tested. If the data word received into FIFO 203 is from an even address location in main memory 3 then cache 1 returns to START 900 to await the next word from main memory 3 from the odd address location. If the data word received into FIFO 203 is from an odd address location in main memory 3 then in block 9151 the next address is loaded.into AOR 207 and RAF 206 and the write address counter 234 is advanced. Note that in block 91 5j the WAC 234 is advanced an extra count for each data word transferred. This is so the WAC 234 stores the even address location in location 00 of RAF 206 and the odd address location in location 01 of RAF 206. Locations 02 and 03 are not used.

In block 915m flop 503, figure 5, is set as follows. The output of AND 567 is high, since input signals CYWRIT, REPLACE and FIFO 17+20 are high. This forces the output of NOR 569, logic signal MEMREQ+OC low forcing the output of NOR 502 high setting flop 503 on the next rise of timing signal CLOCKO+. The Q output logic signal MEMREQ+ going high starts a memory request cycle by returning to block 906 where the cycle request flop 511 is set and the Q output, logic signal CYCREQ+ goes high.

In figure 15 MEMREQ+ 704 goes high at the end of the cycle in which the data word from the 28 GB 2 055 233 A 28 1 1 1 - odd address location in main memory 3 is written into cache 1. This occurs when CYWRITE 722 is high on the last rise of CLOCKO+ 719.

Cache 1 continues to cycle, first requesting 2 data words from main memory 3, then writing those data words in data buffer 201 and the row address in directory 202, until in decision block 91 5i, the 4096th word is received into LR 204, figure 2. In that case BAOR 10+ 10, one input to NAND 570, figure 5, is high. When the output of AND 567 goes high during the cycle in which the data word from the odd address location is written into cache, the output of NAND 570 goes low resetting flop 57 1. In block 915n this forces the Q output, logic signal CY1ULTO+ low concluding the QLT operation.

BAOR 10+ 10 high forces the output of inverter_ 568, logic signal QLTDUNlow forcing the output of NOR 569, logic signal MEIVIREQ+OC high. This forces the output of NOR 502 low. With the D input low, flop 503 resets on the next rise of timing signal CLOCKO+ and the Q output logic signal MEIVIREQ+ goes low preventing further requests of main memory 3.

In figure 15 12LTDUN 712 goes high during the last bus 5 cycle request forcing MEIVIREQ+ 704 low at the next rise of CLOCKO+ 719. CYQLTO+ 702 goes low during the next cycle when CYWRITE 722 is high, the data word from the odd address location is in LR 726 at the fast rise of CLOCKO+ 719.

Claims (12)

1. A data processing system comprising:

a system bus; a central processing unit coupled to said bus 100 and being operative to generate memory requests, each said memory request including a main memory address; an addressable main memory coupled to said bus, said main memory including a plurality of sets 105 of locations for storing a plurality of words, each word location being designated by an address coded to include a first portion and a second portion; and a cache unit coupled to said bus and to said 110 central processing unit, said cache unitcomprising; a register which stores the main memory address received from the central processing unit, an addressable data store having a plurality of locations which store the contents of subsets of 115 said sets of locations in the main memory, each word location being designated by said second portion of said address; an addressable directory having a plurality of locations, corresponding in number to said plurality of data store locations, which stores a plurality of said first portion of said addresses in a location designated by said second portion of said address, each address location of the directory specified by the second portion of the address having a corresponding address location in the data store storing the word specified by the second portion of the address and the first portion of the address stored in the address location of the directory specified by the second portion of the _address, the cache unit and the directory receiving the main memory address from the central processing unit when requesting a word from the main memory and control means coupled to said register and responsive to each memory request received from the central processing unit and coded to specify a read operation so as to indicate if the word requested by the central processing unit is stored in the data store by comparing the first portion of each main memory address received from the central processing unit with said first portion address stored in the location of said directory read out in response to said second portion of each main memory address received from the central processing unit, and in the absence of the equal comparison requesting the word from the main memory by generating a signal which transfers signals representative of said main memory address to said register and to said main memory, said control means being operative upon receiving said word from main memory to generate signals for writing said word jp the data store at the location designated by said second portion of the address stored in said register and which concurrently writes said first portion of said main memory address stored in said register in the directory in the location designated by the second portion of said main memory address. 95

2. A system according to Claim 1 wherein the cache unit further includes means which sends the word received from the main memory to the central processing unit during the writing of said word in the data store at the location specified by the second portion of the main memory adress stored in the register.

3. A system according to Claim 1 or Claim 2 wherein the presence of the equal comparison as specified by the control means generates signals to transfer said word in the data store location designated by the second portion of the main memory address to the central processing unit.

4. A system according to any of Claims 1 to 3 wherein the data store and the directory each are organized in a plurality of levels of storage locations, each of said levels having locations responsive to the second portion of the main memory address, and each of the locations of the plurality of levels of the data store having corresponding locations of the plurality of levels of the directory.

5. A system according to Claim 4 wherein the main memory addressable locations are organized in a plurality of columns of said address locations, and each of the plurality of columns is organized in a plurality of rows of said address locations, the plurality of columns being addressable by the second portion of the main memory address, and the plurality of rows being addressable by the first portion of the main memory address, the data store storing the word in the location designated by a column address, and the directory storing a row address in the location designated by the column address.

i 29 GB 2 055 233 A 29

6. A system according to Claim 5 wherein the number of data store word locations is substantially less than the number of said memory word locations.

7. A data processing system comprising: 65 an addressable main memory having a plurality of sets of locations for storing a plurality of words, each word location being designated having an address which is coded to have a first portion and a second portion; and, a cache unit coupled to the main memory to store signals read out therefrom in response to a main memory request including a main memory address, said cache unit further comprising:

a register which stores the main memory address requested of the cache unit; - an addressable data store having a plurality of locations which store the contents of subsets of said sets of locations in the main memory, each word location being designated by the second portion of said address; an addressable directory having a plurality of locations corresponding in number to said plurality of data store locations which stores at least a first portion of one of said addresses in a location designated by said second portion of said address, each address location of the directory specified by the second portion of the address having a corresponding address location in the data store storing the word soecified by the second portion of the address and the first portion of the address stored in the address location of the directory specified by the second portion of the address, the cache unit and the directory receiving the main memory address requested of the main memory and control means responsive to each memory request specifying a read operation which indicates if a requested word is stored in the data store by comparing said first portion of each main memory address with the first portion address stored in the location of the directory designated by the second portion of said each main memory address, and in the presence of an equal comparison generating signals which transfers signals representative of the main memory address to the register and to the main memory, the control means being operative upon receiving the requested word from the main memory to generate signals for writing the word in the data store at the location designated by the second portion of the address stored in the register and which concurrently writes the first portion of the main memory address stored in the register in the directory in the location designated by the second portion of the main memory address.

8. A system according to Claim 7 wherein the cache unit further includes means which sends the word received from the main memory to the central processing unit during the writing of said word in the data store at the location specified by the second portion of the main memory address stored in the register.

9. A system according to Claim 7 or Claim 8 wherein the presence of the equal comparison as specified by the control means generates signals to transfer said word in the data store location designated by the second portion of the main memory address to the requesting unit.

10. A system according to any of Claims 7 to 9 wherein the data store and the directory each are organized in a plurality of levels of storage locations, each of said levels having locations responsive to the second portion of the main memory address, and each of the locations of said plurality of levels of said data store having corresponding locations of the plurality of levels of the directory.

11. A system according to Claim 10 wherein the main memory addressable locations are organized in a plurality of columns of said address locations, and each of said plurality of columns is organized in a plurality of rows of said address columns, the plurality of columns being addressed by the second portion of the main memory address, and the plurality of rows being addressed by the first portion of the main memory address, said data store storing said word in the location designated by a column address, and the directory storing a row address in the location designated by the column address.

12. The method of organizing a memory system having an addressable main memory and a cache input including an addressable data store and an addressable directory each including a plurality of locations, said method comprising:

(1) storing a plurality of words in a plurality of sets of the main memory locations, each word location being designated by an address coded to include a first portion and a second portion; (2) storing the contents of subsets of said sets of main memory locations into a plurality of the data store locations; (3) storing at least the first portion of one of the addresses in one.of the directory locations designated by the second portion of said one address; (4) comparing the first portion of each main memory address with the first portion address stored in the location of the directory read out in response to the second portion of each main memory address; (5) generating signals in the absence of a prescribed comparison for writing a word read out from main memory in said data store at the location designated by said second portion of said address stored in the register and for concurrently writing said first portion of said main memory address stored in said register in said directory in said location designated by the second portion of the main memory address.

Printed for Her Majesty's Stationery Office by the Courier Press, Leamington Spa, 1981. Published by the Patent Office, 25 Southampton Buildings, London. WC2A lAY, from which copies may be obtained.