GB2056135A - Data Processing System Including a Cache Store - Google Patents

Abstract

A data processing system includes a main memory system, a high speed buffer cache store, a central processor unit (CPU) and an Input/Output processor (IOP) all connected to a system bus. Apparatus in the cache store reads all information on the system bus into a first in, first out buffer comprising a plurality of registers, a write address counter, a read address counter and a means for selectively processing the information. The cache store is word oriented and further comprises a directory 202, a data buffer 201 and associated control logic. The CPU requests data words by sending a main memory address of the requested data word to the cache store. If the cache store does not have the requested information word, apparatus in the cache store requests the data word from the main memory system, and in addition, the apparatus requests additional data words from consecutively higher addresses. If the main memory system is busy, the cache store has apparatus to request fewer words. The cache store is organized in levels. Data from a particular portion of main memory is transferred to these levels on a first in- first out basis. Apparatus in the form of round robin logic circuitry, including memories 601, 602 and gates 613a-613d, makes the first in-first out level selection. Apparatus also exists for resetting the round robin count during the initialization procedure. Apparatus in the cache store monitors each communication between system units to determine if it is a communication from a system unit to the main memory system which will update a word location in main memory. If that word location is also stored in the cache store then the word location in the cache store will be updated in addition to the word location in main memory. <IMAGE>

Description

1 GB 2 056 135 A 1

SPECIFICATION

Improvements in or Relating to Data Processing Systems This invention relates generally to mini computing systems and more particularly to storage hierarchies having high speed low capacity storage devices and lower speed high capacity devices coupled in common to a system bus.

The storage hierarchy concept is based on the phenomena that individual stored programs under execution exhibit the behaviour that in a given period of time a localized area of memory receives a very high frequency of usage. Thus, a memory organization that provides a relatively small size buffer at the CPU interface, and the various levels of increasing capacity slower storage can provide an effective access time that lies somewhere in between the range of the fastest and the slowest elements of the hierarchy and provides a large capacity memory system that is "transparent" to the software.

Prior art systems use a large capacity main store or main memory and a small capacity high speed backing store or cache memory associated with the CPU. The cache memory includes a cache directory and a cache data store. The CPU request a data word from both the main memory and cache. If the data word is in cache then the request of main memory is invalidated. If the data word is not in cache then the requested data word is sent to the CPU and a block of data containing the requested data word is stored in cache. In the prior art the cache is associated with a bus system. Registers in the cache are coupled to the 100 bus system and accept address, data and control signals.

Prior art was limited to storing the requested data word with its address in hardware registers.

When the need came about for expanded size, low cost buffers, the prior art utilized a block organization. If a particular word was requested by the CPU, the block containing that word was stored in a high speed data buffer. This had the disadvantage of bringing into the high speed buffer words with a relatively low probability of usage. Assuming a four word block, if word 4 is requested, the entire block including words 1, 2 and 3 which may have a relatively low probability of usage, are brought into the high speed buffer.

To optimize the usage of the memory hierarchy, the operating system must organize memory in such a manner that software sub-modules and data blocks start with word 1 of the block. To overcome this difficulty, the prior art utilized a "block lookahead". When one block was in the high speed buffer, a decision was made during the processing of a data word in that block to bring the next block into the high speed buffer.

U.S. Patent No. 3,231,868 issued to L. Bloom et al., entitled "Memory Arrangement for Electronic Data Processing System" discloses a "look aside" memory which stores a word in a register and its main memory address in an associated register. To improve performance, U.S.

Patent No. 3,588,829, issued to L. J. Boland, et al., discloses an eight-word block fetch to the high speed buffer from main memory if any word in the eight-word block is requested by the CPU.

An article by C. J. Conti, entitled "Concepts for Buffer Storage" published in the IEEE Computer Group News, March 1969, describes the transfer of 64-byte blocks as used on the IBM 360/85 when a particular byte of that block not currently in the buffer is requested. The IBM 360/85 is described generally on pages 2 through 30 of the IBM System Journal, Vol. 7 1, No. 1., 1968.

U.S. Patent No. 3,588,829 issued to Boland, et al., entitled "Integrated Memory System with Block Transfer to a Buffer Store" describes the prefetching of a block of information if a word in that block is requested.

U.S. Patent No. 3,820,078 issued to Curley et al entitled "Multilevel Storage System Having A Buffer Store With Variable Mapping Modes" describes the transfer of blocks of 32 bytes of half-blocks of 16 bytes from main memory to the high speed buffer when a word (4 bytes) of the block of half-block is requested by the CPU. U.S.

Patent No. 3,896,419 issued to Lange et al., entitled "Cache Memory Store In A Processor Of A Data Processing System" describes the transfer of a four word block from main memory to the high speed buffer when a word of that block is requested by the CPU. U.S. Patent No. 3,898,624 issued to Tobias entitled "Data Processing System With Variable Prefetch and Replacement Algorithms" describes the prefetching of the next line (32 Bytes) from main memory to the high speed buffer when a specific byte is requested by the CPU of the previous line.

In minicomputers, particularly those minicomputers which are organized in such a fashion that a plurality of system units are connected in common to a system bus, the prior art systems present a number of problems all having to do with reducing the throughput of the minicomputer. The prior art sends back to cache from main memory the entire block of words in which the requested word is located. This includes words with addresses preceding the requested word and words with addresses following the requested word. In most cases, the CPU will require on the following cycle the word in the next higher address. This results in words with high probability of being used as well as words with lower probability of being used being transferred into cache. To overcome this problem, the prior art requires that the programmer or the operating system optimize their programs to start sequences off with words at the first address of each block. Another problem in the prior art is that a block of words transferring from main memory to cache comes over in successive cycles, for example, a 32 byte block may be transferred in 8 cycles, 4 bytes at a time. In the minicomputer bus oriented system, this would greatly reduce the throughput of the system.

Prior art systems using the round robbin type

2 GB 2 056 135 A 2 of replacement procedure have the cache store organized in levels. A round robin counter is used to indicate the next level into which replacement information is written. Also, in the prior art a full/empty mechanism is included to indicate the status of the information in each of the levels of the store.

During the initialization operation the prior art systems clear the cache by resetting the full/empty indicators.

In the prior art, the replacement procedure included logic circuitry to ensure that valid data was stored in cache since random data might be resident in the cache store on an initialize cycle for instance.

U.S. Patent 3,840,862 issued to D.T. Ready entitled "Status Indicator Apparatus for Tag Directory in Associative Stores" and U.S. Patent 3,845, 575 issued to R. E. Lange, et al, entitled "Cache Store Clearing Operation for a Multiprocessor Mode" both describe such systems.

The disadvantage of the additional storage of the full/empty bits with the complexities of the additional logic circuitry are overcome by the approach used in this invention.

It is an object of the invention to provide an improved cache directory and cache data store system for use in a system bus oriented computing system.

It is a further object of the invention to provide simplified round robin logic circuitry.

According to the present invention, a data processing system comprises:

a system bus; an addressable main memory coupled to said bus, said main memory including a plurality of sets of word locations, each set of word locations being defined by a column address, and each word location within a set being identified by a row address, said main memory receiving an address word comprising said row address and said column address from said bus for reading a data word onto the bus, or for writing a data word received from the bus; a cache coupled to said system bus including:

a data buffer having a plurality of word locations arranged in a plurality of sets of word locations defined by column addresses for storing data words received from the bus, and a directory including a plurality of word locations corresponding in number to the number of sets in the data buffer and being addressable by column address, each word location of the directory storing a row address of a corresponding 120 one of said words of the set stored in the data buffer, each column of the data buffer and the directory defined by a column address having a plurality of levels; said cache ftirther including round robin circuit 125 means coupled to the directory and the data buffer which generates signals to indicate a next of said levels into which replacement information is to be written, said round robin circuit means including:

a plurality of RAM (random access memory) circuits which store n bits of information of each nth power of 2 number of levels in each of the column addresses of the RAM circuits, said bits of information being coded to indicate the next level of the column address into which replacement information is to be written, said circuits include output circuit means for receiving signals from said RAM circuits during a replacement operation; an encoder coupled to said output circuit means, said RAM circuits being responsive to the column address to provide stored bits of information to the encoder, the latter providing loading signals having a value determined by the output circuit means for writing the replacement information into the next level of the column address of the directory and the data buffer on a first in/first out basis; and a counter coupled to the encoder and to the RAM circuits which increments by one said encoder output and store an incremented count in said column address of the RAM circuits for enabling the storing of information corresponding to said replacement information in the location of the data buffer identical of that stored in main memory during the replacement operation.

The invention also provides a cache unit comprising:

a data buffer having a plurality of locations arranged in a plurality of sets of locations defined by column addresses, each location storing data words; a directory including a plurality of locations corresponding in number to the number of sets in said data buffer and being addressable by said column addresses, each location of said directory storing an address of a corresponding one of the locations of the sets stored in the data buffer, each column of the data buffer and the directory defined by a column address having a plurality of levels; round robin circuit means coupled to the directory and the data buffer which generates signals to indicate a next of said levels into which replacement information is to be written, said round robin circuit means including:

a plurality of RAM (random access memory) circuits which store a number of bits of information for designating the number of levels associated with each of the column addresses of said circuits, said number of bits of information being coded to indicate a next level of said column address into which replacement information is to be written, said circuits including output circuit means for read out of signals from said memory circuits; an encoder coupled to said output circuit, the encoder generating loading signals in response to signals from RAM output circuits for writing the replacement information into the next level of the column address of the directory and the data buffer on a first in/first out basis; and a counter coupled to the encoder and to the RAM circuit, the counter being operative to increment by one said loading signals and to 3 GB 2 056 135 A 3 apply an incremented count to one of the RAM circuits designated by the column address to enable the replacement of information in one of the locations of the data buffer during a 5 replacement operation.

A preferred embodiment of the invention comprises a main memory, a central processor (CPU), a cache store and an Input/Output Processor all connected in common to a system bus. The cache store provides first access to information previously fetched from main memory by way of the system bus. The CPU requests information from the cache system over a private CPU-Cache interface. If the information is in cache, it is returned immediately to the CPU over the private CPU-Cache interface. If the information is not in cache, then the cache requests the information over the system bus from main memory and the cache receives the requested information over the system bus from main memory. In order to assure that the information stored in cache is current with the information stored in main memory, apparatus in the cache reads all system bus information. If the information read from bus is to update main memory then apparatus in cache updates the information stored in cache if the address location of the information is stored in cache.

Information received by cache from the system bus to be updated in cache includes control bits coded to indicate that the information contains a main memory address, that this is a main memory write operation and that the information has been accepted by main memory. If the information also includes a cache identification code then a directory search is made of the address included in the information.

The probability is high that the next information requested by the CPU is in the next higher address location in main memory. It would therefore increase the throughput of the overall data processing system if that information from the next higher address location could be brought into cache immediately. This system provides apparatus for prefetching not only the information in the next higher address location, but prefetches information from a plurality of successively higher locations in main memory to cache over the system bus. In some main memory configurations when main memory is busy processing information from other systems connected to the system bus, and the cache requests information over the system bus, main memory sends out a "busy" logic signal over the system bus. This system senses the busy signal and requests less information from main memory than if main memory were not busy.

In one embodiment, main memory is organized as an interleaved double fetch memory, that is even addresses are in one memory bank and odd 125 addresses are in another memory bank. This allows some increase in main memory throughput. The double fetch feature provides up to 2 data words of information for each main memory request. Interleaved memories are used 130 throughout the industry. This interleaved memory is conventional in design. Typical interleaved memories are described in U.S. Patent No.

3,796,996, issued March 12, 1974.

When the CPU requests information from cache and that requested information is not in cache, apparatus in cache sends 2 requests over the system bus to main memory for a total of 4 data words of information. If main memory responds over the system bus that main memory is busy after receiving the first request, then logic circuits in cache respond to the "busy" by repeating the first request. When the first request is accepted by main memory, cache sends the second request over the system bus to main memory. If main memory responds with a busy logic signal, then apparatus in the cache cancels the second request and awaits the 2 data words of information from main memory over the system bus.

In another embodiment, main memory is organized as a banked double fetch memory, that is each memory bank has consecutive address locations. When the CPU requests information go from cache and that requested information is not in cache, apparatus in cache sends 1 request to main memory over the system bus for 2 data words of informaticim If main memory responds over the system bus with a "busy" signal, then cache responds by repeating the request to main memory over the system bus.

The system uses the attributes of a word system with simplified circuitry over a block system to efficiently process clata with a reasonably high hit ratio. Transferring a word at a time over the system bus between main memory and the cache data store with the cache directory mapping data store location for location increases throughput and decreases the logic circuits required for implementing this system over prior art systems. In the event that the system bus is busy, the data request of main memory by cache of words following the requested word is cancelled.

The cache system monitors all information on the system bus. If the information is a main memory write reference, and if the address of the information to be written is stored in the directory, then the information in the data buffer at that address is "updated" with the new information from the system bus.

The central processor sends information to the main memory over the system bus but requests information from the cache over a private CPU- cache interface by sending the address of the requested information to cache. If that address is stored in the directory, then the data from the data store at that address is sent to the central processor over the private CPU-cache interface. If the address is not stored in the directory, then the cache unit requests this information of main memory by sending the address of the requested information out on the system bus as a memory request.

Cache in its continuous monitoring of the 4 GB 2 056 135 A 4 system bus will receive the information in response to the memory request. The data received on the system bus is sent to the central processor over the private CPU-cache interface.

An 1 8-bit address is sent to the directory. The 8 70 high order address bits are written into the directory at the address specified by the 10 low order address bits. The data sent to the CPU is written into the data store at the address specified by the 10 low order bits. This data replaces the oldest data previously written into that address. A round robin counter keeps track of, for each address, the next level of cache to receive the "replacement" data.

The system bus interface unit connects the cache memory unit to the system bus enabling the cache memory unit to access main memory and read out CPU required information. The system bus has been covered by U.S. Patents 3,993,891 entitled "Apparatus for Processing Data Transfer Requests in a Data Processing System" and 4,030,075 entitled "Data Processing System Having Distributed Priority Network".

The cache apparatus comprises a first in first out buffer, a read address counter, a write address counter and control logic. The first in - first out buffer is made up of four 44 bit registers.

Information from the system bus is read into one of the empty registers of the first in-first out 95 buffer. If the information is to update main memory and is acknowledged as being received by main memory then a search is made of a cache directory for that main memory location. If the cache directory indicates that the main memory address location is stored in a cache data buffer then the data word is written into that data location in the cache data buffer. If the cache directory indicates that the main memory address location is not stored in the cache data buffer then 105 the information is discarded. This assures that the cache data buffer is current with main memory.

Also, if the information in the first in-first out buffer contains a cache address identification code, then the data word portion of the information is written into the cache data buffer at the address stored in a replacement address file.

Information in the first in-first out buffer is If the bit is coded to represent a replacement operation then the control bit enables the replacement address file to send the CPU request address to the directory. The control bit initiates logic circuits to replace the oldest information at the data buffer word location indicated by the CPU request address with the data word contained in the information sent over the system bus.

The overall system initialization procedure includes means for loading all memory locations in cache with information from main memory starting with the low order address and continuing sequentially until the entire cache is full. This eliminates the requirement for the full/empty logic circuitry by eliminating the possibility of random data in cache.

As a consequency of loading the cache during the initialization cycles, the round robin count for each level is set in such a manner that during subsequent processing the first information written into cache will be the first information replaced.

The round robin approach described herein enhances the test and diagnostic procedures by limiting the writing of information in cache to check out that level only.

Arrangements according to the invention will now be described, by way of example, with reference to the accompanying drawings, in which:- Figure 1 is a block diagram of the overall system; Figure 2 is a block diagram of the cache system; Figure 3 is a logic circuit diagram of Clock Control and FIFO R/W Control; Figure 4 is a logic circuit diagram of AOR and RAF Control, the RAF Write Address Counter and the RAF Read Address Multiplexer; Figure 5 is a logic circuit diagram of Cycle Control and System Bus Control; Figure 6 is a timing diagram of the replacement operation with an interleaved memory; Figure 7 is a timing diagram of the replacement operation with a banked memory; Figure 8 shows the system bus formats; Figure 9 is a flow diagram illustrating the replacement and the updata operation; accepted by advancing the write address counter 115 Figure 10 is a timing diagram of the update to point to the next register location in the first in first out buffer. If the information is to be discarded then the write address counter does not advance and the next bus cycle information writes over the previous information.

The information sent over the system bus includes a control bit which indicates if the information is representative of an update or replacement operation.

If the bit is coded to represent an update operation then it enables the address portion of the information sent over the system bus to search the directory. If the directory stores that address then the control bit initiates logic circuits cycle; Figure 11 shows the layout of the address bits for main memory and cache; Figure 12 illustrates the relationship between a 120 banked main memory and cache; Figure 13 illustrates the relationship between an interleaved main memory and cache; Figure 14 is a logic diagram of the round robin; Figure 15 is a timing diagram of the Quality 125 Logic Test operation; and Figure 16 is a flow diagram illustrating the Quality Logic Test operation.

- Figure 1 is a block diagram of a minicomputer system which comprises a central process unit to update the data word stored in the data buffer. 130 (CPU) 2, a main memory 3, an input/output GB 2 056 135 A 5 multiplexer (IOM) 7, a system bus 5, a cache directory and data buffer (cache) 1 and a system support channel (SSC) 8. Not shown are the normal complement of standard peripherals connected to the system by SSC 8. With the exception of SSC 8, each unit couples to the system bus 5 via an interface signal bus 4, SSC 8 couples to the IOM 7 through input/output (1/0) bus 9. In addition, CPU 2 and cache 1 are interconnected by a private interface signal bus 6. 75 IOM 7, 1/0 bus 9 and SSC 8 are not pertinent to the invention and will not be described in detail.

CPU 2 is designed for use as a communications network processor and is a firmware controlled 20 bits per word binary machine. Main memory 3 can be added to the system in modules of 32,768 words up to a maximum of 8 modules or 262,144 words. Main memory 3 is made up of random access MOS chips with 4,096 bits stored in each chip and has a read/write cycle time of 550 nanoseconds.

Cache 1 provides an intermediate high speed storage with a maximum read/write cycle time of 240 nanoseconds. CPU 2 requests a data word from cache 1 over private interface 6 and obtains the data word if in cache 1 in 110 nanoseconds over private interface bus 6. If the requested data 90 is not in cache 1, then CPU 2 receives the data via main memory 3, bus 5, cache 1 and bus 6 in 960 nanoseconds. If cache 1 was not in the system, then the CPU 2/main memory 3 read access time is 830 nanoseconds. Using the prefetch techniques described herein assures that in most cases over 90% of the requested data words are stored in cache 1 thereby greatly increasing the throughput of the system using cache 1 over a system without cache 1. System bus 5 permits 100 any two units on the bus to communicate with each other. To communicate, a unit must request a bus 5 cycle. When the bus 5 cycle is granted, that unit may address any other unit on bus 5. 1/0 bus 9 is identical to system bus 5 in performance 105 and in signal makeup. IOM 7 controls the flow of data between bus 5 and the various communications and peripheral controllers of the system via 1/0 bus 9. SSC 8 is a microprogrammed peripheral controller which 110 provides control for various devices (not shown). Other controllers (not shown) may also connect to 1/0 bus 9.

CPU 2 updates data in main memory 3 by sending the data word with its main memory 3 address and the appropriate control signals out on bus 5. Cache 1, since it reads all information on bus 5 into a register in cache 1 will be updated if that data word location is stored in cache 1. This assures that information stored at each address location in cache 1 is the same as information stored at the corresponding address location in main memory 3.

CPU 2 requests data from cache 1 by sending the requested address (PRA) over private interface 6 to cache 1. If the data is stored in cache 1, the requested data is sent back to CPU 2 from cache 1 over private interface 6. If the requested data is not in cache 1, cache 1 requests the data of main memory 3 over bus 5 and in addition cache 1 requests three additional data words from address locations PRA+ 1, PRA+2 and PRA+3 for the interleaved memory or one additional word of data from address location PRA+ 1 for the banked memory. When the data words are received from main memory 3 over bus 5 by cache 1, they are written into cache 1 and the requested data word is sent from cache 1 to CPU 2 over private interface 6.

Cache System Figure 2 shows the cache 1 system which includes a bus interface unit 10, a replacement and update unit 11, a cache directory and data buffer unit 12, an address control unit 13 and a private cache-CPU interface unit 6. Figure 2 is made up of 4 sheets. The information flow is best seen with sheet 2 at the left, sheet 1 on the right, sheet 3 below sheet 1 and sheet 4 below sheet 3.

Bus Interface Unit 10 - Figure 2, Sheet 1 Bus interface unit 10, Figure 2, comprises drivers 212, 214 and 218, receivers 213, 215 and 217, and system bus control logic unit 219.

Bus interface unit 10 connects to bus 5 through interface signal bus 4. Bus 5, interface signal bus 4 and system bus control 219 are disclosed by U.S. Patent Nos. 3,993,981 entitled "Apparatus For Processing Data Transfer Requests In A Data Processing System-, and 4,030,075 entitled 'Mata Processing Systems Having Distributed Priority Network- and will be described herein only as necessary to provide continuity to the description.

The 18 address leads 13SAD 05-22 are connected between bus 5 and the junction of the driver 212 and the receiver 213 of bus interface unit 10. The output of receivers 213, 215 and 217 connect to a First-In-First-Out (FIFO) buffer 203. The 20 bit data word lines 13SDT A, B, 0015, BSDP 00, 08 are connected to the junction of the driver 214 and receiver 215. A number of control signal lines are connected to the junction of the driver 218 and the receiver 217. These control logic signals Bus request 13SREOT, data cycle now 13SDCNN, bus acknowledge 13SACKR, bus wait BSWAIT, BSAD 23, second half bus cycle 13SSHI3C and bus double pull 13SD13PI- input system bus control 219 through receiver 217 and are distributed to other logic control units which will be described infra as well as being sent out on bus 5 through driver 218.

The My Data Cycle Now logic signal MYXI\IN- connects between System BusControl 219 and drivers 212, 214 and 218.

Signal bus BSAD 08-17, the output of receiver 213, connects to Cycle Control 232 of the Replacement and Update Unit 11. The output of an address register (AOR) 207, 18 bit address BAOR 05-22 in the address control unit 13 connects to the input of driver 212. Cache identification code 0002, and function code 00, or 01. are encoaed on the input of a driver 214 6 GB 2 056 135 A 6 whose output is connected to the bus 5 data lines 65 BSDT A, B, 00-15. Logic circuit signals described infra are connected between other units of cache 1 and system bus control 219.

The receiver driver pairs 212 and 213, 214 and 215, and 217 and 218 are 26S1 0 circuits 70 described on page 4-28 of the catalog entitled "Schottky & Low Power Schottky Bipolar Memory, Logic & Interface" published by Advanced Micro Devices, 901 Thompson Place, Sunnyvale, California 94086.

Replacement and Update Unit 11 - Figure 2, Sheet 3 The replacement and update unit 11 Figure 2 includes the FIFO buffer 203, a local register (LR) 204, buffer bypass drivers 205, FIFO R/W control 230, clock control 220 and cycle control 232.

Replacement and update unit 11 receives from Bus Interface Unit 10 the 18 bit update address BSAD 05-22, the 20 bit data word BSDTA, B, 00-15, BSDP 00, 08 and control signals all of which connect between FIFO 203 and their respective receivers 213, 215 and 217. An 18 line replacement address signal bus AORO 0525 22 connects between the input of LR 204 and a replacement address file (RAF) 206 output in address control unit 13. Signal buses FIFO 0017, FIFO 19-38 and FIFO 18, 39-43 connect between the FIFO 203 output and LR 204 input.

Also connected between the replacement and update unit 11 and the other units of cache 1 are control signals described infra.

A 20 bit data word signal bus DATA 00-19+ connects between the output of the buffer bypass driver 205 unit and a junction 216 in cache directory and data buffer unit 12."rhe 18 line update or replacement address signal bus FIFO 00-17+ connect between the output of LR 204 and one input of 2:1 MUX 208, and the 20 bit data output signal lines DATA 00-19- connect between the output of LR 204 and a cache data buffer 20 1. Read address counter output logic signal FRADDR and FRBDDR connect between FIFO R/W Control 230 and FIFO 203 as do write address counter output FWADDR and FWBDDR and Write Strobe signal FWRITE. Logic signal CYFIFO connects between FIFO R/W control 230, cycle control 232 and LR 204. Logic Signal FIFO 41 + connects between the FIFO bit position 41 output of FIFO 203 and FIFO read enable terminals for FIFO 00-17. Logic Signals FIFO 41- connect between the FIFO bit position 41 output of FIFO 203 and the RAF 206. FIFO 18, 42 and 43 connect between a Read Address Multiplexer 233 and their respective bit position outputs of FIFO 203. Logic Signal MEMREQ connects between cycle control 232, System bus control 219 and a 2:1 MUX 209 switch. CLOCK 0+ connects between Clock Control 220, cycle control 232 and other logic units described infra. Logic signal NO HIT+ connects between FIFO R/W control 230, cycle control 232 and NAND 231 of cache directory and data buffer Unit 12. Logic signal REPLACE connects between the LR 204 output, a 2:1 MUX 223 switch and a Round Robin 224 logic unit. Logic signal FEMPTYconnects between FIFO R/W control 230 and Clock Control 220. Logic signal CACHRQ connects between interface 6 and Clock Control 220 and logic signal CYCADN connects to interface 6 from cycle control 232.

FIFO 203 is organized as four 44-bit registers made up of random access memory chips 74LS 670 described on page 7-526 of the TTL Data Book for Design Engineers, second edition, copyright 1976 by Texas Instruments of Dallas, Texas. LR 204 is a 44 bit register made up of conventional flops using conventional design techniques. Address, data and control information are gated by logic signal buses FIFO 00-17, FIFO 19-38 and FIFO 18, 39-43 respectively. FIFO 19-38, the data signal bus is gated through buffer bypass drivers 205 by logic signal INTERG+ going high. Buffer bypass drivers 205 are made up of 74 367 circuits described on page 5-69 of the aforementioned TTL Data Book. FIFO R/W control 230 provides read address counter signals FRADDR and FRBDDR, write address counter signals FWADDR and FWBDDR, and a write strobe FWRITE to select the FIFO 203 registers for reading and writing. A FEMPTYsignal going high indicating that the FIFO buffer is not empty starts CLOCKO+ cycling in clock control 220. A FIFO 41 + signal low indicates that the LR 204 18 bit address field LR 0-17 will be filled from RAF 206 over the 18 line AOR 05-22 signal bus.

The replacement cycle is operative in response to the CPU 2 memory request logic signal CACHRQ. If the requested information is not in cache 1, a request for the information is sent by cache 1 to main memory 3 over bus 5. The requested information coming back from main memory 3 over bus 5 is sent to CPU 2 and written into data buffer 201. This operation is called replacement.

Cache 1 reads all information on bus 5 into FIFO 203. If that information was to update main memory 3, then cache 1 checks to see if that main memory 3 address location is stored in the data buffer 201. If the information address location is stored in the data buffer 201, then the data word in that location is updated with the new information data word. This operation is called update.

Cache Store and Data Buffer 12 - Figure 2, Sheet 4 The cache directory and data buffer 12 comprises the data buffer 201, the directory 202, 4 comparators 221 a-d, the 2:1 MUX 208, a round robin 224 logic unit, a 2:1 MUX 223, 18 inverters 225, NOR gates 260 and 261, NAND gates 262 and 263, 10 NAND gates each of 266a-j through 273a---j, a NAND gate 231 and junction 216. Data Buffer 201 further comprises a data buffer 264 for storing left bytes and a data buffer 265 for storing right bytes.

Signal busses are coded as follows in the 7 GB 2 056 135 A 7 specification and figures. For example, for row address ADDR 00-07-10, ADDR is the signal name. ADDR 00-07 refers to the 8 signal leads labelled ADDR 00, ADDR 01... ADDR 07.

ADDDR 00-07-indicates that the signals are low if they indicate a '1---and high if they indicate a "0". ADDR 00-07-10 indicates that this is signal bus 10 of 8 bit row address ADDR 00 07-, Main memory 3 address BAOR 05-22+ 75 signal lines connect between bus 6 and one input of 2:1 MUX 208 of the cache directory and data buffer 12. Address signal lines FIFO 00-18+, connect between the output of LR 204 and the other input of 2:1 MUX 208. 2:1 MUX 208 output signal bus ADDR 00-17+ connects to 18 inverters 225 whose output ADDR 00-17-10 splits into row address ADDR 00-07-10 and column address ADDR 08-17-10. Row Address ADDR 00-07-10 connects to directory 202 and to one input each of 4 comparators 22 1 a-d. Column address ADDR 08-17-10 connects to the data buffer 201, directory 202 and round robin 224. Row addresses ADDR 00-07-20,-21,-22 and -23 connect to the second input each of 4 comparators 221 a-d respectively. The 4 outputs of comparators 221 a-d, logic signals HITO-3+ connect to an input of 2:1 MUX 223. HITO+ connects to 10 NAND 226a-j and 10 NAND 270a-j inputs. HIT1 + connects to 10 NAND 267a-j and 10 NAND 271 a-j inputs. HIT2+ connects to 10 NAND 268a-j and 10 NAND 272a-j inputs. HIT3+ connects to 10 NAND 269a-j and 10 NAND 273a-j inputs.

The round robin 224 output, LEVEL 0-3+ connects to the second input of 2:1 MUX 223.

The output of 2:1 MUX 223, logic signals WRITE 0-3 connect to the inputs of 4 NAND 262 and 4 NAND 263 circuits. The output of the 4 NAND 262 circuits, logic signals WRITE 0-1 A, WRITE 2-1 A and WRITE3-1 A respectively connect to Levels 0- 3 respectively of data buffer 264. The output of the 4 NAND 263 circuits, logic signals WRITEO-1 B, WRITE 1 -1 B, WRITE2-1 Band WRITE3-1 B respectively connect to levels 0-3 respectively of data buffer 265. Logic signals WRITEO-3 are connected to inputs of 4 OR 274a--d, logic signal WRITEO-3-1 B connect to the other input of 4 OR 274a-d. The output of NOR 274a-d connects to LEVEL 0 through LEVEL 3 of directory 202.

Logic signal FIFO 18+ connects between the output of LR 204 bit position F/F 18 and an input to NOR 260. Logic signal FIFO 18- connects between the output of LR 204 bit position F/F 18 and an input to NOR 261. Logic signal BYTEMOD connects between the output of LR 204 bit position F/F 39 and the other inputs of NOR 260 and 261 whose outputs connect to the inputs of 4 NAND 262 and 4 NAND 263 circuits. The left byte signals DATA 00-09connect to the input Levels 0-3 of data buffer 264 and the right byte signals DATA 10-1 g- connect to the input levels 0-3 of data buffer 265. The outputs130 of levels 0-3 of data buffer 264, 10 signal line busses CADP 00-09,-10,- 11,-12 and -13 connect to the respective inputs of NAND 266a-j, 267a---j, 268a-j and 269a-j respectively. The outputs of levels 0-3 of data buffer 265, 10 signal line busses CADP 1019-10, -11, -12 and -13 connect to the respective inputs of NAND 270a-j, 271 a-j, 272a-j and 273a-j. Logic signal INTERGconnects to the 3rd input of NAND 266a-j through 273a-j whose outputs connect to junction 216. Data word signal bus CADP 0019+ connects between junction 216 and interface 6. The output signals HIT 0-3+ connect to the 4 inputs of NAND 23 1, the output of which connects to cycle control 232 and FIFO R/W control 230. 2:1 MUX's 208 and 223 are switched by logic signals ADDRSO+ and REPLACE respectively. Logic signal REPLACE connects to round robin 224.

Data buffer 201 is organized into data buffer 264 which stores the left byte DATA 00-09and data buffer 265 which stores the right bytes DATA 1019-. Each data buffer 264 and 265 is organized in 4 levels, each level storing 1,024 bytes in 1,024 byte locations address by 10 bit column address ADDR 08-17-10. 8 bytes are read out of data buffer 201 when data buffer 201 is addressed. Either a byte or a word is written into data buffer 201 depending on the control signal BYTEMOD (FIFO 39). If logic signal BYTEMOD is low then the outputs of NOR 260 or 261 are high, which gates the selected logic signal WRITEO, 1, 2 or 3 through the appropriate NAND 262 and 263 to writethe left byteof the data word in data buffer 264 and the right byte of the data word in data buffer 265. If logic signal BYTEMOD is high then either the output of NOR 260 or 261 goes high depending on the logic signal FIFO 18 inputs to NOR 260 or 261, thereby selecting one of the WRITE 0-3-1 A or one of the WRITE 0-3-1 B logic signals to write the selected byte in data buffer 201. Directory 202 is also organized in four levels of 1,024 memory locations in each level. Each memory location stores an 8 bit row address. When 10 bit column address ADDR 08-17-10 inputs to directory 202 ' four 8 bit row addresses ADDR 00-0720, -21,-22 and -23 are read out of the four levels of directory 202 to four comparators 221 a-d. These row addresses are compared with the input row address ADDR 00-17-10 and if there is an equal, that "hit" line HIT 0+, HIT 1 +, HIT 2+ or HIT 3+ goes high gating the selected output of data buffer 201 through the appropriate 266a-j through 273a-j circuits through junction 216 to CPU 2.

If a data word in data buffer 201 is to be replaced, round robin 224 selects the directory 202 and data buffer 201 level for replacement by setting one of the level signals LEVEL 0-3+ high. 2:1 MUX selects this signal since logic signal REPLACE is high and logic signal WRTPLS- enab les 2:1 MUX 223.

In an update mode the selected hit line HITO- 8 GB 2 056 135 A 8 3+ is switched through 2:1 MUX 223 and inverted by inverter 255 to enable the selected level of data buffer 201 to write the data word DATA 00-19- into the selected column address ADDR 08-17-10. 21 MUX 223 is enabled by logic signal WRTPLS-.

Round robin 224 has two, one bit by 1024 address random access memories (RAM). For each address location, there is stored 2 bits in each RAM which when decoded selects the next level of that column address to be replaced.

The directory 202 and data buffer 201 are designed using random access memory chips 93 LS 425 and round robin 224 is designed using random access memory chips 93 415, described on pages 7-119 and 7-70 respectively in the 80 Bipolar Memory Data Book, copyright 1977, by Fairchild Camera and Instrument Co. of Mountain View, California. Comparator 221 a-d logic circuits are made up of Fairchild TTL/MSI 93547 high speed 6 bit identity comparator circuits. 2:1 85 MUX 208 and 223 are 75S1 57 logic circuits described on page 7-181 of the aforementioned TTL Data Book.

Address Control Unit 13 -Figure 2, Sheet 2 Address control unit 13 includes the address register AOR 207, the replacement address file RAF 206, an adder 211, an AND gate 236, an AND gate 240, a NAND gate 241, an EXCLUSIVE OR gate 237, a 2:1 MUX 209, the read address multiplexer 233, a write address counter 234, and an AOR and RAF control unit 235. CPU2 address signal lines BAOR 05-22+ connect between interface 6 and one input of 2:1 MUX 209. Logic signal MEMREQ, connects between NAND gate 241 and the select terminal of 2:1 MUX 209. Logic signal MEMREG- and CYWTO connect between cycle control 232 and inputs to the NAND gate 241. The output of adder 211 signal lines AOR 05-22+ connects to the other 105 input of 2:1 MUX 209 whose output signal lines BAOR 05-22 connects to the inputs of AOR 207 and RAF 206. Signal BAOR 05-22 +10 connects between the output of AOR 207 and the inputs to adder 211 and driver 212. AOR 207 is 110 organized as an 18 bit register made up of conventional flops. RAF 206 is organized as four 18 bit registers and is designed using the aforementioned random access memory chips 75 LS 670. The logic signals ADDRRO and ADDRI11 connect between the write address counter 234 115 and RAF 206, AOR and RAF control 235, AND gate 236 and EXCLUSIVE OR gate 237. Logic signal CYWOconnects between cycle control 232 and an inputtoAND 236. The output of AND 236 connects to the +2 terminal of ADDER 211.

The output of EXCLUSIVE OR 237-connects to the input of AND 240 whose output connects to the + 1 terminal of ADDER 211. Logic signal CY0LTO+ connects between cycle control 232 and the other input of AND 240. Logic signals ADDRWD+OB and ADD+0A connect between the read address multiplexer 233 and 125 RAF 206. An AORCNT logic signal connects between AOR and RAF control 235 and write address counter 234. Logic signals BAWRIT and BAORCK connect between AOR and RAF control 235 and RAF 206 and AOR 207 respectively.

For the interleaved memory operation the address control unit 13 logic loads AOR 207 with PRA, the CPU memory request address to send out on bus 5 to main memory 3 in a format 8b of Figure 8 during a first memory request cycle. AOR 207 is then loaded with PRA+ 1 which is the memory request address sent out on bus 5 to main memory 3 in the format 8b of Figure 8 during the second memory request cycle. RAF 206 is loaded with PRA, PRA+t PRA+2 and PRA+3 in successive locations under control of write address counter 234, adder 211 and AOR and RAF control 235. These addresses are supplied to the address field of LR 204 when information in the format 8c of Figure 8 are sent from main memory 3 to cache 1 over bus 5. For the banked memory operation, the address control unit 13 logic loads AOR 207 with PRA, the CPU2 memory request address, which is sent out on bus 5 to main memory 3 in the format 8b of Figure 8 during the memory request cycle. RAF

206 is loaded with PRA and PRA+1 in successive locations under control of the write address counter 234. These addresses are supplied to the address field of LR204 when information in the format of Figure 8c are sent from main memory 3 to cache 1 over bus 5. The read address multiplexer 233 selects the RAF 206 address locOon to be read out of LR 204 for each main memory 3 response over bus 5 to the read request of cache 1. The adder 211 output signal lines AOR005100 22+ provide the address stored in AOR 207 incremented by + 1 or +2 under control of AND 236 and 237. If the write address counter 234 is set at location 03, logic signals ADDRRO+ and ADDRR 'I + are high, therefore AND 236 enables the +2 input of adder 211. If the write address counter is set at locations 01 or 02 then the output of EXCLUSIVE OR 237 enables the + 1 input to adder 211. The adder 211 is a 74 283 logic circuit described on page 7-415 of the aforementioned TTI Data Book.

During the 0LT mode the logic signal CYO.LTO- input to AND 236 is low keeping the +2 input to ADDER 211 low. Logic signal CY0LTO+, the input to AND 240 enables the + 1 input to ADDER 211.

Cache CPU Interface Unit 6 Cache CPU Interface Unit 6 includes an 18 line address signal bus BAOR 05- 22, a 20 line data signal bus CADP 00-19 and a control signal bus containing a number of signal lines. Two of the control signal lines CACHRO, the cache request logic signal, and CYCADN, the cache done logic signal, are described herein.

System Bus 5 Control Signals The signals listed below are the bus 5 control signals necessary to describe the invention.

9 GB 2 056 135 A 9 Memory Reference (BSIVIREF) BSMREF high indicates that the address leads BSAD 05-22 contain a memory 3 word address.

BS[VIREF low indicates that the address leads BSAD 08-23 contain a channel address and a function code.

Bus Write (BSWRIT) BSWRIT high indicates that a master unit is requesting a slave unit to execute a write cycle.

Second Half Bus Cycle (BSSHBC) 13SSHI3C high indicates that main memory 3 is sending to cache 1 information previously requested by cache 1 Double Pull (BSDBPL) BS1313PI--- is high when sent from cache 1 to main memory 3 to signal main memory 3 to read data in double pull mode.

BSDBPL is high when sent from main memory 3 to cache 1 with the first word of a two word 75 response to a memory request.

13SDI3PI--- is low when sent from main memory 3 to cache 1 with the second word of a two word response to the memory request.

This enables main memory 3 to send one or two words to cache. If, for example, PRA is the high order address of a memory bank then 13SDI3PI--will be low indicating that only one word will be transferred in response to the memory request.

My Acknowledge (MYACKR) MYACI(R when high is sent by cache 1 to system bus 5 to indicate that cache 1 is accepting a system bus 5 data word transfer from main 90 memory 3.

My Bus Request (MYREQT) MYREOT when high is set by cache 1 to system bus 5 to indicate that cache 1 is requesting a system bus 5 cycle.

My Data Cycle Now (MYIDCNN) MYXI\IN high indicates that cache 1 is transferring information over system bus 5 to main memory 3.

Data Cycle Now (BSDCNN) 13SDCNN high indicates that main memory 3 has placed information on the bus 5 for use by cache 1.

Acknowledge (13SACKR) BSACKR high indicates to cache 1 that main memory 3 has accepted the memory request sent by cache 1.

Wait (BSWAIT) BSWAIT high indicates to cache 1 that main memory 3 is busy and cannot accept the memory request at this time.

Bus Request (BSREOT) 13SREOT high indicates to cache 1 that a system coupled to bus 5 has requested a bus cycle.

Byte Mode (BSBYTE) BSBYTE high indicates a byte transfer rather than a word transfer.

Master Clear (CLEAR-) CLEAR- low initializes the cache by resetting the logic. When CLEAR- rises the QU operation is started.

Clock Control 220 - Figure 3, Sheet 2 The cache request logic signal CACHRQ, Figure 3, connects to a RESET terminal of a flop 301 and to an input terminal of a NAND 302. A clock signal CLOCKO+ connects to the CLK terminal of flop 301. The U output of flop 301 connects to the second input of NAND 302. The CPUREQ+OA output of a NAND 306 connects to the third input of NAND 302 whose output connects to an input of 30 ns delay line 303 and an input of NAND 304. The output of delay line 303 connects to the other input of NAND 304. The Q output of flop 301, logic signal BLKI'lEG+ connects to a D and RESET input of flop 305. The logic '1---signal connects to the SET input of flop 305. A MYACKR logic signal connects to the CLK input of flop 305. The Q output signal INTERG+ connects to buffer bypass drivers 205 and the U output signal INTERGconnects to the input of the HITO-3+ NAND gates 266a-j to 273a-j in the cache directory and data buffer unit 12. Logic signal FEMPTY-20 connects to an input of AND 324 and to the input of inverter 307. A logic signal MEIVIREQ, connects to an input of NAND 306. A logic signal ADDI1S0-, the U output of flop 309 connects to another input of NAND 306. Logic signal CYQLTO+ connects between cycle control 232 and the third input of NAND 306. Logic signal ADDRSO+, the Q output of flop 309, connects to the select input of 2AIVILIX 208 in cache directory and data buffer unit 12. The output of NAND 308 connects to the SET terminal. CLOCKO+ connects to the CLK terminal and a general clear CLEAR signal connects to the reset terminal of flop 309. Logic signals CYFIFO+OA and CYWRIT+OA connect to respective inputs of NAND 308. A CPUREQ logic signal connects the NAND 304 output to a SFT terminal of flop 313. An FEMPTY- logic signal connects to a RESET terminal of flop 313 from an inverter 319 output. A U output terminal logic signal FEMPTY+20 and a Q output logic signal FEM PTY-20 of flop 313 connect to the respective input of a NOR 310. A CYREAD logic signal connects between the Q output of a flop 330 and the third input of NOR 310 and CLOCKO+ connects to the fourth input of NOR 3 10. The output of NOR 310 connects to an input of NOR 311. The CLOCKO+ connects to an inverter 312 input. a CLOCKO- input signal of inverter 312 connects to an input of NAND 315.

Clock control 220 provides a timing signal CLOCKO+ to time the logic circuits of cache 1.

GB 2 056 135 A 10 CLOCKO+ starts cycling on either a CPU2 memory request or by FIFO 203 being loaded with information from bus 5. In the case of the CPU2 memory request, logic signal CACHRQ, the input to NAND 302 is forced high, which sets the output low. The other two inputs to NAND 302 BLI(REQ- and CPUREQ+OA are high at this time.

Flop 301 is not set so the U output is high and both inputs to NAND 306 are low so the output is high. When the output of NAND 302 goes low, one input of NAND 304 goes low and 30 nanoseconds later the other input goes low due to the delay in delay line 303. The delayed signal low sets logic signal CPUREG.high. Logic signal CPUREQ the SET input of flop 313 high sets the Q 80 output FEMPTY-20 low. Flop 313 is a 74S74 logic circuit which has both the Q and Cl outputs high when both the SET and PRESET inputs are low. Flop 74S74 is described on page 5-22 of the aforementioned TTL Data Book.

The logic signal FEMPTY-20 low sets the output of NOR 310 high forcing the timing signal CLOCKO+ output of NOR 311 low. Fifty nanoseconds later, the output of delay line 314 forces the other inputs of NOR 311 low forcing timing signal CLOCKO+ high. Timing signal CLOCKO+ going high sets flop 301 setting the Q output logic signal BLI(REQ- low, this forces the output of NAND 302 high forcing the NAND 304 output logic signal CPUREQ, the SET input to flop 313, low. This sets flop 313 and logic signal FEMPTY-20 is forced high keeping the timing signal CLOCKO+ output of NOR 311 high. Timing signal CLOCKO+ remains high as long as logic signal CACHRQ remains high. Logic signal CACHRQ will remain high until CPU2 receives the 100 requested data word and the cache done logic signal CYCADN is sent to CPU2.

Flop 313 which controls the start of cycling of CLOCKO+ is also controlled by the loading FIFO 205. The read address counter flops 316 and 317 in FIFO R/W control 230 advance to the next location after receiving acknowledged information from bus 5 (BSACKR high). This sets the output of comparator 318, logic signal FEMPTY+ low, setting the inverter 319 output logic signal 110 FEMPTY- high. With the RESET input logic signal FEMPTYof flop 313 high, the U output logic signal FEMPTY+20 goes low starting the timing signal CLOCKO+ cycling as before. In this case, timing signal CLOCKO+ cycles as long as there is 115 information in FIFO 203, and logic signal FEMPTY- keeps going low and logic signal CYREAD the input to NOR 310 is low.

CPUREQ+OA output logic signal from NAND 306 stays low as long as the MEIVIREO, or ADDRSOinputs to NAND 306 are high. This prevents a second CPU2 memory request cycle if logic signal CACHRQ is again high until the responses to the main memory 3 requests as a result of a previous CPU2 memory request is sent to cache 1. MYACKR logic signal going high at the start of the main memory 3 response to the CPU2 memory request sets flop 305, setting logic signal INTERG+ high to gate buffer bypass drivers 205 to send the CPU2 requested data (PRA) directly out on interface 6. 1 NTERG- when high gates NAND 266a-j through 273a-j in cache directory and data buffer 12 to allow the selected word from data buffer 201 to be sent to CPU 2 if the data word was stored in data buffer 201 when logic signal CACHRO, was set high. The logic signal FEMPTY+30 input to the SET terminal of flop 301 assures that the flop 301 does not set when logic signal CACHRQ comes high during a FIFO 203 cycle. Flops 301, 305 and 313 are 74S74 logic circuits described on page 5-22 of the aforementioned TTL Data Book. Flop 309 is a 74S '175 logic circuit described on page 5-46 of the TTL Data Book.

Detailed Description of FIFO R/W Control 230 - Figure 3, Sheets 1 Et 2

In Figure 3, the output of a NAND 324 connects to the SET input, a general clear signal CLEAR connects to the RESET input and timing signal CLOCKO+ connects to the CLK input of a flop 323. The Q output logic signal CYFIFO connects to a NAND 315 input. Timing signal CLOCKO- connects between the inverter 312 output and the other input of NAND 315. The Q output, logic signal CYFIFO also connects to cycle control 232. The U output connects to the input of AND 324. Logic signal FEMPTY-20 connects to the other input of AND 324. A BUMPUP logic signal output of NAND 315 connects to the CLK inputs; and CLEAR connects to the RESET inputs of flops 316 and 317. The logic---1 " signals connect to the J, K and PRESET inputs of flop 316, and the PRESET input of flop 317. The 0 output of flop 316 connects to the J and K inputs of flop 317 and to a comparator 318 input. The Q output of flop 317 connects to comparator 318. The U outputs of flop 316 and 317 connect to the read address select terminals of FIFO 203. A MYACKR+ logic signal and a BSSHBC logic signal connect to NAND 322 whose output, logic signal F plus 1 connects to the CLK inputs of flops 320 and 32 1. CLEAR logic signals connect to the RESET inputs of flops 320 and 32 1. Logic--1---signals connect to the J, K and PRESET inputs of flop 320 and the PRESET input of flop 32 1. The Q output of flop 320 connects to comparator 318 and the J and K input of flop 32 1.

The Q output of flop 321 connects to comparator 31 8. The U outputs of flops 320 and 321 connect to the write address select terminals of FIFO 203. FIFO 41 + logic signal connects to the read enable terminals of address field FIFO bit positions 00-17 of FIFO 203. A ground signal connects to the read enable terminals of the data and control field FIFO bit positions 18-43 of FIFO 203. FIFO 41 + connects to the SET input of LR 204 replace-update bit position 41 flop. Logic signals CYFIFO and REPLACE connect to input terminals of NOR 325 whose output connects to a NOR 327, whose output logic signal CYWRIT+DA connects to the SET input of flop 330 and an input of NAND 308. Timing signal CLOCKO- connects to the CLK terminal, and R 11 GB 2 056 135 A 11 CLEAR connects to the RESET terminal of flop 330 whose Q output, logic signal CYWRIT connects to 2:1 MUX 223 and whose Cl output logic signal CYREAD connects to round robin 5 224 and an input to NOR 310. Logic signal 13SDMN+ connects to the input of an inverter 326 whose output connects to the inputs of delay lines 328 and 329. Delay line 328 output connects to an input of inverter 331 whose output connects to an input of NAND 332. The output of delay line 329 connects to the other input of NAND 332 whose output logic signal FWRITEconnects to the write enable terminal of FIFO 203. Logic signal NOHIT+ connects to an input of inverter 334 whose output logic signal NOHITconnects to an input of a NOR 340 and to an input of NOR 333 whose output connects to the other input of NOR 327. Logic signals CYFIFO and UPDATE connect to the other inputs of NOR 333. Logic signal CYQ1-TO- connects between cycle control 232 and the input to NOR 340 whose output connects to an input of NOR 325.

Bus 5 logic signals 13SACKR, BSWRIT and BSMREF connect between receiver 217 and a NAND 337 whose output connects to a NOR 336 whose output logic signal FPLUS 1 connects to the CLK inputs of flops 320 and 32 1. The output of NAND 322 connects to the other input of NOR 336.

Logic signal BSDCNN+ goes high at the start of every main memory 3 to cache 1 data transfer cycle, is inverted by inverter 326, is delayed 10 nanoseconds by delay line 328, and is again inverted by inverter 331 appearing at the first input of NAND 332 as a delayed positive logic signal. The output of delay line 329 is a negative going logic signal appearing at the second input of NAND 332 delayed 40 nanoseconds. The 2 inputs to NAND 332 are positive for 30 nanoseconds forcing the FWRITE write enable input to a negative going pulse 30 nanoseconds wide, delayed 10 nanoseconds from the rise of BSDCNN+ . This strobes the bus 5 information at the output of receivers 213, 215 and 217 into a location of FIFO 203 defined by the 5 outputs of the write address flops 320 and 32 1, logic signals FWADDR- and FW13DDR-. MYACKFI goes high, if a cache identification AND 546 output, Figure 5, goes high indicating that cache ID 0002, was received from bus 5 through receiver 213 and that this is not a main memory 3 write operation. When 13SDMN+ delayed 60 nanoseconds by delay line 522 goes high, flop 516 sets and logic signal MYACKR, the input to NAND 322 goes high. Since this is a response to a memory request, BSSHBC is high forcing the output of NAND 322 logic signal F PLUS 1 low. Forcing the CLK inputs of flops 320 and 321 low increments the write address counter flops 320 and 32 1.

Since the output logic signals FWADDR+ and FW13DDR+, of the write address counter flops 320 and 321 and logic signals FRADDR+ and FR13DDR+, outputs of the read address counter flops 316 and 317 are no longer equal, logic signal FEMPTY+, the output of comparator 318 goes low, starting CLOCKO+ cycles as previously described in Clock Control 220.

Write address counter flops 320 and 321 and read address counter flops 316 and 317 are conventional X flops 74S 112 described on page 5-24 of the aforementioned TTL Data Book and they operate in the following manner. Assume flops 320 and 321 are both reset, that is the outputs FWADDR- and FW13DDIR- are high.

When FPLUS 1 goes low, flop 320 sets on the fall of logic signal FPLUS 1. The Q output of flop 320 being low kept flop 321 reset. With flop 320 set and its Q output high, flop 320 resets and flop 321 sets on the next fall of logic signal FPLUS 1.

On the next fall of logic signal FPLUS 1, both flops 320 and 321 are set and on the fourth fall of logic signal PLUS 1, both flops are reset. The rise of CLOCKO+ sets flop 323 and its Q output, logic signal CYFIFO goes high. When CLOCKO+ next goes low, both logic signals CYFIFO and CLOCKOinput to NAND 315, go high forcing the output logic signal BUMPUP low, advancing the read address counter flops 316 and 317. The inputs to comparator 318 signals FWADDR+ and FW13DDR+ are equal to FRADDR+ and FR13DDR+ thereby setting FEMPTY+ high. This prevents timing signal CLOCKO+ from cycling if no bus 5 cycle logic signal BSDCNN+ is present. Logic signal FEMPTY+ is inverted by inverter 319 and the output logic signal FEMPTY- going low sets the FEMPTY+20 output of flop 313 high, forcing the output of NOR 310 low, forcing the CLOCKO+ output of NOR 311 high. Logic signal CYFIFO, Figure 2, going high sets the FIFO 203 output of l 00 the location indicated by the read address counter flops 316 and 317 (FRADDR- and FR13DDR-) into LR 204. If the information in FIFO 203 is a response to a memory request, FIFO 41 + is high. This lets LR 204, F/F 41, Figure 3, so that its Q output, logic signal REPLACE is high. The output of NOR 340 is high during the QLT mode since the logic signal CYQ1-TO- is low. This sets the output of NOR 325 low and the output of NOR 327 high, so that at the next rise of CLOCKO+, flop 330 sets and the Q output logic signal CYWRIT goes high and continues cycling under control of the logic signal CYFIFO input to NOR 325 for the remainder of the QLT operation.

During normal operation, logic signal CM1-TO-, the input to NOR 340 is high. Therefore, in a replacement mode with logic signals REPLACE and CYFIFO high if the directory 202 search results in a---NOHIT", then the 3 inputs to NOR 325 are high, its output is low setting the output of inverter 327 high, so that at the next rise of CLOCKO+, flop 330 sets and the Q output logic signal CYWRIT goes high indicating that this is a cache write cycle. Flop 309 of clock control 220 was previously set since CYWRIT+OA and CYFIF0i+0A were low in previous cycles setting the Q output ADDRSO+ high, switching 2:1 MUX 208 Figure 2, to receive memory address BAOR 05-22+. At the rise of CLOCKO+, logic signal CYFIFO+OA is high, since flop 323 is not Set and theld output which is high 12 GB 2 056 135 A 12 inputs AND 324. The FEMPTY-20 input to AND 324 is also high, forcing the CYFIFO+OA input to NAND 308 high, setting the output low. Since the SET input to flop 309 is low the Q output ADDFISO+ goes low, switching 2:1 MUX 208, Figure 2, to receive the FIFO 00-17+ address output from LR 204. Flop 323 when set is reset on the next rise of CLOCKO+ since the U output which inputs AND 324 is low, forcing the SET 10, input of flop 323 low, resetting flop 323 and the Q output logic signal CYFIFO goes low.

During an update operation logic signal 75 UPDATE, an input to NOR 333 is high. If the directory 202 indicates a "hit" then the output of inverter 334, logic signal NO HIT- is high. When logic signal CYFIFO is high, the 3 inputs to NOR 333 are high forcing the output low forcing the output of NOR 327 high. At the next rise of timing signal CLOCKO+, flop 330, sets as before indicating a cache write cycle.

Flops 323 and 330 are 74S1 75 logic circuits described on page 5---46of the aforementioned 85 TTL Data Book.

Detailed Description of AOR and RAF Control

25.235-Figure 4, Sheet 1 Read Address Multiplexer 233, and Write Address Counter 234, Figure 4, Sheet 2 The outputs of a NAND 417 and 418 connects to NOR 419 inputs. Logic signal BLOCKF+ connects between a NAND 417 and cycle control 232. Logic signal FEMPTY-20 connects between clock control 220 and an input to a NOR 442 whose output connects to the 3rd input of NOR 419. The output of NOR 419, logic signal AORCNT, connects to the inputs of delay lines 420 and 421, an input of a NAND 424 and an input to NAND 416. Logic signals MEIVIREQ- and CYQLTO+ connect between cycle control 232 and inputs to a NAND 441. Logic signal CYFIFO connects between FIFO R/W control 230 and another input of NAND 441 whose output connects to an input of NOR 442. Logic signals CYQLTO- 1 A and CYQ1-TO-013 connect between cycle control 232 and inputs to a NAND 443 whose output connects to an input of NOR 419.

The output of NAND 424, logic signal BAORCK connects to the AOR 207. The delay line 421 output connects to an inverter 423 input whose output logic signal AORCNT-30 connect to the CLK inputs of flip 426 and 427. The delay line 420 output connects to an inverter 422 input whose output connects to inputs of NAND 416 and NAND 424. Logic signal BAWRIT connects between the output of NAND 416, the input of 55 NAND 425, and the WRITE strobe terminal of RAF 120 206. Logic signal MEMREQ connects to NAND 425 input, the RESET input flops 412 and 413 and cycle control 232. The output of NAND 425 connects to the reset terminals of flops 426 and 60 427 and the J and K inputs of flop 427. The Q output of flop 426, logic signal ADDRRO+ connects to the Write Address terminal 2 of RAF 206 and connects to the input of NAND 418.

Logic signal MYACKR connects between another input of NAND 418 and cycle control 232. The'd output of flop 426 logic signal ADDRROconnects to the inputs of NAND 417 and NAND 424. The Q output of flop 427, logic signal ADDRRI+ connects to the Write Address terminal 1 of RAF 206 and the input of NAND 417.

Logic signal BSDCND+ connects between cycle control 232 and the CLK terminal of a flop 409. Logic signal BSAD 23+ connects to the SET input of flop 409 and the output of Receiver 217. Logic signal MYACKD connects between cycle control 232 and input of NAND 410 and 411. The Q output of flop 409, logic signal BSAD23+1 0, connects to the other input of NAND 410. The 5 output of flop 409, logic signal BSAD 23-10, connects to the other input of NAND 411. The output of NAND 410 connects to the CLK terminal of flop 412 and the output of NAND 411 connects to the CLK terminal of flop 413. Logic -1 " signal connects to the PRESET, J and K terminals of flops 412 and 413. The Q output of flop 412, logic signal FCHONE+ connects to the input of FIFO bit position 43 of FIFO 203, Figure 4. The Q output of flop 413, logic signal FCHZRO+, connects to the input of the FIFO bit go position 42 of FIFO 203. Logic signal BSAD23+ connects to the input of the FIFO bit position 18 of FIFO 203. The output of the FIFO bit position 18 connects to a select terminal 1 of MUX 414 and 415. The MUX's are 74S1 53 dual 4 lines to 1 line Data Selectors/Multiplexers described in page 5-42 of the aforementioned TTL Data Book. Terminal 1 of a Banked-interleaved select switch 407 is connected to ground. Terminal 2 is connected to logic "'I ". Logic signal BANKED+00 connects between terminal 3 and an input to inverter 408 whose output logic signal ADDRWD+ connects to select terminal 2 of 4:1 MUX 414 and 415. Logic signal BANKED +00 also connects to cycle control 232. The enable input and the terminal 2 input of 4:1 MUX 414 are connected to ground as is the enable input and the terminal 0 input of 4:1 MUX 415. Input 3 of 4:1 MUX 414 and input 1 of 4:1 MUX 415 are connected to logic -1 ". Input 0 of 4:1 MUX 414- and input 2 or 4:1 MUX 415 connect to the FIFO bit position 42 output of FIFO 203 and input 1 of 4:1 MUX 414 and input 3 of 4:1 MUX 415 connect to the FIFO bit position 42 output of FIFO 203. The outputs of MUX 414 and 415, logic signals ADDRWD+OB and ADDRWD+OA connect to the Read Address terminals 1 and 2 respectively of RAF 206 and also connect to cycle control 232. Logic signal FIFO 41 - connects to the read enable input of RAF 206. Logic signal BSDCNB+ connects between the RESET input of flop 409 and cycle control 232.

When CACHRQ, Figure 3, goes high indicating that CPU2 is requesting a data word and CPU2 also sends the main memory 3 address location BAOR 05-22+, Figure 2, of the requested data word, the address BAOR 05-22 (PRA) appears at the inputs of AOR 207 and location 00 of RAF 206. In addition, the address is sent to directory 13 GB 2 056 135 A 13 202 and data buffer 201 as row address ADDROO-07-1 0 and column address ADDR 08-17-10. 2:1 MUX 208 is switched by ADDRSO+ high to input BAOR 05- 22+ and a 5 directory 202 search is started. When FEMPTY-20, the output of flop 313, Figure 3, goes low the AORMT output of NOR 419, Figure 4, goes high, one input to NAND 416 and 424 high. Since the other inputs to NAND 416 and 424 are high logic signals BAWRIT and BAORCK 75 go low. 50 nanoseconds later the output of delay line 420 goes high setting the output of inverter 422 low, setting the outputs of NAND 416 and 424 logic signals BAWRIT and BAORCK high.

PRA is strobed into AOR 207 and into location 00 80 of RAF 206 when BAWRIT and BAORCK are low.

Logic signal AORCNT going high is delayed 70 nanoseconds by delay line 421 and is inverted by inverter 423. Inverter 423 output logic signal AORCNT-30 going low advances Write Address 85 Counter 234 to location 01. The Write Address Counter is made up of JK flops 426 and 427 whose operation has been described supra. Logic signals ADDRRI+ is now high and ADDRRO+ is 25 low setting the Write Address in RAF 206 to location 01. Assuming the data requested by CPU2 of Cache 1 is not stored in Cache 1 then MEMREQ+, Figure 5, is forced high. In Figure 2 logic signal MEMREQlow forces the output of NAND 241 high which transfers 2:1 MUX 209 to 95 receive the AOR005-22+ output of ADDER 211. Since logic signal ADDRR1 + is high and logic signal ADDRO+ is low, the + 1 output of EXCLUSIVE OR 237 is high forcing PRA+1 on the address signal lines AOR005-22+ and on the 100 2:1 mux 209 output signal lines BAOR 05-22.

During normal operation for both banked and interleaved memories the first memory request is sent to main memory 3 over bus 5 and an acknowledge signal BSACKR returned by main memory 3 to cache 1 over bus 5 sets logic signal BLOCKF+ high, Figure 5. When BLOCKF+ goes high the 3 inputs to NAND 417, Figure 4, are high setting the output low. This sets the output of NOR 419 logic signal AORMT high which sets logic signal BAWRIT, the RAF 206 write strobe, and logic signal BAORCK the AOR 207 strobe low, as described supra. This sets PRA+ 1 into AOR 207 and location 01 of RAF 206. Logic signal AORCNT-30 going low as before advances 115 the write address counter 234 to location 02. For location 01 logic signal ADDRRI+ is high and logic signal ADDRO+ is set low. The fall of logic signals AORCNT-30 sets logic signal ADDRRO+ high and sets ADDRRI+ low and the Write Address Counter 234 addresses location 02. The banked memory system now awaits the main memory 3 response to the first memory request whereas the interleaved memory system sends a second memory request.

At the end of the second memory request cycle logic signal MYACKR+, Figure 4, goes high to start the first main memory 3 to cache 1 data response cycle. Since logic signal ADDRRO+ is also high the output of NAND 418 goes low 130 setting logic signal AORCNT, the output of NOR 419 high. As previously described, logic signal BAWRIT goes low setting PRA+2 into location 02 of RAF. In Figure 2, PRA+ 1 remains stored in AOR 207. When the Write Address Counter 234 is set at location 02 the output logic signals ADDRRO+ high and ADDRR1 + low results in the + 1 output from EXCLUSIVE OR 236. Since PRA+ 1 is applied to the input of ADDER 211 the output of ADDER 211 puts PRA+2 on the address signal lines, AORO 05- 22+ and BAOR 05-22, the output of 2:1 MUX 209. Note that logic signal BAORCK the write strobe for AOR 207 is not set low since the logic signal ADDRROinput to NAND 424 is low. The Write Address Counter 234 is advanced to location 03 when AORCNT-30 goes low as described supra and logic signal ADDRRO + and ADDRR 1 + are both set high. This results in the +2 output of AND 236, Figure 2, going high which sets the output of ADDER 211 to PRA+3. Logic signal MYACKR again comes high at the start of the second main memory 3 to cache 1 data word cycle in response to the first memory request again forcing logic signal AORCNT high. This forces logic signal BAWRIT low and forces PRA+3 into location 03 of RAF 206 and advances the Write Address Counter 234 to location 00.

For an interleaved memory 4 data words are transferred from main memory 3 to cache 1 over bus 5 on 4 separate bus 5 cycles. Figure 8C shows the format of the responses. The low order bit BSAD23 of the Function Code identifies whether the data word is in response to the first memory request or the second memory request for data words. Logic signal BSAD 23+ and the Function Code history flops 412 and 413 identify the location of RAF 206 that stores the main memory 3 address for the data word being transferred. The first data word is at the PRA main memory 3 location and transfers from main memory 3 cache 1 with the Function Code set to 00, BSAD 23+ the low order bit of Function Code 00, is low and sets into FIFO bit position 18 of FIFO 203 Figure 2, when the FIFO strobe FWRITE- goes low. Also, at this time the function history flops 412 and 413 are not set and the output logic signals FCHZRO+ and FCHONE+ are low setting the FIFO 42 and FIFO 43 bit positions low. With Switch 407 set to interleaved, the input to inverter 408 logic signal BANKED is low setting the output logic signal ADDRWD+ high, setting the SELECT terminal 2 high. This sets the 2 and 3 input terminals of 4:1 MUX 414 and 415 active.

FIFO 18 sets SELECT terminal 1 of 4:1 MUX 414 and 415 low setting input 2 active. Since FIFO 42 is low the outputs of 4:1 MUX 414 and 415 logic signals ADDRWD+OB and ADDRWD+OA are low which set the read address of RAF 206 to location 00 and PRA appears on address signal lines AORO 05-22, Figure 2, and is strobed into LR 204 when logic signal CYFIFO goes high. BSAD 23+ is low the U output of flop 409 which inputs NAND 411 goes high. Since BSAD 23+ is low the U output which inputs NAND 411 goes high, 14 GB 2 056 135 A 14 when logic signal BSDCND+ goes high. When logic signal MYACKD, the input of NAND 411 goes high the output of NAND 411 goes low setting flop 413 with the Q output signal FCHZRO+ high.

On the next bus 5 cycle the data word PRA+2 location in main memory 3 is transferred to cache 1 and the Function Code on bus 5 signal lines BSAD 18-23 is still 00 and BSAD 23+ the low order bit is low. In this case, in Figure 4, FIFO bit position 18 of FIFO 203 is set low and FIFO bit position 42 is high, since flop 413 is set with the Q output logic signal FCHRZO+ high. The outputs of 4:1 MUX 414 and 415, logic signal ADDRWD+OB is low and logic signal ADDRWD+OA is high since the 2 input terminal of 4:1 MUX 414 is -0- and the 2 input terminal of 4:1 MUX 415 is a -1 ", thereby resulting in that reading out location 02 of RAF 206 which has the P RA+2 address stored.

The third data word transfer cycle over bus 5 brings the data word from the P RA+ 1 main memory 3 locations with a Function Code of 01 In this case, BSAD 23+ is high and FIFO bit position 18 of FIFO 203, Figure 4, is high setting the 3 input terminal of 4:1 MUX 414 and 415 active. FIFO bit position, 43 is low and FIFO bit position 42 is a "don't care". In this case with FIFO 18 high the ADDRWD+ 013 output of flop 414 is high and the ADDRWD+OA output of flop 415 is low reading out from RAF 206 location 0 1 which contains PRA+1. BSAD 23 high causes flop 409 to set when logic signal BSDCND+ goes high, setting the Q output logic signal BSAD23 +10 high forcing the output of NAN D 410 low when logic signal MYACKD+ goes high. This sets flop 412 and its Q output logic signal FCHONE+ goes high. The 4th bus 5 cycle bringing the data word from the PRA+3 location in main memory3hasaFunctionCodeof0l.BSAD23 high as before sets FIFO bit position 18 high and FIFO bit position 43 is set high since logic signal FCHONE+ is high.

The output of 4:1 MUX 414 and 415 logic signals ADDRWD+OB and ADDRWD+OA are high 110 reading out RAF 206 location 03 which stores PRA+3. Flops 412 and 413 are reset when logic signal MEMREQ+ goes low.

For a banked memory, two data words are transferred from main memory 3 to cache 1 over bus 5 on two separate bus 5 cycles. In this case, switch 407 is set to terminal 2 (banked), setting the input of inverter 408 high, forcing the output logic signal ADDRWD + low. Also, for the banked memory, the function code is 00, as the response to the memory request. Therefore, BSAD23+ is low for both data words sent to cache 1 from main memory 3 over bus 5. FIFO bit position 18 of FIFO 203 is therefore low for both data words.

The select inputs of 4:1 MUX 414 and 415 of terminals 1 and 2 are both low thereby activating input terminal 0. When the first data word is read into FIFO 203 from bus 5, logic signals ADDRWD+OB and ADDRWD+OA are both low and PRA stored in location 00 is read out of RAF 206. Then, when logic signal MYACKD is forced high, the output of NAND 411 goes low, setting flop 413. BSAD23-1 0 G the output of flop 409 is high at this time. The G output FCHZRO+ flop 413 high is stored in FIFO bit position 42 on the next FWRITE enable pulse of FIFO 203. This forces the output of 4:1 MUX 414 ADDRWD+013 high, so that the address in RAF 206 location 01 (PRA+ 1) is transferred to LR 204 with the second data word in response to the memory request.

Flops 412,413, 426 and 427 are 74S l 12 logic circuits described on page 5-34 and flop 409 is a 74S 175 logic circuit described on page 5-46 of the aforementioned TTL Data Book.

In the initialization mode, the CLEAR- logic signal initialises the contents of AOR 207 to all zeros. This forces the adder 211 output to all zeros. Therefore, when the strobe signals BAOROCK and BAWRIT are forced low the adder 211 output of all zeros is written into AOR 207 and RAF 206 location 00.

In the 0LT mode the RAF write strobe BAWRIT and the AOR write strobe BAORCK are forced low when the 2 inputs to NAND 443 are forced low when the 2 inputs to NAND 443, logic signal CYQ1-TO-1 A and CYQ1-TO+013 are high. This forces the output of NAND 443 low, forcing the output of NOR 419, logic signal AORMT high. As previously discussed, write strobes BAWRIT and BAORCK are forced low. This sets PRA address location 0000 into AOR 207 and location 00 of RAF 206. The RAF Write Address Counter 234 is advanced to location 01 when logic signal AORMT-30, the output of inverter 423 is forced l 00 low. Logic signals ADDFIR l +, the Q output of flop 427 and ADDRRO-, the Q output of flop 426 are set high. This forces the + 1 terminal of ADDER 211, the output of EXCLUSIVE OR 237 high and signal lines AORO 05- 22+, the outputs of ADDER 211 are forced to hexadecimal 0001.

When logic signal BLOCKF+, the input to NAND 417, is forced high the 3 inputs to NAND 417, Figure 4, are high and the output is forced low forcing logic signal AORMT, the output of NOR 419. This forces write strobes BAWRIT and BAORCK low setting address location 0001 into RAF 206 location 01 and AOR 207. The write address counter 234 then advances to location 02. The Q output of flop 426, logic signal ADDRRO+ is set high and logic signal ADDRR1 +, the Q output of flop 427 is set low, in Figure 2, the output of EXCLUSIVE OR 237 logic signal +1 again goes high forcing the output of ADDER 211, signal lines AORO 05-22+ to 0002.

When MYACKR+ the input to NAND 418, Figure 4, goes high, the output is forced low, forcing logic signal AORMT, the output of NOR 419 high. In this case, write strobe address BAORCK remains high since the input to NAND 424, logic signal ADDRRO- is low. White strobe BAWRIT is forced low setting 000,002,, into location 02 of RAF 206. Write address counter 234 is advanced to location 03. Logic signal MYACKR+ again goes high and address location 0002 is stored in location 03 of RAF 206 and the GB 2 056 135 A 15 write address counter is advanced to location 00. 65 Locations 02 and 03 of RAF 206 are considered "dummy" locations and are not used in the OLT mode.

When the inputs to NAND 441, logic signals MEMREQ-, CYQLTO+ and CYFIFO are high, the output is low forcing the output of NOR 44 2 low, forcing logic signal AORCNT, the output of NOR 419 high. This sets address location 0002 into AOR 207 and RAF 206 location 00 and advances the write address counter 234 to location 01.

The above sequence continues until address location 4096 is set into AOR 207 and RAF 206 and the OLT operation is concluded.

Logic signal ADDRWD+, the output of NOR 408 remains high for the OLT mode since the input, logic signal CYQLTO- remains low. This forces terminals 2 of 4:1 MUX 414 and 415 high, since FIFO bit position 18 of FIFO 203, Figure 4, remains low. Select terminals 1 of 4:1 MUX 414 and 415 are forced low. Therefore input terminal 2 of 4:1 MUX 414 and 415 are active since select terminal 1 is low and select terminal 2 is high.

Detailed Description of Cycle Control 232

Figure 5, Sheets 1 Et 2 Logic signals MYACKI), BSDBPL-, BSWAIT, MY13CM+, MEMREQ+, BSDCND-, 13SACKR, CLEAR- and CI-RREQ-0A connect to system bus control 219. MEMREQ- connects to AOR and RAF control 235 and address control unit 13. Logic signals CYFIFO, CYREAD+ and FEMPTY+30 connect to FIFO R/W control 230. Logic signal NO HIT+ connects to directory 202. Logic signal MYACKI) connects to an input of NAND 506 and BSDBPL- connects to the other input of NAND 506 whose output connects to an input of NOR 507 whose output, logic signal DATACK- connects to the CLOCK inputs of flops 508 and 509. Logic signal BSWAIT connects to an input of NAND 505 and MYDCNN+ connects to another input of NAND 505 and a SET input to flop 504. Logic signal BLOCKF+ connects between the Q output of flop 504 and a third input to NAND 505 whose output connects to the other input of NOR 507. Logic signal 13SACKFI 110 connects to the CLOCK input of flop 504 whose U output logic signal BLOCKF- connects to an input to NOR 536. Logic signals MLT0-, NOHIT+, CYREAD+, and FEMPTY +30 connect to the inputs of NOR 501 whose output connects to an 115 input of NOR 502 whose output connects to the D input of flop 503. Logic signal MI-TO+M connects between a NOR 565 output and the PRESET input of flop 503. The U output of flop 503, logic signal MEIVIREQ-, connects to an input 120 of NOR 502 and logic signal MEIVIREQ+OC connects to another input of NOR 502. The CLOCKO+ signal connects to the CLK input of flop 503 whose Q output logic signal MEMREQ+ connects to the RESET inputs of flops 508, 509 and 504. Logic---1 " connects to the SET input of flop 508 whose Q output, logic signal DATCTO, connects to the SET input of flop 509 whose Q output, logic signal DATCTI, connects to an input of NAND 510 whose output, logic signal MEMREQ RESET, connects to the input of a NOR 566 whose output connects to the RESET input of flop 503. Logic signal CLEAR- connects between system bus control 219 and the other input of NOR 566.

Logic signals ADDRW13+0A and ADDRW+013 connect to the inputs of their respective inverters 523 and 524 whose outputs, logic signals ADDRM-0A and ADDRWD-013 connect to the inputs of AND 533 whose output connects to an input of NOR 527. FIF041 + connects to another input of NOR 527. Logic signal FEIVIPTY+30 connects to inputs of NOR 526 and Inverter 534 whose output logic signal FEMPTY-30 connects to another input of NOR 527. Logic signal CYREAD connects to inputs of NOR 526 and 527. Logic signal NOHIT+ connects to an inverter 525 input whose output logic signal CAHIT connects to an input of NOR 526. The outputs of NOR 526 and 527 connect to their respective inputs of NOR 528 whose output connects to the D input of flop 529. The Q output of flop 529 logic signal CYCADN+, connects to inputs of inverters 520 and 532. The output of Inverter 530 connects to the input of Delay line 531 whose output connects to the RESET terminal of flop 529. The output of Inverter 532, logic signal CYCADNconnects to cache CPU interface unit 6. CLOCKO+ connects to the CLK input of flop 529.

Logic signal BANKED+ connects between AOR and RAF control 235 and an input of a NAND 560 whose output connects to the input of NOR 536 and the PRESET input of flop 508. Logic signal CYGI-TO- connects to the other input of NAND 560. CYFIFO connects to the other input of NAND 510. Logic signals CYQ1- TO+ and CLEARconnect to inputs of a NAND 561 whose output connects to inputs of delay lines 562 and 563 and an inverter 567a. The output of delay line 562 logic signal CY0LT0+013 connects to the input of an inverter 564 and to AOR and RAF control 235. The output of inverter 564, logic signal MI- TO-1 B connects to an input of a NOR 565 whose output logic signal CYQLTO+ OD connects to the PRESET input of flop 503. The output of delay line 563, logic signal MI-TO +OC connects to the other input of NOR 565. The output of inverter 567, logic signal MI-TO-1 A connects to AOR and RAF control 235.

Logic signals REPLACE and FIFO 17+ connect between inputs of an AND 567 and LR 204. Logic signal CYWRIT connects between FIFO F1W control 230 and the 3rd input of AND 567 whose output, logic signal, MEIVIREQ+M connects between the input of a NOR 569 and a NAND 570. The output of NOR 569 logic signal ME[VIREQ+OC connects to an input of a NOR 502. Logic signal BAOR 10+ 10 connects between AOR 207, the input of an inverter 568 and theother input to NAND 570. The output of inverter 568, logic signal QLTDUNconnects to another input of NOR 569. The output of NAND 570 connects to the i RESET input of a flop 571. Logic signal 1 connects to the PRESET and D inputs and 16 GB 2 056 135 A 16 logic signal CLEAR- connects between system bus control 219 and CLK input of flop 571. The Q output logic signal CYQLTO+ connects to the round robin 224 and the 3rd input of NOR 569 and the U output, logic signal CYQLTO- connects to an input of AND 533. Logic signal CLIRREQ+013 connects between the output of NOR 536 and an input of NAND 535. Logic signals MY13CNN+ and 13SIDCND- connect to the other inputs of NAND 535.

During the normal CPU2 request mode the first memory request cycle flop 503 sets on the rise of CLOCKO+ if the CPU2 requested address PRA is not stored in the directory 202. The output of NAND 231, Figure 2, logic signal NO HIT+ is high forcing the output of NOR 50 1, Figure 5 low, forcing the output of NOR 502 high setting flop 503. The Q output logic signal MEIVIREQ+ going high sets the cycle request flop 511 of system bus control 219 to request a bus 5 cycle. The acknowledge response from main memory 3. logic signal 13SACKIR going high sets flop 504 whose Q output BLOCKF+ inputs the AOR and RAF control 235; this operation is described supra.

If there is a "hit" during the first memory request cycle, the logic signal NO HIT+ input to inverter 525 is low, setting the logic signal CAHIT input to NOR 526 high setting the input to NOR 528 low, setting the D input to flop 529 high. FEMPTY+30 is high at this time since FIFO 203 is empty. On the rise of timing signal CLOCKO+ flop 529 sets and the Q output logic signal CYCADN+ goes high forcing the output of inverter logic signal CYCADN- low which signals CPU2 that the requested data is available. Logic signal CYCADN+ is inverted by inverter 530, delayed 25 ns. by delay line 531 and resets flop 529. If there was not a---hiV in the first memory request cycle then during the cycle that sends the PRA data word from main memory 3 to cache 1 over bus 5, CYCADN+ is again set high as follows. The Read Address Multiplexer 233, Figure 2, output logic signals ADDRWD+OB and ADDIRWD+0A are low and are forced high by inverters 523 and 524 which set the output of AND 533 high, setting the output of NOR 527 low, setting the output of NOR 528 high, setting flop 529 as before. At this time FIFO 203 is not empty, and CYREAD is high since logic signal CYFIFO, Figure 3, has not cycled high.

Flops 508 and 509 are configured as a counter. For an interleaved memory, logic signal MYACKID goes high during each bus 5 cycle where the data word is sent from main memory 3 to cache 1 over bus 5 in response to a CPU2 request. Logic signal 13SDI3PL- goes low for the 2nd word of the 2 word response or if only one word is sent from main memory 3 to cache 1 over bus 5. Only one word may be sent to cache 1 if main memory 3 was busy to the 2nd word request from cache 1. This sets the output of NAND 506 low, forcing the output of NOR 507 logic signal DATACK- low setting flop 508 in response to the 2nd word received from main memory 3. DATACK- goes low for the 4th word 130 since MYACKID and BSID13PL- are again high setting flop 509 since the SET input logic signal DATCTO is high. The Q output of flop 509, logic signal DATCTI, going high sets the output of NAND 510, logic signal MEIVIREQ RESET low, resetting flop 503 through NOR 566. CLEAR- the other input to NOR 566 going low also resets flop 503. Flop 503 was held set through the logic signal MEMREQ- input to NOR 502 set low. This kept the SET input of flop 503 high at every rise of CLOCKO+. If the main memory 3 response to the 2nd memory request was logic signal BSWAIT high then the output of NAND 505 goes low forcing DATACK-, the output of OR 507 low thereby setting flop 508. Since the 2nd memory request is aborted if the main memory 3 response is BSWAIT, the Data Counter flop 508 must be set since only 2 data words will be received from main memory 3.

For the banked memory, the input to NAND 560, logic signal BANKED+, is high setting the output low which sets the PRESET input of flop 508 low setting the Q output, logic signal DATCTO, high. Since the banked memory system only makes one memory request and cache 1 received 2 data words in response, the 2nd data word in response will set flop 509 as above and reset flop 503. Logic signal MEMREQ+ going low resets flops 504, 508 and 509.

During a system initialization cycle, logic signal CLEAR- is transferred over bus 5 to receiver 217, Figure 2, as a negative going pulse which sets flop 571, Figure 5, on the rise of the trailing edge.

This sets logic signal CY0LTO+ high and logic signal CYQLTO- low.

The output of NOR 561 is normally high. When logic signals CLEAR- and CYQ1-TO+, the inputs to NOR 561 are high, the output is forced low. 160 ns. later, the output of delay line 562, logic signal CY0LT0+013 is forced low which forces the output of inverter 564, logic signal CYQLTO-1 B high. This signal inputs NOR 565. The other input to NOR 565, logic signal CYQ1-TO+OC, the output of delay line 563 is high at this time and remains high for 40 ns. This forces the output, logic signal CYQLT0+01D low for 40 ns. setting flop 503 and the Q output MEMREQ+ goes high starting a main memory 3 request cycle as before.

When logic signal MENIREQ+ is high, 2 bus 5 cycle requests are made by cache 1. The first request sends the even address to main memory 3 and the second request sends the odd address to main memory 3. The first data word sent to cache 1 from the even address location of main memory 3 to cache 1 sets the data counter, flop 508, Figure 5. The second data word to cache 1 cycle from the odd address location of main memory 3 sets the data counter flop 509 whose Q output logic signal DATCTI forces the output of NAND 510 low when CYFIFO is high thereby resetting the memory request flop 503 which in turn resets the data counter flops 508 and 509.

-During the second data cycle, the input to AND 567, logic signal FIFO 17 +, the low order address bit stored in LR 204, is high. The other inputs, 5Z 17 GB 2 056 135 A 17 logic signals CYWRIT and REPLACE going high force the output high. This forces the output of NOR 569, logic signal MEIVIREQ+OC low, forcing the output of NOR 502 high. On the next rise of 5 CLOCKO+ flip 503 sets and the G output, MEIVIREQ+, again goes high starting the next bus 70 5 cycle request.

The logic signal CY01-TO- input to NOR 501, which is low during the QLT mode, simulates a directory 202 "no hit- condition.

When the 4096 word is requested from main 75 memory 3 address location 7777, AOR 207, Figure 2, is incremented + 1 by ADDER 211. The next address 100008 is set into AOR 207 as described supra. The output line BAOR 10+ is high and inputs NAND 570, Figure 5. During the cycle when the 409611 data word is transferred from main memory 3 to cache 1 over bus 5 the inputs to AND 567, CYWRIT, REPLACE and FIF01 7+ are high forcing the output, logic signal MEIVIREQ+01) high. This forces the output of NAND 570 low resetting flop 571 and the G output, logic signal CY01-TO+ goes low. The logic signal QUDLIN- high input to NOR 569 prevents flop 503 from setting after the 4096th data word is received. Logic signal CYQLTO-, the input to AND 533 low, prevents flop 529 from setting during the QLT operation.

Detailed Description of System Bus Control

219 - Figure 5, Sheets 3 & 4 Logic signals BSAD 08-15-, 16+ and 17 connect between the receiver 213 output and an AND 546 whose output logic signal MYCHAN, connects to the SET input of flop 516. 13SIVIREF+ connects between receiver 217 and inverter 547 whose output BSMREF- connects to the AND 546 input. Logic signal BSDCNN+ connects between the receiver 217 cycle control 232, a delay line 522 input, and one input of an OR 521.

The output of delay line 522 connects to the other 105 input of OR 521 whose output logic signal BSDCNB+ connects to AOR and RAF control 235 and to the RESET terminal of flops 514, 516, 536, 574 and AOR and RAF control 235. The output of delay line 522, logic signal 13SDCND+, also connects to the CLK terminals of flops 516 and 536 and 574. Logic signal MYACKR connects between the Q output of flop 516 and the input terminals of delay lines 517, 518, AOR and RAF control 235, FIFO R/W control 230 and driver 218. The output of delay line 517 connects to an input of AND 520 whose output logic signal MYACKID connects to AOR and RAF 235 and to an input of NAND 506 in cycle control 232. The output of delay line 518 connects to an inverter 519 input whose output connects to the other input of AND 520. Logic '1 " signal connects to the SET input of flop 536 whose U output, logic signal 13SDCND-, connects to an input of NAND 535 in cycle control 232. Logic '1- signal connects to the PRESET and D inputs of flop 511.

The Q output of flop 511 logic signal CYREQ+ connects to an input of NAND 513. Logic signal BSBUSY- connects between an output of NOR 540 and the other input of NAND 513 whose output logic signal SETREQ- connects to a PRESET input of flop 515. Logic '1 " signal connects to a PRESET input of flop 514. Logic signal 13SIDCND+ connects to the D input and the RESET input.

MYMNN- connects beteen a 5 output of flop 541, the CLK input of flop 514 and the enabling inputs of drivers 212, 214 and 218. The Q output of flop 514 logic signal MYREQ+ connects to the CLIK input of flop 515. The CLEARlogic signal connects to the RESET input of flop 515. Logic signals BSWAIT and BLOCKF- connect to inputs of AND 512 whose output logic signal MYREQ+ connects to the D input of flop 515 whose Q output logic signal MYREQT connects to Driver 218 and an input to AND 542. BSDCNB+ connects to an inverter 544 input whose output connects to the input of AND 542 whose output, logic signal SETDCN- connects to the PRESET input of flop 541. Logic signals BSACKR and BSWAIT connect between inputs of NOR 543 and Receiver 217. The NOR 543 output connects to the RESET input of flop 541. CLEAR connects between an inverter 573 output and to the input of NOR 543. CLEAR- connects between an input of inverter 573 and receiver 217. BSDCNBconnects between the output of inverter 544 and an input of AND 538. BSREQT+ connects between the input of AND 538 and Receiver 217 and CLEAR connects to the input of AND 538 whose output connects to the input of delay line 539 and an input of NOR 540. The output of delay line 539 connects to the other input of NOR 540. The Q output of flop 541, logic signal MYMNN+ connects to driver 218 and the input of NAND 535 in cycle control 232. The output of NOR 536, logic signal BSDCNB- connects to the input of NAND 535. Priority logic signals 13SAU0K - BSIUOK connects between AND 542 inputs and receiver 217.

Logic signals MEMIREQ+ and CLIRREQ-0A connect between cycle control 232 and the CLK and RESET inputs respectively of flop 511. Logic signal 13SDI3PL+ connects between the SET input of flop 574 and receiver 217. The U output of flop 574 connects to cycle control 232.

During the first memory request cycle, if the CPU2 requested data is not in cache 1 then the MEIVIREQ+ CLK input to flop 511 goes high setting the Q output, logic signal CY1REQ+, the input to NAND 513 high. The logic signal BSBUSY- is high if the bus 5 is not busy and the output of NAND 513, logic signal SETREQ- goes low setting flop 515 whose Q output MYREQT goes high and inputs AND 542 requesting a bus 5 cycle. If bus 5 does not have a high priority request the logic signals 13SAU0K through BS1U0K are high, and if bus 5 is not transferring information then logic signal BCDCNB- is high and the logic signal SETDCN- output of AND 542 goes low setting flop 541 and the Q output MYMNN+ goes high gating drivers 212, 214 and 218 putting. out on bus 5 information in the format 86 of Figure 8. When main memory 3 18 GB 2 056 135 A 18 receives the bus 5 information, the acknowledge logic signal 13SACKFl is sent back to cache 1 over bus 5 and reset flop 541 by setting the NOR 543 output low. The G output, logic signal MYXI\IN-, going high sets flop 514 whose Q output logic signal MYREQR+ high, resets flop 515 since the D input logic signal MYREO, is low. This sets the Q output logic signal MYREQT low. A BSWAIT signal returned by main memory 3 indicating that main memory 3 is busy, resets flops 541 since the output of NAND 543 goes low. However, since the output of AND 512 is high when flop 514 sets and its G output logic signal MYREGR+ goes high, the G output of flop 515, logic signal MYREQT remains high and the first memory request is repeated.

In the interleaved mode when main memory 3 acknowledges the first memory request by sending the 13SACI(R logic signal, flop 511 remains set with the Q output logic signal 85 CYREQ+ high to start the second memory request cycle. Flop 511 remains set during the interleaved mode since the output of NAND 535 remains high as does the CLK input MEIVIREQ+. The CI-FIREC1+013 input to NAND 535 is low as long as BLOCKF- input to NOR 53 6 is high. Logic signal BLOCKF- goes low after the first BSACKR acknowledge. When MYDCNN+ goes high during the second memory request cycle flop 511 is reset since BLOCKF- is low.

However, if the system is in the banked mode flop 511 is reset since the output of NAND 535 in cycle control 232 goes low at the end of the first memory request cycle. Logic signal CLI1REQ+013, the input to NAND 535 is high forcing the output 100 of NAND 535, logic signal URREQ-0A low when MYXI\IN+ goes high. A second memory request cycle starts when logic signal BSREQT the input to AND 538 goes low when there is no request being made of bus 5. This forces the output of AND 538 low forcing the NOR 540 input low. 20 ns. later the other input to NOR 540 goes low forcing the output logic signal BSBUSY- high. Note that CLEAR is normally high and goes low during system initialization to reset functions.

With both inputs to NAND 513 high, the output, logic signal SETREQ- going low again sets the G output of flop 515 logic signal MYREQT high which requests a bus 5 cycle. Again the output of NAND 542 logic signal SET13CNgoes low setting flop 541 whose Q output logic signal MYXI\IN+ goes high gating drivers 212,214 and 218 to send out the second memory request in the format 8b of Figure 8 over bus 5 to main memory 3. If main memory 3 sends back the ackowledge logic signal 13SACKR flop 541 is reset as before which sets flop 514 which resets flop 515 setting the Q output logic signal MYREOT low. Logic signal MY13CNN+ the input to NAND 535 going high setsthe RESET input to flop 511 125 low setting the Q output logic signal CYREQ+ low thereby preventing subsequent memory request bus 5 cycles. Logic signal CLEAR the input to NOR 543 also resets flop 54 1.

If main memory 3 were busy and sent back a 130 BSWAIT logic signal in response to the second memory response, flop 541 resets since logic signal BSWAIT going high forces the NOR 543 output low, and the Q output of flop 541, logic signal MYDCNN- goes high setting flop 514 whose Q output logic signal MYREQR goes high. The D input to flop 5 15 is low since logic signal BLOCKF+ is high at this time forcing the output of NOR 572 low. This forces the output of AND 512, logic signal MYREQ+ low. When logic signal MYREQR + goes high flop 515 resets setting the Q output logic signal MYREOT low. Since flop 511 was reset during the second memory request cycle as before the second memory request is aborted. However, in the OLT mode logic signal CYQLTO-, the input to NOR 572 is low forcing the output high. When the BSWAIT response is given the output of AND 512 is high setting flop 5 15. The Q output logic signal MYREQT high starts another memory request.

The flops 503, 504, 511, 514, 515, 529, 541 and 571 are 74S74 circuits described on page 522 of the aforementioned TTL Data Book. Flops 508 and 509 are 74S1 12 logic circuits described go on page 5-34 and flops 516, 536 and 574 are 74S1 75 logic circuits described on page 5-46 of the aforementioned TTL Data Book.

Main memory 3 sends the logic signals BSDCNN+ and the information in the format 8c of Figure 8 out on bus 5 to receivers 213, 215 and 217 and the information is strobed into FIFO 203. BSAD 08-17 input AND 546 along with logic signal BSMREF- which was inverted by inverter 547. If the cache 1 identification is 0002., that is BSAD1 6+ is high and BSAD 00-15 and 17are high and that is not a main memory 3 write, i.e., BSMREF- is high, then the output of AND 546 logic signal MYCHAN goes high. Logic signal BSDCNN+ high sets the output of OR 521, logic signal BSDCNB+, high which sets the RESET input of flop 516 high. Logic signal BSDCNN+ is delayed 60 ns. by delay lines 522 and sets flop 516 whose output logic signal MYACKR going high advances the FIFO Write Address Counter flops 320 and 32 1, Figure 3. This operation was described supra. Logic signal MYACKR high sets flops 305, Figure 3, and the Q output logic signal INTERG+ going high gates the data through buffer bypass drivers 205, Figure 2, to junction 216, since this first data word from main memory 3 is in response to the CPU2 request. Logic signal MYACKR also goes out on bus 5 to acknowledge to main memory 3 that cache 1 received the information set out by main memory 3 addressed to cache 1. In Figure 5, logic signal MYACKR is delayed 20 ns. by delay line 517 and inputs AND 520 whose output, logic signal MYACKD goes high 20 ns. after the rise of MYACKR. Logic signal MYACKR is delayed 40 ns. by delay line 518, is inverted by inverter 519 and sets the other input of AND 520 low. Logic signal MYACKD is a positive going 20 ns. pulse delayed 20 ns. from the rise of MYACKR. Logic signal MYACKD delays the setting of the Function Code History flops 412 and 413, Figure 4, until after the data received 19 GB 2 056 135 A 19 from bus 5 is set into FIFO 203.

The above sequence is repeated in the 65 interleaved mode for the 4 cycles in which the data words are transferred from main memory 3 to cache 1 in response to the first and second memory requests. In the banked mode the sequence is repeated for 2 cycles in response to the one memory request.

System Bus 5 Formats Figure 8 shows the system bus 5 formats processed by cache 1 and/or main memory 3.

Figure 8 shows at 8a the memory address field with an 18 bit main memory 3 word address BSAD 05-22 of a 20 bit data word BSDT 00 15, A, B, DSDP 00, 08.Thisformatis used by CPU2 to update main memory 3 over system bus 5. Cache 1 reads the address and data in FIFO 203 from bus 5 through receivers 213, 215 and 217. Cache 1 senses that logic signal BSMREF is high, indicating that the address field contains a main memory 3 address, senses the BSWRIT is high indicating this is a write operation and checks if the address location is written into cache 1. If the address is found in directory 202, Figure 2, then the data word stored in data store 201 is updated. If the address is not in the directory 202, then the data is discarded. A 90 peripheral controller may send a 19 bit byte main memory 3 address BSAD 05-23. In that case, cache 1 would update byte 0 or byte 1 if either byte is stored in the data buffer 201.

Figure 8 shows at 8b the main memory 3 request sent from cache 1 to main memory 3. The address field contains the main memory 3 word address BSAD 05-22. The data field contains the 12 bit cache 1 identification code 0002, 13SDT A, B, 00-09 and the 6 bit function code 008 or 018, A function code of 008 designates the bus cycle as the first memory request cycle. The function code of 01, designates the bus 5 cycle as the second memory request cycle. BSMREF is high since this is a request of main memory 3.

Figure 8 shows at 8c the main memory 3 response format to the memory read request of 8b. The address field contains the destination number of cache 1, 0002. and the function code110 00,,, indicating a response to a first memory request or the function code 01. indicating a response to a second memory request, BSWRIT indicates that main memory 3 is requesting cache 1 to write the data word in cache 1 at the address indicated by the Figure 8 at 8b main memory 3 read request. 13SSHI3C high indicates that this is in response to a memory request. An interleaved memory main memory 3 request in the format 8b of Figure 8 contains PPA for the first request address and PRA+ 1 for the 2nd request address. Main memory 3 responds with the PRA and PRA+2 data words in response to the first request and the PRA+1 and PRA+3 data words in response to the 2nd request.

A banked memory main memory 3 request in the format 8b of Figure 8 contains PRA. Main memory 3 responds with the PRA and PRA+ 1 data words.

Main Memory 3-Data Buffer 201 Directory 202 Relationships Figure 11 illustrates the relationships of the 18 bit address ADDR 00-17 in main memory 3, data buffer 201 and directory 202.

The 262,143 word locations in main memory are addressed by the 18 bit, ADDR 00-17 100 address which is made up of a row address portion ADDR 0007 1 00a and a column address portion ADDR 07-17 1 00b. Main memory 3 may therefore be considered as organized into 1,024 columns and 256 rows.

The data buffer 201, Figure 12, has 4 levels, LEVEL 0-3 201 a-d. The column address ADDR 08-17 10 1, Figure 11, locates 4 words one from each level of data buffer 201. The directory 202, Figure 12, also has 4 levels, LEVEL 0-3 202a-d and the 18 bit address ADDR 00-17 102 Figure 11, is made up of a column address ADDR 08-17 102b and a row address ADDR 00-17 102a. Row addresses ADDR 00- 07 102a are stored in column address ADDR 08-17 102b locations of directory 202.

Figure 12 shows the relationships between data buffer 201, directory 202 and main memory 3 where main memory 3 is organized in a banked configuration. In the banked configuration the data words are stored in successive address locations. This is in contrast to the interleaved configuration in Figure 13 where data words in even address locations (ADDR 17 is a---01 are in one memory 3 bank and data words in odd address locations (ADDR 17 is a '1 ") are in the adjacent memory 3 bank.

Data buffer 201 comprises 4 levels, LEVEL 03 201 a-d, each level having 1, 024 data word address locations. Directory 202 comprises 4 levels, LEVEL 0-3 202a-d, each level storing 1,024 row addresses. For each data word location in data buffer 201 there is a corresponding location in directory 202 that stores a row address. The combination of column address and row address identifies the data word in data buffer 201 and main memory 3.

The example below will show the relationship between the main memory 3, data buffer 201 and directory 202. Assume the 20 bit data word in main memory address location 1025 is to be stored in level 1 of data buffer 201.

The data word DATAOO-1 9 in address location 1025 has the value of ADDR 00-17 as 002001, The column address ADDR 08-17 has a value of 0001.. The row address ADDR 00-07 has a value of 001.. The data word is written into the LEVEL 1 201 e location identified by column address 00018 of data buffer 201. The row address 001. is written into LEVEL 1 202e location identified by column address 0018.

Figure 13 illustrates the interleaved main memory 3 with all the even address locations, address bit ADDR 17 set to "0", in memory bank 3a and all the odd address locations, address bit GB 2 056 135 A 20 ADDR 17 set to---1 ", in memory bank 3b. In 65 Figures 12 and 13 the lines designated Col 1 through Col 1023 are not actual connections but rather indicate that a data word in a particular column of main memory 3 will be written into that column of data buffer 201 and the row address wili be written into that column of directory 202.

Description of Operation - Replacement 10 Figure 9 is a flow chart illustrating the sequence of operations that start when CPU 2 makes a request of cache 1 for a data word. The sequence starts in Block 901. CPU2 forces signal CACHRQ high which sets flop 313 Figure 3 forcing the Q output signal FEMPTY-20 low. Signal FEMPTY-20 low starts CLOCKO+ to cycle and sets the RAF 206 read address counter flops 426 and 427 Figure 4, to location 00. CPU2 sends the request address (PRA) signals BAOR 05-22+ through the 2:1 MUX 208, which is enabled by signal ADDRSO+, to directory 202 Figure 2 to perform the search.

The directory search is made in block 902 and PRA is loaded into AOR 207 and RAF 206 location 00 through 2:1 MUX 209. Signal FEMPTY-20 forces signal AORCNT, the output of NOR 419 Figure 4 high which enable signal BAWRIT, the RAF 206 write strobe, enables signal BAORCK, the AOR 207 write strobe, and advances the RAF 206 Write Address Counter flops 426 and 427 to location 01.

In block 903 the rise of CLOCKO+ set flop 301 Figure 3 whose U output signal BLI(REQ- resets flop 313. The Q output signal FEMPTY-20 is forced high keeping CLOCKO+ high.

If in block 904 PRA was found in directory 202 Figure 2, then in block 905 the data word in the corresponding data buffer 201 address location, signals CADP 00-19 are sent to CPU2. Also a directory "hit" results in the setting of flop 529 Figure 5 whose Q output is inverted and sent to CPU2 as signal CYCADN- where it strobes the data word into a register (not shown) and forces signal CACHRQ low.

* If in block 904 PRA is not stored in directory 202 Figure 2 then in block 906 flop 503 Figure 5 sets and the Q output signal MEIVIREQ+ sets flops 511 whose Q output signal CYREQ+ goes high. Also, PPA+ 1 appears at the output of ADDER 211 when RAF 206 write address counter is set to location 01.

Cache 1 now requests bus 5 to send the memory request to main memory 3 for 2 data words if main memory 3 is banked. Or if main memory 3 is interleaved 2 memory requests are sent by cache 1 for 4 data words from main memory 3.

Cache 1 requests access to bus 5 by forcing signal CYREQ+ the Q output of flop 511 high, Figure 5. In block 907 when bus 5 is not busy the 125 2 signal inputs to NAND 513, Figure 5, BSBUSY and CYREQ+ which in block 908 sets flop 515.

The Q output signal MYREQT remains high in block 909 until cache 1 has the highest priority of the system units requesting access to bus 5 then in block 9 10 the output of AND 542 goes low and sets flop 541. The Q output signal MYDCNN+ going high gates drivers 212, 214 and 218 to send out on bus 5 information in the format of Figure 8b. PRA, cache identification 0002, Function Code 00. indicating that this is the first request of main memory 3, 13SIVIREF low indicating that the address levels BSAD 05-22 contain a main memory 3 address and 13SD13PIhigh indicating that 2 data words are sent to main memory 3. Main memory 3 responds in block 912. If main memory 3 is busy and cannot accept the bus 5 cycle in block 913a flop 541 the MYXI\IN flop is reset, however, flop 515 remains set and signal MYREQT high requests another bus 5 cycle. When the response is an acknowledge and signal BSACKR goes high flops 515 and 541 are reset in block 913. Also flop 511 resets in the banked memory operation. Flop 504 sets in block 914 and the Q output logic signal BLOCKF+ goes high.

Figure 6 is a timing chart illustrating the relative sequencing of the interleaved memory operation. In the first memory request cycle timing signal CACHRQ 601 going high starts the cycle, causing FEMPTY-20 602 to go low. FEMPTY-20 going low forces BAWRiT 604 and BAORCK 605 low to strobe PRA into RAF 206 and AOR 207 respectively; and also advance the RAF 206 write address counter 234 by forcing AORCNT-30 609 low. If there is a directory---hitHIT 0-3 606 goes high in the middle of the cycle (dotted line) and the data word CADP 00-19 607 (dotted line) is sent to CPU2. CYCADN- 608 is sent to CPU2 and forces CACHFIQ 601 low (dotted line). If there is no-- -hit-MEIVIREQ 610 is set high by the rise of CLOCKO+ 603 which sets MYREQT 612 high. MYREQT 612 is turn sets MYXI\IN+ 613 high. The BSACKR 614 response resets MYXI\IN 613 which resets MYREQT 612. BSACKR 614 sets BLOCKF 611 high to start the second memory request.

Figure 7 is a timing chart illustrating the relative sequence of the banked memory I l 0 operation. The timing signals of the memory request cycle of Figure 7 are the same as the corresponding timing signals ofFigure 6. With BLOCKF high in block 915, signal BAWRIT strobes PRA+ 1 into RAF 206 location 115 0 1. Signal BAORCK strobes PRA+ 1 into AOR 207 and the write address counter 234 is advanced to location 02. P RA+ 1 is switched from the ADDER 211 output through 2:1 MUX 209 which is enabled by signal MEIVIREQ, Figure 2. 120 For the interleaved memory block 916 advances to block 917 whereas for the banked memory block 925 is processed next. For the interleaved memory blocks 917 through 920 is a repeat of blocks 907 through 910. In block 921 signal MYXI\IN+ is set and strobes drivers 212, 214 and 215, Figure 2, sending out on bus 5, PRA+ 1, Cache Identification 0002, Function 018 designating this as the second memory cycle, 13SIVIREF and 13SDI3PI- as before.

1 21 GB 2 056 135 A 21 This time the main memory 3 is busy and responds in block 922 with signal BSWAIT increments in block 923 the data counter by setting flop 508, Figure 5. Now in block 924, signals BSACKR and BSWAIT reset MYREQT, MYDCNN+ and CYREQ.

BLOCKF 611, Figure 6, starts the second memory request cycle by going high thereby' forcing BAWRIT 604 low to strobe PRA+ 1 into location 0 1 or RAF 206 and forcing BAORCK 605 75 low to strobe PRA+ 1 into AOR 207. Signal AORCNT-30 609 advances RAF 206 write address counter 234 to location 02.

MYREQT 612, MYMNN 613 and BSACKR 614 cycle as before. BSWAIT 615 resets MYREQT 612 and MTDCNN 613 and forces DATACK 616 low (dotted).

Both the Banked and interleaved operations now await the bus 5 cycle which sends the PRA data word from main memory 3 to cache 1 in 85 response to the first memory request.

When information is being transferred on bus 5, signal BSDCNN+ goes high in Block 925 forcing the output of NAND 332, Figure 3, the write enable signal FWRITE low. This signal transfers the information on bus 5 through receivers 213, 215 and 217, Figure 2, into FIFO 203.

For both interleaved and banked memories the flow diagram of Figure b makes a number of passes from block 926 through 950; that is one pass for each data word transfer from main memory 3 to cache 1 over bus 5 in response to the memory request.

The information received in block 926 by FIFO 100 203 must be in the format of Figure 8c if it is a response to the memory request. If it is not in that format then cache 1 performs a different sequence of operations.

Assuming the information received is in response to the memory request, then the PRA data word is received by cache 1 on the first bus 5 data cycle as is the cache identification 0002, function code 00. indicating that this is in response to the first memory request, BSDBPL high indicating that this is the first of the 2 data words in response to the first memory request, 13SMREF low indicating that the address field contains the cache identification and function code and BSSHBC high indicating that this bus cycle is in response to the memory request.

For the banked memory the PRA and PRA+ 1 data words are received in response to the memory request. 13SDI3PI- will be low for the PRA+ 1 data word. The function code will be 00. 120 for both the P RA and PRA+ 1 data words.

For the interleaved memory the PRA and PRA+2 data words will be sent from main memory 3 to cache 1 over bus 5 with a function code of 00, indicating this is the response to the first memory request, PRA+ 1 and PRA+3 will be sent with a function code of 01. indicating this as a response to the second memory cycle. 13SD13P1will high for PRA and PRA+ 1 and low for PRA+2 and PRA+3.

If the cache identification is 0002, then in block 927 signal MYCHAN is forced high as the output of AND 546, Figure 5, and sets flop 516 whose Q output MYACKR going high sends a signal back to main memory 3 acknowledging that the information was received in response to the memory request. The signal is received by main memory 3 as BSACKR.

If in block 926 the data word received by FIFO 203 is not in response to the memory request, then in block 927, signal MYCHAN does not go high and the decision block 927a exits to a series of decision blocks 927b, 927c and 927d which tests if the information in FIFO 203 is an acknowledged main memory 3 write operation. If it is a write BSWRIT is high, and if it is addressed to main memory 3, BSMREF is high and if main memory 3 acknowledged the receiving of the information BSACKR is high then in block 932a, the FIFO 203 Write Address Counter is incremented by + 1.

For the interleaved memory, decision block 929 tests the RAF 206 write address counter 234. If set at location 02 then in block 930 the ADDER 211 input control signal + 1, the output of EXCLUSIVE OR 237 Figure 2 is high and PRA+2 appears at the output of ADDER 211 and is strobed into RAF 206 location 02. The write address counter 234 is then advanced to location 03. If the write address counter 234 has been set to location 03 then the +2 control signal, the output of AND 236 is high and PRA+3 appears at the output of ADDER 211 and is strobed into RAF 206 location 03 after which the write address counter 234 advances to location 00.

Both banked and interleaved memory system in block 932 advance the FIFO 203 write address counter flops 320 and 321 Figure 3 by forcing signal PLUS 1 low. Advancing the write address counter flops forces the output signal FEMPTY+ of comparator 318 low. This signal is inverted and sets flops 313 so that the 5 output signal FEMPTY+20 goes low and starts CLOCKO+ cycling in block 933.

Decision block 934 now tests the function code low order bit BSAD23. If BSAD23 is low indicating this is the response to the first memory request then in block 935 the FCHZRO flop 413 Figure 4 sets and if BSAD23 is high the FCHONE flop 412 of block 936 sets. Flops 412 and 413 condition the read address multiplexer 233 outputs to select the address stored in RAF 206 with the proper PRA data word received from main memory 3 in response to the memory request. Decision block 937 tests signal BSDBPL which when low indicates the second word of a memory response and advances the block 933 data counter flops 508 and 509 Figure 5. 125 Decision block 939 tests for the end of the bus 5 cycle and when signal BSDCNN+ goes low, flop 516 Figure 5 sets in block 940 and the Q output signal MYACKR goes low. The first bus 5 information stored in FIFO 203 is read in block 941 and if the FIFO bit position GB 2 056 135 A 22 41 + is low in decision block 942 it indicates that this is update information. If the FIFO bit position 41 + is high indicating that this is a replacement operation then the read address multiplexer 233, Figure 2, selects the proper location in RAF 206 to read out the address corresponding to the data word in FIFO 203 into LR 204. On the CLOCKO+ rise flop 323, Figure 3, sets the Q output CYFIFO high which enables LR 204. This sets the output of the selected location of RAF 206 indicated by read address multiplexer 233 into the address flops of LR 204 and also sets the data output and control output of FIFO 203 into the respective flops of LR 204.

Decision block 945 tests the output of the read 80 address multiplexers 414 and 415, Figure 4, and if set to location 00, sets flop 529, Figure 5, in block 946 which results in signal CYCADN being sent to CPU2 as before. Also flop 305, Figure 3, is set and the Q output signal INTERG+ gates the data word from signal lines FIFO 1038 through the buffer bypass drivers 206, Figure 2, to CPU2 as CADPOO-1 9. CPU2 then resets signal CACHRO, which resets flop 301, Figure 3, which resets flop 305. If this is not the first data word cycle then the read address multiplexers 233 are not set to location 00 and in block 947 a directory 202 search is made. If the data word is already in the data buffer 201 then no further action is taken on the data word. If the data word is not in data buffer 201 then in block 948, the round robin logic unit 224 selects the WRITE signal of the next level of that column address into which the data word is to be written. In block 949 the data word is written into the data buffer 100 201, the row address is written into the directory 202 and the old level of round robin 224 is incremented by+ 1 the address location selected by the column address.

In decision block 950 the data counter flop 509 Figure 5 if set resets the flops indicated in block 951 and the operation is concluded. If flop 509 is not set then the operation returns to block 925 to await the next data word from main memory 3 in response to the memory request.

Again returning to Figure 6 for the PRA cycle, that is the cycle in which the first data word is sent from main memory 3 to cache 1 over bus 5 signal BSDCNN+ 618 goes high indicating that there is a bus 5 cycle starting and forces the FIFO 203 write enable signal FWRITE 619 low. This loads FIFO 203 from receivers 213, 215 and 217 with the information from bus 5. If the information is in response to the memory request then signal MYACKR 620 goes high acknowledging the bus 5 transfer and advancing the FIFO 203 write address counter by forcing FPLUS 1 621 low. Advancing the counter indicates that FIFO 203 has information stored in it. This forces FEMPTY+ 20 621 low which starts 125 CLOCKO+ 603 cycling. The data word output of FIFO 203 is sent through the buffer bypass drivers 205 during the time indicates by INTERG 625 as CADPOO-1 9 607. Signal CYCADN- 608 strobes the data word CADPOO-1 9 607 into 130 CPU2 and resets CACHRQ 601.

Signal ADDRSO+ switches 2:1 MUX 208 so that when signal CYFIFO 627 comes high and strobes the outputs of RAF 206 and FIFO 203 into LR 204, the output of LR 204 can start the directory search by transferring the address signals ADDROO-1 7+ through the switch. Signal REPLACE comes high to switch 2:1 MUX 223 to receive the selected WRITE 629 signal for the directory 202 and data buffer 201 replacement write operation. Signal CYREAD 628 low gates the selected signal WRITE 0-3 629.

Local Register 632 shows information transferring into LR 204 when signal CYFIFO goes high.

Signal BUMPUP 630 advances the read address counter of FIFO 203 by going low. LR 632 is already loaded with the FIFO 203 at this time. The RAF read address multiplexer 631 when high, gates the output of the location indicated by the ADDRWD+013 and ADDRWD+OA signals to LR 204. BAWRIT 604 loads PRA+2 into location 02 and PRA+3 into location 03 on successive MYACKR 620 pulses. AORCNT-30 609 advances the write address counter after each loading of PRA+2 and PRA+3 into RAF 206.

In the PRA+2, PRA+ 1 and PRA+3 cycles if the data word is stored in data buffer 201 then HIT 0-3 606 will go high (dotted) for that data word, suppressing the fall of CYREAD 628 which in term suppresses the WRITE 0-3 629 pulse. The data word will therefore not be written into the data buffer 20 1.

As previously stated if the response to the second memory request was the BSWAIT signal then the request is not repeated. Since 2 data words instead of 4 data words will be sent from main memory 3 to cache 1 over bus 5 the data counter is incremented when signal DATACK 616 pulses (dotted) in the second memory request cycle. Then in the PRA+2 cycle when the second data word is sent over bus 5 to cache 1, the signal DATACK 616 again pulses which sets DATCTI high (dotted). This resets MEMREQ 610 (dotted) which resets BLOCKF 611 (dotted) and DATCTI 617 and the prefetch operation is completed.

Normally signal DATACK is pulsed by the second data word and the fourth data word (BSDBPL high) and the operation completed after the fourth data word cycle when signal DATCT1 617 comes high and resets MEIVIREQ 610 which resets BLOCKF 611 and DATCTI 617.

Now returning to Figure 7 illustrating the timing of the banked main memory 3 and cache 1 operation, in many respects the timing signals of Figure 6 illustrating the interleaved operation is similar to their respective timing signals in Figure 7. The basic difference is that Figure 7 illustrates the banked timing which requires 2 data cycles, the PRA and PRA+ 1 data cycles compared to Figure 6 which illustrates the interleaved timing which requires 4 data cycles, PRA, PRA+ 1, PRA+2 and PRA+3. Therefore, many of the Figure 6 timings show 4 cycles as compared to the Figure 7 timings which show 2 cycles of 1.

23 GB 2 056 135 A 23 operation. Also, since the data counter is forced to 65 + 1 in the banked operation only 1 DATACK 716 pulse is needed to set DATCT1 717 which resets MEMREQ 716 pulse is needed to set DATCTI 717 which resets MEIVIREO, 7 10 which in turn, resets BLOCKF 711 and DATCTI 717 as before.

Description of Operation - Update

In block 925 logic signal BSDCNN goes high indicating a bus 5 cycle is started. In Figure 3, logic signal BSDCNN going high generates the FWRITE strobe as the output of NAND 332. This loads FIFO 203 with the bus 5 information, Block 926, in this case, receives the bus 5 information and tests in decision block 927a if MYCHAN is high. That is, if the cache identification 0002, was received with BSMREF high. In the update, in Figure 5, the output of AND 515, logic signal MYCHAN is low therefore testing blocks 927b-d. In the update mode the 3 inputs to NAND 337, Figure 3, logic signals BSACKR, BSMREF and BSWRIT are high forcing the block 932a, logic signal FPLUS 1 low advancing FIFO 203 Write Address Counter flops 320 and 321 to the next location. In block 941, FIFO 203 bit position FIFO 41 + is read and in decision block 942 FIFO 41 + is low indicating an 90 update operation in block 952.

Logic signal CYFIFO, the Q output of flop 323, Figure 3, is set high when the write address counter flops 320 and 321 advance to the next location forcing the FEMPTY+ output of comparator 3 18 low. This sets flop 313 and starts CLOCKO+ cycling. CYFIFO going high transfers, in Figure 2, the output of FIFO 203 to LR 204 and advances the FIFO 203 read address flops 316 and 317 by forcing the logic signal BUMP UP low. 100 The 18 bit address signals FIFO 00-17+ transfers through 2:1 MUX 208 to start a directory 202 search. Also, F/F 41 of LR 204, Figure 3, resets and the U output UPDATE goes high. Column Address ADDR 08-17-10 reads 105 out 4 locations, one in each level, to the 4 comparator 221 a-d inputs. These outputs ADDR 00-07-20,-21,-22 and 023 are compared with row address ADDR 00-07-10.

In block 955, if there is no hit, that is, all 4 110 outputs HIT 0-3+ remain low, no further action is taken on the data. If there is a hit, that is, one of the 4 outputs HIT 0-3+ goes high, then in block 956, flop 330, Figure 3, sets and the ?i output CYREAD goes low thereby enabling the selected WRITE 0-3 write lines. REPLACE, the 2:1 MUX 223 switch signal is low allowing the selected HIT 0-3+ logic signal to force the corresponding WRITE 0-3 logic signal lines high provided the 2:1 MUX 223 enabling signal CYREAD is low. If a byte is to be updated logic signals BYTE MOD and FIFO 18+ or FIFO 18- select the data buffer 264 or 266 for updating. If logic signal BYTE MOD is low then the data word in the column address location ADDR 08-17-10 in data buffers 264 and 265 are updated and the operation is completed.

The timing diagram, Figure 10, illustrates the update cycle. Logic signal BSDCNN+70 high indicates the start of the bus 5 cycle. This forces FIFO 203 strobe FWRITE 72 low, loading FIFO 203 from the receivers 213, 215 and 217. When BSMREF 7 1, BSWRITE 72 and BSACKR are all high, logic signal F PLUS 1 advances the FIFO 203 write address counter forcing FEMPTY+20 76 low. This starts CLOCKO+77 which forces CYFIFO 70 high transferring information from FIFO 203 to LR 204. The directory 202 search is made and if there is a hit, one of the HIT 0-3 78 signals going high forces CYREAD 81 low enabling the data buffer 201 and directory 202 write. If no HIT 0-3 78 signal goes high indicating that the information is not in data buffer 201 then, CYREAD 81 remains high, suppressing the last (dotted) CLOCKO+77 cycle and preventing a write cycle. The FIFO 203 Read Address Counter is advanced by logic signal BUMPUP going low. If there is no additional information in FIFO 203 logic signal FEMPTY+20 76 goes high.

If there was a hit the rise of CLOCKO+77 at point B concludes the cycle. If there was no hit then the rise at Point A concludes the operation.

Round Robin 224- Figure 14 Logic signal CYWRIT connects between FIFO R/W Control 230, the inputs to delay lines 603 and 605 and the CLK inputs of flops 610 and 611. The output of delay line 603 connects to the input of an AND 604. The output of delay line 605 connects to an input of an inverter 614 whose output connects to the other input of AND 604. The output of AND 604 connects to inputs of an inverter 606 and a NAND 607. The output of inverter 606, logic signal W13TPL5- connects to the ENABLE terminal of 2:1 MUX 223. Logic signal REPLACE connects between LR 204, the other input of NAND 607 and the SELECT terminal of 2:1 MUX 223. The outputs of AND 613a-cl, logic signals LEVELO-3+ connect to the---1 - input terminals of 2:1 MUX 223. The output of NAND 607, logic signal RNDWRTconnects to the Write Enable terminals of Random Access Memory RAM 601 and 602, the Read Enable terminals are connected to ground.

Signal lines ADDR 08-17+ connect between 2:1 MUX 208 and the ADDRESS select terminals of RAM 601 and 602. Logic signal RNDADD+ connects between NOR/AND 612 and the data input of RAM 601 whose data output Rounc10+0A connects to the D input of a flop 610. Logic signals BAOR 11 + 10 and BAOR 12+10 connect between AOR 207 and inputs to a NOR 608 whose output logic signal ROUNDR- connects to the D input of a flop 609. Logic signal CYFIFO connects between FIFO R/W control 230 and the CLK input of flop 609. The 5 output of logic signal ROUNDO-OR connects to the CLR inputs of flops 610 and 611. Logic signal CY01-TO+ connects between cycle control 232 and the CLR input of flop 609.

The Q output of flop 610, logic signal ROUNDO+ connects to inputs of NOR1/AND 612, 24 GB 2 056 135 A 24 AND 613c and AND 613d. The Q output, logic signal ROUNDO- connects to the inputs of NOR2/AND612,AND613aandAND613b.The Q output of flop 611, logic signal ROUND1 +, connects to inputs of NOR 1/AND 612, AND 613b and AND 613d. The U output, logic signal ROUND 1 -, connects to inputs of NOR2/AND 612, AND 613a, AND 613c and the data input of RAM 602. The data output of RAM 602 logic signal ROUND1 +OA connects to the D input of flop 611.

Signal lines HITO-3+ connect between the COMPARE 221 a-d outputs and the 0 terminal of 2:1 MUX 223. Signal lines WRITEO-3 connect between the 2 terminal of 2:1 MUX 223 and data buffer 201 and directory 202.

Round robin 224 selects the next level of data buffer 201 and directory 202, Figure 2, into which new information is written. Round robin 224 points to the oldest information for that column address ADDR 08-17. That is the information for replacement.

The two 1 bit by 1024 RAM 601 and 602 are set to level 0 for each column address; that is, the 1024 addresses in RAM 601 and the 1024 addresses in RAM 602 are set to 0 during the QLT mod e.

Initially, logic signal CYO.LTO+, the CLR input to flop 609 is high. Both inputs to NOR 608, logic signals BAOR 11 + 10 and BAOR 12+10 are low forcing the output logic signal ROUNDR- high. When logic signal CYFIFO goes high flop 609 sets and the U output, logic signal ROUNDO-OR goes low preventing flop 610 and 611 from setting.

Logic signals ROUNDO- and ROUND1 - are high forcing the output of AND 613a, logic signal LEVELO+ high.

The 2 inputs to NOR2/AND 612, logic signals ROUNDO- and ROUND 1 - are high forcing the output logic signal RNDADD+ low. The data input 105 to RAM 601 therefore is low. Since the U output of flop 611, logic signal ROUND 1 is high, the data input to RAM 602 is high.

During the QLT mode, the first 4096 data words in main memory 3 are written into the data 110 buffer 201 and their respective row addresses ADDR 00-07-10 are written into directory 202. The first 1024 data words with their row addresses are written into level 0, the second 1024 data words with their row addresses are written into level 1, the third 1024 data words with their row addresses are written into level 2 and the last 1024 data words with their row addresses are written into level 3. The levels are selected by the round robin RAM 601 and 602.

For each of the first 1024 write cycles, logic signal CYWRIT the input to delay lines 603 and 605 goes high. 20 ns. later the output of delay lines 603 goes high. Both inputs to AND 604 are high and the output logic signal WRITPLS+ is high. REPLACE is high in the 0LT mode. This forces the output of NAND 607, logic signal 13NDWRT- low enabling the write function of RAM 601 and 602. The output of inverter 606, logic signal W13TPI-S- goes low enabling 2:1 MUX 223. 50 ns. later the output of delay line 605 goes high forcing the output of inverter 614 low. This forces the output of AND 604 low forcing the output of inverter 606, logic signal WRTPLS- high. Logic signal FINDWRT-, the output of NAND 607 goes high terminating the write enable pulse.

All zeros are forced into the 1024 successive addresses of RAM 601 and all ones are forced into the 1024 successive addresses (0-1023) of RAM 602.

When address 1024 (2000j is stored in AOR 207, BAOR 12+10 is high forcing the output of NOR 608, logic signal ROUDNR- low. When logic signal CYFIFO goes high, flop 609 resets and the U output logic signal ROUNDO-OR goes high. Flops 610 and 611 are now activated. ADDR 08-18+ selects address 0000. of RAM 601 and 602. The data output, logic signal ROUNDO+OA is low and logic signal ROUND 'I +OA is high. When logic signal CYWRIT goes high flop 611 sets and the Q output logic signal ROUND1 + is high. Logic signals ROUND 1 + high and ROUNDO- high select the output of AND 613b, logic signal LEVEL 1 +. Also, the output of NOR/AND 612 is forced high writing a - 1 - in RAM 601 and a "0" in RAM 602 at address 000..

This sequence continues until 1024 level 1 locations in data buffer 201 and directory 202 are filled and RAM 601 stores all -1's- and RAM 602 stores all "O's".

Logic signal BAOR 11 + 10 is high for the transfer of data words in addresses 2048 to 4096 keeping flop 609 reset. Flop 610 is set and flop 611 is reset for the 3rd 1024 data words with their row addresses to be written into data buffer 201 and directory 202. In this case, the output of AND 613c, logic signal LEVEL 2+ is high. During this 3rd sequence '1'sare written into all addresses of RAM 601 and 602.

During the 4th sequence flops 610 and 611 are set selecting the output of AND 613d, logic signal LEVEL 3+ high. This results in all O's being written into RAM 601 and 602. During the sequence when the 4096th data word is transferred from main memory 3 and written into cache 1, logic signal CY0LTO+ goes low resetting 3 flop 609 thereby enabling flips 610 and 611 for subsequent replacement operation.

Flop 609 is a 74S74 logic circuit described on page 5-22. Flops 610 and 611 are 74S 175 logic circuits described on page 5-56 and NOR/AND 612 is a 74LS51 logic circuit described on page 5-16. The above are described in the aforementioned TTL Data Book.

Description of Operation

Figure 16 is a flow diagram illustrating the Quality logic test (O.LT) mode. As a result of system initialization, a negative going CLEAR- signal is sent over bus 6 to cache 1. As a consequence of receiving the CLEARsignal, the contents of the first 4096 address locations in main memory 3 are stored in the 4 levels of data buffer 20 1, Figure 2. The directory 202 is loaded 1 GB 2 056 135 A 25 with the respective row addresses of the first 4096 address locations and the round robins RAMs are set to point to Level 0 as the first level in data buffer 201 and directory 202 to be 5 replaced.

Figure 15 is a timing diagram of the QU operation and will be used with Figure 16 in the description of the overall operation.

START 901 designates a bus 5 transfer cycle.

Cache 1 receives all bus 5 transfers for possible updating or replacement.

In the QLT operation logic signal CLEAR- is received by cache 1 over bus 5. This is indicated by START 900.

The decision block 901 selects the QLT mode 902 and in block 903, flop 57 1, Figure 5, sets on the rise of logic signal CLEAR- and the Q output logic signal CYGI-TO+ goes high. This forces the output of NOR 561 low and logic signal CY0LTO- 1A, the output of inverter 567 is forced high. Logic signal CYGU0+013, the output of delay line 562 remains high for 160 ns. In Figure 4 the output of NAND 443 goes low forcing the output of NOR 419, logic signal AORMT, high.

In block 904 the output of ADDER 211, Figure 2, signal lines AORO 05-22+ are at 000000 The output of NAND 241 is high switching 2:1 MUX 209 to allow signal lines AORO 05-22+ through. an input AOR 207.

Logic signal AORMT, Figure 4, forces logic signals BAWRIT, the output of NAND 416 low, and BAORCK, the output of NAND 424 low writing the PRA 000000. into AOR 207, Figure 2, and location 00 into RAF 206. 70 ns. later logic signal AORCNT-30 the output of inverter 423, goes low advancing the RAF write address counter 234 to location 01.

ns. after logic signal MILTO+ rises, logic signal MILT0+00, the output of NOR 565, Figure 5, goes low setting flop 503. This forces the Q output MEIVIREQ+ high, block 905, setting flop 511. This forces the Q output, logic signal CYCREQ+ high in block 906, requesting a bus 5 cycle in block 907. 45 In Figure 15, timing signal CLEAR- 701 goes 110 high at 0 ns. of the first bus 5 cycle request forcing MLTO+ 702 high. This results in BAWRIT 710 and BAORCK 711 going low strobing 000000, into AOR 207 and RAF 206. 50 AORCNT-30 713 advances the RAF write address counter 234 to location 01. 160 ns. after the rise of CYQ1-TO+ 702, CYQLTO+OD 703 fails forcing MEIVIREQ+ 704 high which forces CYCREQ+ 705 high. 55 In decision block 907a logic signal BSBUSY-, 120 the input to NAND 513, Figure 5, goes high. Since logic signal CYCREQ+ is high, flop 513 sets and the Q output MYREQT goes high in block 907b. In block 907c, if there is no higher priority request on bus 5 then the output of NAND 542 goes low setting flop 541. The Q output logic signal MYMNN+ going high, block 907d enables drivers 212, 214 and 218 which sends out on bus in block 907c the output of AOR 207, 0000008, the cache 1 identification and function code, 130 BSDBPL and BSMREF.

The response from main memory 3 in decision block 907f 13SACKR, acknowledging the information sent from cache 1 is sent back over bus 5. Signal BSACKR is applied to the input of NOR 543, Figure 5 thereby forcing the output low. This results in flop 541 resetting, flop 514 setting and flop 515 resetting. This is shown in block 907, Figure 9. The Q outputs MYMNN+ and MYREQT are now low and in block 907k, the Bus cycle Request is concluded.

If the main memory 3 response was BSWAIT in decision block 907f then in decision block 907g the output of NOR 543, Figure 5 goes low, resetting flop 541 and the Q output, logical signal MYMNN+ goes low. In blocks 907h and 907j the output of NOR 572, Figure 5, is high forcing the output of AND 512 high keeping flop 515 set with the Q output logic signal MYREQT high, requesting another bus 5 cycle.

P RA+ 1 address (000000,) now appears at the output of ADDER 211, Figure 3, in block 908.

The BSACKR response to the first bus 5 cycle request sets flop 504, Figure 5, and the Q output BLOCKF+ is high. Since the write address counter 234 is set to location 0 1, the output of NOR 417, Figure 4, goes low forcing the output of NOR 419, logic signal AORMT high. This loads in block 909 00000 1. into AOR 707 and location 0 1 of RAF 206. When logic signal AORCNT-30 goes low the RAF write address counter advances to location 02.

In Figure 15, MYREOT 706 goes high forcing MYMNN+ 707 high when the bus 5 is available, MYMNN- strobes the cache 1 information onto bus 5 and when main memory 3 receives the information it sends back BSACKR 708 which resets MYXI\IN+ 707 and sets BLOCKF 709. MYMNN+ going low causes MYREQT 706 to reset. When the bus 5 is no longer busy MYREQT 706 goes high requesting another bus 5 cycle. When Block F 709 goes high to start the 2nd bus 5 cycle request BAWRIT 710 and BAORCK 711 strobe the addressappearing at the output of ADDER 211, Figure 2, into AOR 207 and RAF 206. AORCNT-30 713 then advances the RAF write address counter 234 to location 02.

Since CYCREQ+ 705 is still high in the 2nd bus 5 cycle request MYREQT 706 again goes high requesting the bus 5 cycle.

Block 907-1, Figure 16 sheet 2, requests the 2nd bus 5 cycle and blocks 907-jas repeated to send the next address in sequence out on bus 5 with the cache identification 0002, the function code, 13SDI3P1- and BSIVIREF.

In Figure 15, MYREQT 706 high starts the 2nd bus 5 cycle request by forcing MYDMN+ 707 high which resets CYCREQ+ 705 and strobes in the information out on bus 5 as before. When main memory 3 receives the information, BSACKR 708 is sent to cache 1 over bus 5 and resets MYIDMN+707 which results in MYREQT 706 resetting.

In block 910, cache 1 waits for the first data word from mainmemory 3. In block 900, 26 GB 2 056 135 A 26 information is on bus 5. In decision block 901 CLEAR is not set selecting decision block 911 where BSDCNN+ is high indicating that information on bus 5 is to be written into FIFO 5 203 in block 912. In block 912a logic signal FWRITE, the output of NAND 332, Figure 3, forces the write enable terminal of FIFO 203 low and in Figure 2 the output of receivers 213, 215 and 217 are strobed into FIFO 203. As shown in block 912b FIFO 203 is loaded with the data word in response to the first bus 5 cycle request whereby PRA 000000, was sent to main memory 3. Also loaded into FIFO 203 are the octal Cache I.D. (0002,) and the function code (00,) signals, as well as logic signals BSDBPL high, ESMREF low and BSSHBC high.

Decision block 91 2c tests the cache identification code for 0002, and that BSMREF is low. In that case in Figure 5 the output of AND 546, logic signal MYCHAN goes high starting the second half bus cycle of block 913.

In block 913a with logic signal MYC14AN high, the CLK input of flop 516, logic signal E1SDCND+ goes high, flop 516 sets and the Q output, logic signal MYACKR goes high and acknowledges to main memory 3 that the information was received.

In block 913b the output of NAND 322, Figure 3, logic signal FPLUS 1 sets the FIFO 203 write address counter flop 320 thereby advancing the counter. This forces the output of comparator 318 low resulting in f lop 313 setting. The G output logic signal FEMPTY+20 going low starts timing signal CLOCKO+ the output of NOR 311 to cycle in block 913c.

Since the function code is 00., BSAD23 is low in decision block 913d, then in block 913f the FCHZRO, flop 413, Figure 4, sets and a "I" is forced into FIFO 203 bit position 42.

Decision block 913g tests for BSDBPLhigh. In 105 the OLT mode BSDBPL is low and flop 574, Figure 5, remains reset and the ?i output logic signal BSDBPL- is high forcing the output of NAND 506 low setting the output of NOF1 507, logic signal DATACK- low setting the data counterflop 508 in block 913h.

Decision block 913i is tested forflop 509, Figure 5, set. In this case flop 509 is not set and the output of NAND 510 remains high. In decision block 913j, logic signal BSDCNN+ is tested and ns. after it goes low in block 913k, flop 516 resets and the Q output logic signal MYACKR falls and cache 1 goes into an idle cycle waiting in start block 900.

The second data word in response to the 2nd Bus Cycle Request 907-1 is transferred to cache 1. When BSDCNN+ is high FIFO write block 912-1 is activated since the data word is from an odd address location in main memory 3.

The FIFO write sequence described above is repeated through blocks 91 2a-c to second half bus cycle block 913-1. The second half bus cycle sequence of blocks 913a-g is repeated. In block 913h data counter flop 509, Figure 5, is set and the Q output logic signal CYFIFO and DATCTI high in decision block 913i forces the output of NAND 510 low resetting flop 503 in block 913n and the Q output logic signal MEREQ+ falls.

The MYACKR flop 516 in block 913m is reset when in decision block 913 1, logic signal BSDCNN+ goes low. In block 913n, logic signal MEMREQ+ going low resets flops 508, 509, 504, Figure 5 and 413, Figure 4. This forces logic signals DATCTO, DATCTI, BLOCKF+ and FCHZRO low in block 913o.

Cache 1 returns to START 900 for the first FIFO 203 read cycle.

In Figure 15, BSDCNN+ 714 is high to start the FIFO write cycle in which the first data word from the even address location in main memory 3 is transferred to cache 1. FWRITE 715 strobes the bus 5 information into FIFO 203. MYACKR 716 is forced high when FIFO 203 contains the Cache I.D. 0002, and BSIVIREF is low. MYACKR 716 high advances the FIFO write address counter by forcing F PLUS 1 717 low. FIFO 203 is now not empty and FEMPTY+20 goes low starting CLOCKO+ 719 to cycle to start the first FIFO 203 read cycle.

During the first word to cache cycle BSDBPL low forced the data counter clock pulse DATACK 728 low. During the 2nd FIFO write cycle BSDBPI, is again low and DATACK 728 is again forced low forcing DATCTI 729 high. This resets MEMREQ+ 704 which resets BLOCK F 709 and DATCTI 729.

In block 913b of the second half bus cycle, the FIFO write address counter is incremented. This sets the output of comparator 318, Figure 3, logic signal FEMPTY+ low, indicating in decision block 916 that FIFO 203 is not empty, starting the clock cycling by setting flop 313 in block 913c and starting a FIFO read operation in block 914.

The FIFO read address counter flops 316 and 317 select in block 914a the FIFO address from which information is transferred from FIFO 203 to LR 204.

Since the output of decision block 914b is high, that is the bit position 41 of FIFO 203 is high, the replacement block 915 is selected. The update block 914c is not active in the OLT operation.

RAF 206 stores the address for the data word stored in the selected FIFO 203 address location. In block 91 5a the RAF read address multiplexer 4:1 MUX414 and 415, Figure 4, select location 00. Logic signal CYQLTO- is low forcing the output of NOR 440 high forcing select terminal 2 of 4:1 MUX 414 and 415 high. Since bit position 18 of FIFO 203 is low, select terminal 1 of 4:1 MUX 404 and 415 are low; therefore input terminal 2 is enabled. 4:1 MUX 414 input terminal 2 is low as is input terminal 2 of 4:1 MUX 415.

In block 91 5b, the address from location 00 of RAF 206 and the data word and controls from FIFO 203 are transferred to LR 204 on the rise of logic signal CYFIFO. The output of AND 324, Figure 3, is high and on the rise of timing signal CLOCKO+ flop 323 sets and the Q output, logic signal CYFIFO goes high loading LR 204.

ii b 27 GB 2 056 135 A 27 Decision block 91 5c tests BAOR1 1 and BAOR1 2. If both are low indicating that the first 1024 data words are being transferred then in block 91 5d the Round Robin Register is held reset selecting level 0 of the data buffer 201 and directory 2 02. In Figure 14 the output of NOR 608 logic signal ROUNDR- is high. When logic signal CYFIFO goes high flop 609 sets and the 5 output, logic signal ROUND-OR goes low holding flops 610 and 611 reset. In block 91 5e therefore the Q outputs logic signals ROUNDO- and ROUND1 - are high forcing the output of AND 613a logic signal LEVEL 0+ high.- In block 91 5h at the selected column address, the data word is written into the data buffer 201, the row address is written into the directory 202 and the round robin RAM's are incremented + 1. The output of NOR 340, Figure 3, is high forcing the output of NOR 325 low when logic signal CYFIFO is high, forcing the output of NOR 327 high. This sets flop 330 and the Q output CYWRIT goes high. In Figure 14 logic signal CYWRIT high develops a 30 ns. negative going pulse delayed 20 ns. to the enable input of 2:1 MUX 223. This forces logic signal WRITEO high, writing the data word into level 0 of data buffer 201 and writing the row address into directory 202 at the selected column address. The output of NAND 607 goes low enabling the write input of RAM 601 and 602 forcing a " 1 " in RAM 602 and a "0" in RAM 601 at the selected column address ADDR 08-17+ since logic signal ROUND 1 - is high and RNDADD+ is low.

In decision block 91 5c, address locations between 1024 and 4095 have bit positions BAOR 11 + 10 and/or BAOR 12+10, the output of AOR 207, Figure 2, high. In block 91 5f normal round robin 224 operation takes place, i.e., in Figure 14, the output of RAM 601 and 602 at the column address location ADDR 08-17+ is loaded into flops 610 and 611 at the rise of logic signal CYWRIT. The outputs of flops 610 and 611 are decoded by AND 613a-d in block 91 5g to select the level in directory 202 and data buffer 201 into which the data word is written. This was 110 described supra.

The FIFO Read timing is shown in Figure 15 by F PLUS 1 717 advancing the FIFO 203 write address counter flops 320 and 32 1, Figure 3. This results in flop 313 setting the U output FEMPTY+20 718 going low starting CLOCKO+ 719, loading the data word and control bits from FIFO 203 and the address location from RAF 206 in LR 204. LR 726 shows the timing.

CYREAD 721 and CYWRITE 722, the d and Q outputs respectively of flop 330, Figure 3, switch on the rise of CLOCKO+ 719 when CYFIFO 720 is high; REPLACE 723 is high since FIFO bit position 41 is high for the QLT operation. REPLACE 723 comes high at the rise of CYFIFO 720 and 125 remains high for the 4096 data word QLT transfer.

WRITE 0-3 727 is generated in round robin 224, Figure 14. Logic signal CYWRIT outputs AND 604 as a positive going pulse 30 ns. wide, 130 delayed 20 ns. which is inverted by inverter 606 and enables 2:1 MUX 223. Since the select input logic signal REPLACE is high, the 1 input terminal is activated. The rise of logic signal CYWRIT sets the selected output of RAM's 601 and 602 into flops 610 and 611 forcing one of the outputs of AND 613a-d, logic signals LEVEL 0-3+, high. This selected signal inputs terminal 1 of 2:1 MUX 223 and exits terminal 2, is inverted by inverter 255, Figure 2 and enables the writing into data buffer 201 and directory 202 as the negative going 30 ns. wide pulse WRITE 0-3-.

The FIFO read address counter is advanced by BUMP UP 724 which causes FEMPTY+20 718 to go high and stop CLOCKO+ 719 from cycling. However, the odd word is being received by cache 1 from main memory 3 so that F PLUS 1 717 again advances the FIFO write address counter, forcing FEMPTY+20 718 low keeping CLOCKO+ 719 cycling to store the odd word in the data buffer 201, and its row address in the directory 202. After the odd word is stored FEMPTY+20 718 stays high and CLOCKO+ 720 remains high at the completion of the cycle which stores the data word from the odd address location into cache 1 In Figure 16, decision block 9151 is tested for the 4096th word. If the last word was not received then in block 91 5j the address at the ADDER 211 output, Figuire 2 is incremented + 1 and the RAF write address counter 234 is advanced.

Decision block 915k is tested. If the data word received into FIFO 203 is from an even address location in main memory 3 then cache 1 returns to START 900 to await the next word from main memory 3 from the odd address location. If the data word received into FIFO 203 is from an odd address location in main memory 3 then in block 9151 the next address is loaded into AOR 207 and RAF 206 and the write address counter 234 is advanced. Note that in block 91 5j the WAC 234 is advanced an extra count for each data word transferred. This is so the WAC 234 stores the even address location in location 00 of RAF 206 and the odd address location in location 01 of RAF 206. Locatiors 02 and 03 are not used.

In block 91 5m flop 503, Figure 5, is set as follows. The output of AND 567 is high, since input signals CYWRIT, REPLACE and FIFO 17+20 are high. This forces the output of NOR 569, logic signal MEMREQ+OC low forcing the output of NOR 502 high setting flop 503 on the next rise of timing signal CLOCKO+. The Q output logic signal MEMREQ+ going high starts a memory request cycle by returning to block 906 where the cycle request flop 5 11 is set and the Q output, logic signal CYCREQ+ goes high.

In Figure 15, MEMREQ+ 704 goes high at the end of the cycle in which the data word from the odd address location in main memory 3 is written into cache 1. This occurs when CYWRITE 722 is high on the last rise of CLOCKO+ 719.

Cache 1 continues to cycle, first requesting 2 data words from main memory 3, then writing 28 GB 2 056 135 A 28 those data words in data buffer 201 and the row address in directory 202 until in decision block 915i, the 4096th word is received into LR 204, Figure 2. In that case BAOR 10+ 10, one input to NAND 570, Figure 5, is high. When the output of AND 567 goes high during the cycle in which the data word from the odd address location is written into cache, the output of NAND 570 goes low resetting flop 57 1. In block 915n this forces the Q output, logic signal CYQ1-TO+ low concluding the QU operation. BAOR 10+ 10 high forces the output of inverter 468, logic signal QLTDUN- low forcing the output of NOR 569, logic signal MEMREQ+OC high. This forces the output of NOR 502 low. With the D input low, flop 503 resets on the next rise of - 80 timing signal CLOCKO+ and the Q output logic signal MEMREQ+ goes low preventing further requests of main memory 3.

In Figure 15, QUDUN 712 goes high during the last bus 5 cycle request forcing MEIVIREQ+ 704 low at the next rise of CLOCKO+ 719.

CYQ1-TO+ 702 goes low during the next cycle when CYWRITE 722 is high, the data word from the ODD address location is in LR 726 at the last rise of CLOCKO+ 719.

Claims (10)

1. Claims 1. A data processing system comprising: a system bus; 30 an

   addressable main memory coupled to said bus, said main memory including a plurality of sets of word locations, each set of word locations being defined by a column address, and each word location-within a set being identified by a row address, said main memory receiving an address word comprising said row address and said column address from said bus for reading a data word onto the bus, or for writing a data word received from the bus; a cache coupled to said system bus including:

   a data buffer having a plurality of word locations arranged in a plurality of sets of word locations defined by column addresses for storing data words received from the bus; and a directory including a plurality of word 110 locations corresponding in number to the number of sets in the data buffer and being addressable by column address, each word location of the directory storing a row address of a corresponding one of said words of the set stored in the data buffer, each column of the data buffer and the directory defined by a column address having a plurality of levels; said cache further including round robin circuit means coupled to the directory and the data buffer which generates signals to indicate a next of said levels into which replacement information is to be written, said round robin circuit means including:

   a plurality of RAM (random access memory) circuits which store n bits of information for each n th power of 2 number of levels in each of the column addresses of the RAM circuits, said bits of inlormation being coded to indicate the next level of the column address into which replacement information is to be written, said circuits include output circuit means for receiving signals from said RAM circuits during a replacement operation; an encoder coupled to said output circuit means, said RAM circuits being responsive to the column address to provide stored bits of information to the encoder, the latter providing loading signals having a value determined by the output circuit means for writing the replacement information into the next level of the column address of the directory and the data buffer on a first in/first out basis; and a counter coupled to the encoder and to the RAM circuits which increments by one said encoder output and store an incremented count in said column address of the RAM circuits for enabling the storing of information corresponding to said replacement information in the location of the data buffer identical of that stored in main memory during the replacement operation.
2. 2. A system according to Claim 1, wherein the cache further includes address register means, and means for coupling the RAM circuits to the output circuit means, said address register means generating a sequence of successive address signals during an initialization operation, said coupling means being responsive to selected ones of the address signals for initially setting the RAM circuits to predetermined values.
3. 3. A system according to Claim 2, wherein the output circuit means include a plurality of bistable circuits, the latter being switched to a reset state in response to selected ones of the address signals during a sequential transfer of information for filling a first one of said levels of the directory and the data buffer and the bistable circuits being operative to generate output signals for loading the column address locations of the RAM circuits with bits of information coded for indicating a second one of said levels of the directory and the data buffer into which the replacement information is to be written.
4. 4. A system according to Claim 3, wherein the bistable circuits are operative in response to said address signals during the sequential transfer of information to generate output signals to fill said second level and subsequent levels of the directory and the data buffer.
5. 5. A system according to any preceding claim, wherein the number of levels in the directory and the data buffer is four thereby making n equal to two and wherein the RAM circuit stores two bits of information of each of the column addresses.
6. 6. A cache unit comprising:

   a data buffer having a plurality of locations arranged in a plurality, of sets of locations defined by column addresses, each location storing data a directory including a plurality of locations corresponding in number to the number of sets in said data buffer and being addressable by said column addresses, each location of said directory storing an address of a corresponding one of the locations of the sets stored in the data buffer, 4 29 GB 2 056 135 A 29 each column of the data buffer and the directory defined by a column address having a plurality of 35 levels; round robin circuit means coupled to the directory and the data buffer which generates signals to indicate a next of said levels into which replacement information is to be written, said round robin circuit means including:

   a plurality of RAM (random access memory) circuits which store a number of bits of information for designating the number of levels associated with each of the column addresses of said circuits, said number of bits of information being coded to indicate a next level of said column address into which replacement information is to be written, said circuits including output circuit means for read out of signals from.50 said memory circuits, an encoder coupled to said output circuit, the encoder generating loading signals in response to signals from RAM output circuits for writing the replacement information into the next level of the column address of the directory and the data buffer on a first in/first output basis; and a counter coupled to the encoder and to the RAM circuit, the counter being operative to increment by one said loading signals and to apply an incremented count to one of the RAM circuits designated by the column address to enable the replacement of information in one of the locations of the data buffer during a replacement operation.
7. 7. A cache unit according to Claim 6, wherein the cache unit further includes address register means and means for coupling the RAM output circuits to the RAM circuits, the address register means generating a sequence of successive address signals during an initialization operation, said coupling means being response to selected ones of the address signals whereby the RAM circuits are initially set to predetermined values.
8. 8. A cache unit according to Claim 7, wherein the RAM output circuits include a plurality of bistable circuits, said bistable circuits being switched to a reset state in response to selected ones of the address signals during a sequential transfer of information for filling a first one of the levels of the directory and the data buffer and the;bistable circuits being operative to generate output signals for loading the column address locations of the RAM circuits with bits of information coded for indicating a second one of the levels of the directory and the data buffer into which the replacement information is to be written.
9. 9. A cache unit according to Claim 8, wherein the bistable circuits are operative in response to the address signals during the sequential transfer of information to generate output signals to fill the second level and subsequent levels of the directory and the buffer.
10. 10. A cache unit according to any of Claims 6 to 9, wherein the number of levels in the directory and the data buffer is four and wherein the RAM circuit stores two bits of information of each of the column addresses.

    Printed for Her Majesty's Stationery Office by the courier Press, Leamington Spa, 1981. Published by the Patent Office, 25 Southampton Buildings, London, WC2A lAY, from which copies may be obtained.