DE69330875T2 - CACHE DEVICE. - Google Patents

Description

Technical area

The present invention relates to a cache memory device for reading data at high speed for use with an information processing unit such as a microprocessor (hereinafter referred to as MPU).

Related state of the art

Cache memory devices have been widely used to improve the processing speeds of information processing units. The technologies of cache memory devices are described, for example, in:

(1) Harold S. Stone, "High Performance Computer Architecture (Translated Title)", March 30, 1989, Maruzen, pp. 23-42.

(2) Nikkei Electronics [434], November 16, 1987, Nikkei BP Company, pp. 159-174.

Documents 1 and 2 describe the basic structures of the conventional cache memory devices. The conventional cache memory devices include a memory with a smaller storage space than an external memory in order to increase the processing speed. This memory is called a cache memory. When data that is often read is stored in the cache memory, this data can be read quickly. When required data is not stored in the cache memory, it is read from an external memory of the cache memory device. In this case, the data is read at a normal speed. Next, a practical structure of the cache memory device and its operation will be described.

Fig. 2 is a schematic diagram showing a basic circuit of a conventional cache memory device.

In Fig. 2, reference numeral 50 is a cache memory device. The cache memory device 50 outputs cache data CD to a data read requester 1 (hereinafter, the data read requester is called data requester) as for example, a central processing unit, according to a cache address CA requested by it.

The cache memory device 50 includes a control circuit 10, a cache tag memory 11 and a cache data memory 12, and a match determination circuit 13. The control circuit 10 controls internal circuits of the cache memory device 50. The cache tag memory 11 is constructed of a high-speed, small-capacity random access memory (hereinafter referred to as RAM) or the like. The cache data memory 12 is also constructed of a RAM or the like. The cache tag memory 11 stores a part of addresses of data stored in the cache data memory 12. The cache tag memory 11 has an address terminal A, a data input/output terminal (hereinafter referred to as I/O terminal), a write enable terminal WE, and terminals VAi and VAe. The write enable terminal W E is activated by the control circuit 10. Similarly, the terminals VAi and VAe are activated by the control circuit 10. The cache data memory 12 stores data that is often read. The cache data memory 12 has an address terminal A, an I/O terminal D and a write enable terminal WE. The write enable terminal WE is activated by the control circuit 10. The match determination circuit 10 has an enable terminal E. When the enable terminal E is activated, the match determination circuit 13 detects whether or not two pieces of information match each other. When the two pieces of information match each other, the match determination circuit 13 outputs a hit signal HIT.

The cache memory 50 also includes registers 14 and 15, an external register 16, tri-state buffers 17, 18, 20 and 21, an AND gate 19 and an IA bus 22. The register 14 has an enable terminal E. When the enable terminal E is activated with a hit signal HIT, the register 14 stores a cache address CA. The register 15 also has an enable terminal E. When the enable terminal E is activated with a hit signal HIT, the register 15 stores cache data CD received via the ID bus 23. The external register 16 has a count enable terminal CE. When the count enable terminal CE is activated by the control circuit 10, the external register 16 stores an address EA. The three-state buffers 17, 18, 20 and 21 are controlled by the control circuit 10.

Address terminals A of the cache tag memory 11 and the cache data memory 12 are connected to the output side of the register 14 storing a cache address CA via the tri-state buffer 17 and the IA bus 22. The register 14 outputs the number of bits a of a cache address CA to the IA bus 22. Log2 (the number of tags) = b of the number of bits a is supplied to the address terminal A of the cache tag memory 11. The low-order part (b + 1) {where 1 = Log2 (number of lines)} of the cache address CA is supplied to the address terminal A of the cache data memory 12. The high-order part (a - b - 1) of the cache address CA is supplied to the match determination circuit 13. The high-order part (a - b - 1) of the cache address CA is supplied to both the I/O terminal D of the cache tag memory 11 and the match determination circuit 13. The terminal VAo of the cache tag memory 11 is connected to the enable terminal E of the match determination circuit 13 via the AND gate 19 controlled by the control circuit 10.

The I/O terminal D of the cache data memory 12 is connected to the ID bus 23. The ID bus 23 is connected to the input side of the register 15. The external register 16 is connected to the output side of the register 14. The counter enable terminal CE of the control circuit 10 is activated by the control circuit 10. When the terminal CE is activated, the external register 16 stores the number of bits a (= address EA) of the cache address CA supplied from the register 14. The output side of the external register 16 is connected to both the IA bus 22 via the three-state buffer 20 and an address terminal 30 of the external memory 30 constructed of a low-speed, large-capacity RAM or the like. The external memory 30 also has a data output terminal D, a D-WAIT terminal, and so on, as well as the address terminal A. The D-WAIT terminal outputs a signal that causes the cache memory device 50 to enter a wait state. The data output terminal D is connected to the ID bus 23 via the tri-state buffer 21. The D-WAIT terminal is connected to the input side of the control circuit 10.

Fig. 3 is a schematic diagram for explaining data stored in the cache tag memory 11. The cache tag memory 11 is constructed of addresses (tags), valid bits, and so on. The addresses (tags) are grouped so that the hardware overhead is reduced. The number of groups refers to the number of lines (or the number of blocks). Usually, the adjacent addresses are grouped. In Fig. 3, one group has four data. For example, data with the same bits except the two low-order bits is defined as one group.

Next, the operation of the cache memory device 50 shown in Fig. 2 will be described.

When the cache requester 1 supplies a cache address CA to the cache memory device 50, the cache address CA is temporarily stored in the register 14. Thereafter, the cache address CA is read, and it is determined whether or not data corresponds to the cache address CA stored in the cache memory 12 (i.e., whether or not a hit occurs). In other words, the match determination circuit 13 determines whether or not the cache address CA output from the register 14 to the IA bus 22 via the three-state buffer 17 matches the content of the cache tag memory 11. When they match each other (hereinafter, this state is called a hit), the match determination circuit 13 outputs a hit signal HIT to the control circuit 10 and to the enable terminals E of the registers 14 and 15. When the hit signal HIT is input to the control circuit 10, an output signal of the control circuit 10 activates the write enable terminals WE of the cache tag memory 11 and the cache data memory 12. Thus, data designated with the low-order part (b + 1) of the cache address CA is supplied from the cache data memory 12 to the ID bus 23. The data supplied to the ID bus 23 is cache data CD and is output to the cache requester 1 via the register 15.

On the other hand, when the data corresponds to the cache address CA requested by the cache requester 1 (this state is hereinafter called miss), the cache register 16 activated by the output signal of the control circuit 10 supplies the number of bits a (EA) of the cache address CA to the address terminal A of the memory 30. Thus, record data corresponding to the number of bits a is supplied from the output terminal D of the memory 30. The read data is supplied to the cache data memory 12 via the three-state buffer 21. Thus, the content of the cache data memory 12 is subjected to updating. Subsequently, the read data is Cache data CD and are fed to cache requester 1 via ID bus 23 and register 15. In this case, the read data is cache data CD.

Thus, when a miss occurs, data for a line having an address where a miss occurred is read from the external memory 30. Consequently, the contents of the cache data memory 12 undergo an update. There are two methods for updating the contents of the cache data memory 12 in accordance with the occurrence of a miss and for supplying real cache data CD to the cache requester 1.

First procedure

Fig. 4 is a timing chart showing the operation of the cache memory device 50 shown in Fig. 2. In the drawing, m, n + 1, ... represent addresses. A miss overhead time is a time period in which cache data becomes valid after a miss occurs.

In Fig. 4, n + 1 = "x ... x01" (in a binary notation). As shown in Fig. 3, one line has four addresses. The external memory can be accessed in two cycles. A tag contains one valid bit. In each of four write operations, tag data (= "x ... x") is written. However, in the last write operation, valid information is written to the valid bit. The two low-order bits of the external register 16 shown in Fig. 2 work as a counter. Whenever a miss occurs, the value of the cache address CA is loaded and the two low-order bits are cleared to "00".

As the simplest method for updating the cache data memory 12 after the occurrence of a miss and supplying the real cache data CD to the cache requester 1, as shown in Fig. 4, when a miss occurs, data is read from a predetermined address from a line containing it. For example, as shown in Fig. 4, when a line has four addresses, data is read in the order of "xx...x00", "x...x01", "x...x10" and "x...x11". While the data is being read, the cache data memory 12 is used to update the data. Thus, even if the cache data CD is read, it does not become valid.

Second procedure

By a memory interleaving method or an access method using the characteristics of a dynamic RAM (hereinafter referred to as DRAM) having, for example, a page mode or a static column, a burst transfer or a frame transfer can be supported to shorten the time for an overhead for a miss. Fig. 5 shows a structure of the second method.

Fig. 6 is a schematic diagram showing a circuit of a cache memory device 51 according to the second method. The parts of the structure common to Fig. 2 are denoted by the same reference numerals.

The cache memory device 51 uses a DRAM page mode. The difference between the cache memory device shown in Fig. 6 and that shown in Fig. 2 is that a counter output of the external register 16 is incremented by an adder 35. The output of the adder 35 is supplied to a selector 36. The output of the selector 36 is supplied to the counter. In Fig. 5, a reference numeral 40 represents a connected line.

A cache address CA requested by a cache requester 1 is composed of a tag TAG, a line address LA and an input line address IA stored in the order of the most significant bit (MSB) to the least significant bit (LSB) of the register 14. One of the outputs of the input line address 1A and the adder 35 is selected by the selector 36. The output of the selector 36 is supplied to a counter of an external register 16. The external memory 30 is composed of a DRAM. To operate the DRAM in the page mode, a low address strobe signal {hereinafter referred to as RASN (N represents negative logic)}, a column address strobe signal (hereinafter referred to as CASN), and a memory control signal S10 representing a wait signal ratio are exchanged between the external memory 30 and the control circuit 10.

In DRAM page mode, while RASN is at the L level, CASN pulses are supplied sequentially to perform high-speed read/write operations. In this mode, while RASN is at the "L"level, and the bit line level is maintained at the "L" level or the "H" level, the CAS operation is repeatedly performed to write or read data to a desired bit line.

Fig. 6 is a timing chart showing the operation of Fig. 5. In this timing chart, one line has four data. CK represents one clock. n represents that the two low-order bits are "0".

In the cache memory device 51 shown in Fig. 5, when a required cache address CA is stored in the register 14, the match determination circuit 13 determines whether or not a tag TAG stored in the register 14 matches data read from the cache tag memory 11 through the data output terminal Do. If these data do not match each other, a miss occurs. Thus, the tag TAG stored in the register 14 is supplied to the external register 16 through a line 40. The output of the external register 16 is supplied to the address terminal A of the external memory 30. With the memory control signal S10, data is read from the data output terminal D of the external memory at high speed in the page mode and supplied as cache data CD to the input terminal Di of the cache data memory 12. The cache data CD is read from the output terminal Do of the cache data memory 12. Thus, a time for an overhead for a miss can be shortened.

However, the cache memory devices 50 and 51 described above have the following disadvantages.

In the cache memory devices 50 and 51 as shown in Fig. 2, when a miss occurs, since it takes a long time to write the miss data to the cache data memory 12, a time for an overhead for a miss for which data is read is long. In the cache memory device 51 shown in Fig. 5, since the processing time of the DRAM constituting the external memory 30 and so on is shorter than the burst transfer rate, several clock periods are required for reading the miss data. The first miss data is followed by four data as shown in Fig. 6.

In the cache memory device 51, when the line next to a line containing an address where a miss occurred is required, the cache memory device 51 exits even from the burst transfer access mode. Thus, the cache memory device 51 should wait until the first data of the line is received after another miss occurred. In other words, because data of a line containing a miss is subjected to updating even though it can be estimated that another miss will occur in data of the subsequent addresses, data of only one predetermined line is subjected to updating. Thus, the hit rate is low. Consequently, it has been difficult to achieve cache memories with technical satisfaction.

It is an object of the present invention to provide a cache memory that has a reduced miss overhead time and an improved hit rate without increasing hardware overhead.

EP-0,029,517 discloses a cache memory device comprising a cache tag memory for storing high-order address information, a cache data memory for storing the data corresponding to a plurality of low-order address information, a match determination circuit for comparing the most significant bits of an input address with the address information stored in the cache tag memory, an address register for storing the input address only in a case of a miss, and a control circuit and an output circuit for outputting data corresponding to the input address in a case of a hit.

PATENT ABSTRACTS OF JAPAN, Vol. 11, No. 270 (P-611) September 3, 1987 & JP-A62 072 041 discloses comparing block addresses in an address register and a block load address register and calculating based on the decision of an input block word address where block loading is started and this is compared with the input block word address of the CPU memory read request to decide whether data at a request address is already written to a cache memory or not.

Disclosure of the invention

To solve the problems described above, the present invention provides a cache memory device as defined in independent claim 1. The dependent claims define particular embodiments of the invention.

According to another aspect of the present invention, there is provided a cache memory device comprising: a first cache memory for storing high-order address information of address information corresponding to desired data, a second cache memory for storing a plurality of low-order address information of the high-order address information and a plurality of data corresponding to the plurality of low-order address information, a first coincidence determination circuit for comparing high-order address information of address information inputted with the high-order address information stored in the first cache memory to determine whether or not they coincide with each other, a register for storing a plurality of input address information and generating a plurality of address information included in the high-order address information of the input address information only when the first detection circuit has determined a non-coincidence state, a control circuit for reading data corresponding to the input address information from the second cache memory when the first coincidence determination circuit has determined a coincidence state, for writing the high-order address information of the address information corresponding to the plurality of of address information included in the high-order address information of the address information generated by the register to the first cache memory when the first match determination circuit has determined a non-match state, and for writing the low-order address information of the address information and the plurality of data corresponding to the address information stored in an external memory to the second cache memory, a second match determination circuit for determining whether or not the address information generated by the register matches the input address information, and an output circuit for outputting data corresponding to the input address information supplied from the second cache memory when the first match determination circuit has determined a match state, for outputting data corresponding to the input address information supplied from the external memory when the second match determination circuit has determined a match state, and for outputting no data corresponding to the input address information when both the first and second match determination circuits have determined a non-match state.

Short description of the drawings

Fig. 1 is a schematic diagram showing a circuit of a cache memory device according to a first embodiment of the present invention;

Fig. 2 is a schematic diagram showing a circuit of a cache memory device according to a first related prior art reference;

Fig. 3 is a schematic diagram for explaining the contents stored in a cache tag memory;

Fig. 4 is a timing diagram showing the operation of the cache memory device of Fig. 2;

Fig. 5 is a schematic diagram showing a circuit of a cache memory device according to a second related prior art reference;

Fig. 6 is a timing chart showing the operation of the cache memory device of Fig. 5;

Fig. 7 is a timing chart showing the operation of the cache memory device of Fig. 1;

Fig. 8 is a schematic diagram showing a circuit of a cache memory device according to a second embodiment of the present invention;

Fig. 9 is a timing chart showing the operation of the cache memory device of Fig. 8;

Fig. 10 is a schematic diagram showing a circuit of a cache memory device according to a third embodiment of the present invention;

Fig. 11 is a timing chart showing the operation of the cache memory device of Fig. 10;

Fig. 12 is a schematic diagram showing a circuit of a cache memory device according to a fourth embodiment of the present invention;

Fig. 13 is a timing chart showing the operation of the cache memory device of Fig. 12;

Fig. 14 is a schematic diagram showing a circuit of a cache memory device according to a fifth embodiment of the present invention;

Fig. 15 is a timing chart showing the operation of the cache memory device of Fig. 14;

Fig. 16 is a schematic diagram showing a circuit of a cache memory device according to a sixth embodiment of the present invention;

Fig. 17 is a timing chart showing the operation of the cache memory device of Fig. 16.

Best ways to achieve invention

Fig. 1 is a schematic diagram showing a circuit of a cache memory device according to a first embodiment of the present invention.

In Fig. 1, reference numeral 100 is a cache memory device according to a first embodiment of the present invention. The difference between the cache memory device 100 shown in Fig. 1 and the cache memory device 50 shown in Fig. 2 is that the former includes a match determination circuit 150 and an OR gate 151. Whenever a cache data memory is updated due to the occurrence of a miss, an enable terminal E of the match determination circuit 150 is activated by an output signal of a control circuit 110. The match determination circuit 150 operates as follows. The match determination circuit 150 determines whether or not the number of bits a of a cache address CA received from a register 114 matches addresses of data written from an external memory 130 to a cache memory 112. The OR gate 151 ORs the output of the match determination circuit 150 and a tag hit signal TAG.HIT received from the match determination circuit 113. When they match each other, an enable terminal E of a register 115 is activated.

When a control circuit 110 receives the tag hit signal TAG. HIT from the match determination circuit 113, the control circuit 110 outputs a cache update signal S10a to turn on tri-state buffers 120 and 121 and output data read from a data output terminal D of the external memory 130 to an ID bus 123. The read data output to the ID bus 123 is supplied to the register 115 which is enabled by the OR gate 151. The output of the register 115 is cache data and is supplied to the cache requester 1. In other words, when the cache memory is being updated due to the occurrence of a miss, if the match determination circuit 150 has determined that two data match each other, data read from the external memory 130 is bypassed. Instead, the data is supplied to the cache requester 1 as cache data CD.

Next, the operation of the cache memory device 100 shown in Fig. 1 will be described with reference to Fig. 6.

Fig. 6 is a timing chart showing the operation of the cache memory device 200 shown in Fig. 1. In Fig. 6, it is assumed that n + 1 = "x ... x01" and that n + 4 = "Y ... Y00". In addition, it is assumed that one line has four addresses. The external memory 130 can initially read consecutive addresses with one wait cycle by a burst transfer. When the last write operation is performed, "1" is written to a valid bit. The two low-order bits of the external register 116 are a counter that operates when a count enable terminal CE is activated.

In Fig. 1, when the cache requester 101 supplies a cache address CA of desired data to the cache storage device 100, the cache address CA is written to the register 114. Until the cache data storage 112 is updated, the tri-state buffer 117 is turned on with a cache update signal S10a supplied from the control circuit 104. Thus, the cache address CA stored in the register 114 is supplied to an IA bus 122. The cache data storage 112 receives addresses of a predetermined tag and a predetermined line from the IA bus 122 (for example, a low-order part (b + 1) via the address terminal A). Stored data corresponding to the address is supplied to the ID bus via the I/O terminal D.

In addition, to determine whether or not data stored in the cache data memory 112 matches the requested cache address CA, the data stored in the cache tag memory 111 is read from the I/O port D according to the predetermined tag address Log2 (the number of tags) = b. The match determination circuit 113 determines whether or not the read data matches the predetermined tag. When the cache data memory 112 is in the read state (i.e., not in the cache update state) and the content of the cache tag memory 111 represented by the port VAo of the cache data memory 111 is valid, the result of the determination by the match determination circuit 113 enabled by the AND gate 124 is valid. Thus, the match determination circuit 113 carries a tag hit signal TAG. HIT to control circuit 110.

At this point, if the match determination circuit 113 has determined that both data match each other, a hit signal HIT output from the OR gate 151 of the tag hit signal TAG.HIT is supplied to the cache requester 1 to inform it that the content of the ID bus 123 is valid. The hit signal HIT allows the register 115 to be written. In addition, the hit signal HIT allows data to be written to the register 114 to receive a next cache address from the cache requester 1. On the other hand, when the tag hit signal TAG.HIT output from the match determination circuit 113 represents that both data do not match each other, a miss occurs. In this case, the cache data memory 112 is subjected to updating at the next cycle.

When the cache data memory 114 is in an update state, the control circuit 110 outputs a cache update signal SIOa to the tri-state buffers 120 and 121 so that they are turned on. Thus, data can be received from the external memory 112. In addition, the control circuit 110 activates the count enable terminal CE of the external register 116, which is an address supply source to the IA bus 122, to change the read data supply source of the ID bus 123 to the external memory 130. Whenever a miss occurs, the content of the external register 116 is always subjected to updating.

At this point, the signal level of a terminal D-WAIT of the external memory 130, which represents that the external read data is in a valid timing, becomes an "L" level. In addition, the signal level of the cache update signal SIOa output from the control circuit 110 is at an "H" level. Thus, the control circuit 110 activates write enable terminals WE of the cache tag memory 111 and the cache data memory 112 at predetermined intervals. Since the two low-order bits of the external register 116 function as a counter, when the write enable terminals WE of the cache tag memory 111 and the cache data memory 112 are activated, a count enable terminal CE of the external register 116 is activated to thereby count up the counter.

This operation is repeated n times (for example, four times). Thus, all data from line addresses where a miss occurred are updated. Data is read from the data output terminal D of the external memory 130. The read data is applied to an I/O terminal D of the cache data memory 112 via the tri-state buffer 121. Thus, the cache data memory 112 is subjected to updating. The control circuit 110 outputs a signal representing that only the fourth operation is valid and supplies this signal to a terminal VAi of the cache tag memory 111. The cache update operation in this embodiment is the same as that of the cache memory device 50 according to the first related prior art reference shown in Fig. 2.

In this embodiment, in addition to the cache update operation described above, while cache data is being updated, when write data to be written to the cache data memory 112 is requested by the cache requester 1, the write data is redirected to the cache requester 1. In other words, while cache data is being updated, the output of the control circuit 110 causes the match determination circuit 150 to be enabled. The match determination circuit 150 determines whether or not the content of the register 114 matches the content of the external register 116. The output of the match determination circuit 150 and the tag hit signal TAG.HIT supplied from the match determination circuit 150 are supplied to the OR gate 151. The output of the OR gate 151 is a hit signal HIT. The hit signal HIT is supplied to the cache requester 1. In addition, the register 115 is enabled. Thus, data read from the external memory 130 to the ID bus 123 is supplied to the cache requester 1.

This operation will be described with reference to Fig. 7. When a miss occurs at n+1 of a cache address CA at a clock period 2, the cache memory device 100 subjects the cache tag memory 111 and the cache data memory 112 to an update. At this point, the signal TAG-HIT becomes an "L" state, which represents that the match determination circuit 113 has determined that the data stored in the register 114 does not match the data stored in the cache data memory 112. At a clock period 3, the control circuit 110 enables the match determination circuit 150 and the external register 116 according to the signal state of TAG-HIT. In addition, the control circuit 15 causes the cache tag memory 111 and the cache data memory 112 to be in the write enable state. The cache address CA ("x...x01") is written directly to the external Register 116. Address data EA is input to match determination circuit 150 corresponding to cache address CA and cache address supplied to external register 116. At this point, the two low order bits of external register 116 function as a counter. In addition, the counter counts up by one whenever a line is written to cache memories 111 and 112. Thus, address data EA at clock period 4 is "x...x01". At clock periods 5, 6 and 7, address data EA are "x...x10", "x...x11" and "x...x00", respectively. Thus, at clock period 4, match determination circuit 150 determines that cache address CA matches address data EA. Consequently, match determination circuit 150 enables registers 114 and 115. The external memory 130 outputs data corresponding to the address data EA "x...x01" generated by the external memory 116. The output of the external memory 130 is cache data CD and is supplied to the cache requester 101 via the register 115. In addition, the cache data CD is written to the cache data memory 112. Since the register 114 is enabled, the cache requester 101 supplies n+2 ("x...x10") as the next cache address CA to the register 114. At clock period 5, the cache memory device 100 updates cache data of the line containing n+1. In other words, the cache memory device 100 updates data corresponding to the address data "x ... x10" generated by the external register 116 and writes it to the cache data memory 112. Since the register 114 has stored n + 2 and the cache tag memory 111 has not stored the tag "x ... x", the coincidence determination circuit 113 does not determine that they coincide with each other. However, because the coincidence determination circuit 150 and the external register 116 are kept in the enable state, n + 2 of the cache address CA is supplied to the coincidence determination circuit 150. At this point, because the coincidence determination circuit 150 has received the same address data as n + 2 from the other input, it determines that two data coincide with each other to thereby cause the registers 114 and 115 to be kept in the enable state. The data corresponding to n + 2 of the cache address CA requested by the cache requester 101 is supplied to both the cache data memory 112 and the cache requester 101 via the register 115. Since the register 114 is in the enable state, the cache requester 1 supplies n + 3 ("x ... x11") as the next cache data CA. Since n + 3 is address data preceding by n + 2, the same operation is performed at a clock period 6. as that at the clock period 5. However, at a clock period 7, n + 4 ("Y ... Y00") of the cache address CA is input. n + 4 matches a tag stored in the cache tag memory 111. However, n + 4 does not match the address data "x ... x00" for which the fourth write operation is performed. Thus, the enable states of the registers 114 and 115 are cleared. At this point, "x ... x00" is supplied as the address data EA to the external memory 130. In addition, data corresponding to the address data "x ... x00" has been supplied to the cache data memory 112 and the register 115, and data corresponding to "x ... x00" as cache data CD is supplied to the cache requester 101 via the register 115. At the clock period 7, "x ... x" is written to the cache tag memory 111. At a clock period of 8, the same operation as that at clock period 2 is performed. If two tags do not match at a clock period of 9 or later, the update operation described above is performed.

Second embodiment

Fig. 8 is a schematic diagram showing a circuit of a cache memory device according to a second embodiment of the present invention. In Fig. 8, reference numeral 200 is the cache memory device. The cache memory device 200 according to the second embodiment is different from the cache memory device 100 according to the first embodiment in that the cache data update operation can be temporarily interrupted in accordance with a wait request issued by a cache requester 1. Unlike the cache memory device 100 according to the first embodiment, the cache memory device 200 includes three AND gates 201, 202, and 203. The AND gate 201 ANDs a signal representing a wait request state issued by the cache requester 1 and an output signal of the control circuit 110, and outputs to write enable terminals WE of a cache tag memory 111 and a cache data memory 112. In other words, when the cache requester 1 has not issued a wait request and write requests are issued to the cache tag memory 111 and the cache data memory 112, the AND gate 201 activates the write enable terminals WE of the cache tag memory 111 and the cache data memory 112. On the other hand, the AND gate 202 subjects the signal representing a wait request state issued by the cache requester 101 and the output signal of the control circuit 110 and inputs the resultant signal to a count enable terminal CE of an external register 116. In other words, when the cache requester 1 has not issued a wait request and a request to increment the count of the external register 116 by 1 is issued, the AND gate 202 activates the count enable terminal CE of the external register 116. The AND gate 203 ANDs the signal representing the wait request issued by the cache requester 1 and an output signal of an OR gate 151 (namely, a signal representing a HIT state of cache data) and inputs the resultant signal to enable terminals E of the registers 114 and 115. In other words, when the cache requester 1 has not issued a wait request and a cache address CA matches a tag stored in the cache tag memory 111 or the cache address CA matches data stored in the external register 116, the AND gate 203 activates the enable terminals E of the registers 114 and 115. When the cache requester 1 issues a wait request, data writing to the cache tag memory 111 and the cache data memory 112, data address output to the external register 116 corresponding to a read request by the external register 116, and storage of the cache data CD in the register 115 are inhibited. Thus, the entire update operation of cache data in the cache storage device 200 is temporarily suspended (it is in a wait state).

Next, the operation of the cache memory device 200 shown in Fig. 8 will be described with reference to Fig. 9. Fig. 9 is a timing chart showing the operation of the cache memory device 200 of Fig. 8.

In Fig. 9, in clock periods 2 to 4 in which the cache requester 1 has issued a wait request, the registers 114 and 115 are deactivated. In these periods, the registers 114 and 115 store cache addresses CA = n + 1 and cache data CD = m, respectively. In addition, the external register 116 stores n + 1. Since the signal levels of the write enable terminals WE of the cache tag memory 111 and the cache data memory 112 are at the "L" level, they are not activated.

Third embodiment

Fig. 10 is a schematic diagram showing a circuit of a cache memory device according to a third embodiment of the present invention. In Fig. 10, reference numeral 300 is a cache memory device according to the third embodiment. The difference between the cache memory device according to the third embodiment and the cache memory device 100 according to the first embodiment is that although cache data is updated in accordance with a wait request issued by a cache requester 1, data updated in a wait state can be easily accessed. The cache memory device 300 includes a plurality of buffers 301, a plurality of match determination circuits 302, a plurality of three-state buffers 304, a three-state buffer 321, an AND gate 303, and OR gates 305 and 306. The match determination circuits 302 correspond to the buffers 301. The three-state buffers 304 correspond to the buffers 301. The registers 301 each store a group of addresses and data read from an external memory 130 and a validity flag which is a signal output from a control circuit 110. An output of the control circuit 110 is input to an enable terminal E of the buffer 301. Thus, the buffer 301 is activated. In this embodiment, three buffers 301 (buffers 301-1, 301-2 and 301-3) are provided. Since one line has four addresses and cache data is updated line by line with three buffers 301, data can be updated appropriately. However, it should be noted that the number of buffers 301 is not limited to three. The number of the match determination circuits 302 is three corresponding to the three buffers 301. Each of the match determination circuits 302 is activated with a validity flag signal V received from the corresponding buffer 301. Each of the match determination circuits 302 determines whether or not a cache address CA received from the register 114 matches an address stored in the corresponding buffer 301. The output of the match determination circuit 302 controls the corresponding three-state buffer 304. In addition, the output of the match determination circuit 302 is supplied to the OR gate 305. The OR gate 305 ORs the outputs of the match determination circuits 302 and outputs the resultant Signal to the OR gate 351. In addition, an inverted signal of the output of the OR gate 305 controls the operation of the three-state buffer 321. The number of the three-state buffers 304 is three, corresponding to three match determination circuits 302. Each of the three-state buffers 304 is controlled by the output of the corresponding match determination circuits 302.

Data stored in each of the buffers 301 is output to an ID bus 123. Each of the tri-state buffers 321 outputs data stored in the external memory 130 to the ID bus 123 in accordance with an inverted signal of the output of the OR gate 305. The OR gate 351 is a three-input type OR gate to which the output of the OR gate 305 and the results of the match determination circuits 113 and 150 are input. The output of the OR gate 351 is supplied to the AND gate 303. In addition, a wait signal WAIT received from the cache requester 1 is supplied to the AND gate 303. The AND gate 303 ANDs the output signal of the OR gate 351 and the wait signal WAIT and inputs the resulting signal to enable terminals E of the registers 114 and 115.

Next, the operation of the cache memory device 300 shown in Fig. 10 will be described with reference to Fig. 11. Fig. 11 is a timing chart showing the operation of the cache memory device 300 of Fig. 10.

In Fig. 11, a miss (the tag HIT is "0") occurs at a clock period 2. Thus, the cache storage device 300 starts the update operation of cache data. However, the cache requester 1 is in a waiting state at the clock period 2. In the second embodiment, the cache data update operation is not performed while the cache requester 1 is in a waiting state. However, in the third embodiment, at a clock period 4, while the cache requester 1 is in the waiting state, when data of the external memory 130 is output, the data is written to a cache data memory 112. In addition, the data is supplied to the register 115 via the tri-state buffer 321. At the clock period 4, because the cache requester 1 is still in the waiting state, it does not receive the cache data stored in the register 115. However, at clock period 4, an output signal from control circuit 110 activates one of buffers 301 (for example, buffer 301-0), to store an address and corresponding data output from external memory 130. In addition to the address and data, the output of control circuit 110 causes a validity flag to become valid. At clock period 5, the cache requester requests the same address as it did at clock period 4. At this point, because the required address and data have been stored in register 301 at clock period 4, one of match determination circuits 302 determines that two pieces of data match each other. Thus, match determination circuit 302 disables tri-state buffer 321 via OR gate 305. Consequently, data of the required address is output from register 301 (from buffer 301-0) to ID bus 123. At this point, data corresponding to the next address is written to cache data memory 112. In addition, the same address and the same data are written to the buffer 301 (for example, the buffer 301-1). Thus, although an address output by the cache requester 1 differs from a write timing to the cache data storage 112, cache data CD is supplied from the buffers 301 (for example, the buffers 301-1 and 301-2) to the cache requester 1.

Fourth embodiment

Fig. 12 is a schematic diagram showing a circuit of a cache memory device according to a fourth embodiment of the present invention. In Fig. 12, reference numeral 400 is the cache memory device according to the fourth embodiment. The difference between the cache memory device 400 according to the fourth embodiment and the cache memory device 300 according to the third embodiment is that an address and data are written to a buffer 301 when necessary. Unlike the cache memory device according to the third embodiment, the cache memory device 400 includes a buffer monitor circuit 401. The buffer monitor circuit 401 determines whether or not cache data to be updated should be stored in the buffer 301 while a cache requester 1 is in a waiting state. The buffer monitoring circuit 401 stores the resulting data in predetermined buffers 301 (in this example, buffers 301-1 and 301-2 as shown in Fig. 12). In addition, the buffer monitoring circuit 401 invalidates data that is not necessary. The buffer monitoring circuit 401 receives a Wait signal WAIT, output signals (determined results) of the match determination circuits 150 and 302, an output of an external register 116, and an output signal of a control circuit 110. The output signal of the control circuit 110 activates write enable terminals of a cache tag memory 111 and a cache data memory 112. The buffer control circuit 110 outputs a signal activating the buffer 301 and a validity flag representing the validation of data stored in the buffer 301.

Next, the operation of the cache memory device 400 shown in Fig. 12 will be described with reference to Fig. 13. Fig. 13 is a timing chart showing the operation of the cache memory device 400 of Fig. 12.

In the buffer monitor circuit 401, there are conditions for storing data to the buffers 301 (the buffers 301-0 and 301-1) and for invalidating data stored in the buffers 301.

(1) Conditions for storing data to buffer 301-0

the one least significant bit of the address of data written to the cache data memory is 0;

data stored in buffer 301-0 is invalid; and

Cache requester 1 is in a wait state while a bypass hit occurs; or

Cache requester 1 is in the waiting state while a hit occurs in buffer 301-1.

(2) Conditions for storing data to buffer 301-1

the one least significant bit of the address of data written to the cache data memory is 0;

data stored in buffer 301-1 is invalid; and

Cache requester 1 is in the waiting state while a bypass hit occurs; or

Cache requester 1 is in the waiting state while a hit occurs in buffer 301-0.

(3) Conditions for invalidating data stored in buffer 301-0

the one least significant bit of the address of data written to the cache data memory is 0;

Cache requester 1 is not in the wait state while a bypass hit occurs or a hit occurs in buffer 301-0.

(4) Conditions for invalidating data stored in buffer 301-1

the one least significant bit of the address of data written to the cache data store is 1; and

Cache requester 1 is not in the waiting state while a bypass hit occurs or a hit occurs in buffer 301-1.

At clock period 2, a miss occurs and thereby the cache data memory 112 undergoes an update. At clock period 4, data n+1 occurs on an ID bus 123 where data is read from an external memory 130 (i.e., a bypass hit occurs). At clock period 4, the cache requester 1 is in a wait state. For example, if the low-order bit of the address of data n+1 is "0", condition (1) described above is satisfied. Thus, the data n+1 is written to the buffer 301-0. At clock period 5, a hit occurs in the buffer 301-0 when the cache requester 1 is in the wait state. Thus, the data stored in the buffer 301-0 is not invalidated. However, because the conditions (2) are satisfied (i.e., because the low-order bit of the data n + 1 is "0", the low-order bit of the next data n + 2 is "1"), the data n + 2 is written to the buffer 301-1. When the conditions (1) to (4) described above are satisfied, new data is written or invalidated.

In the above-described embodiments, the cache memory device according to the present invention has been described. However, it should be noted that the circuits and timings of operations in the above-described embodiments may be modified in various ways as long as the above-described operations can be achieved.

Commercial applicability

As described above, according to the first embodiment of the present invention, since a means for supplying data, written to a cache requester while cache data is being updated due to a miss occurrence, the hit rate can be improved, and the time for a miss overhead can be reduced.

According to the second embodiment of the present invention, since a means for temporarily suspending the updating of cache data in accordance with a wait request by a cache requester is provided in the apparatus according to the first embodiment, the operability of the entire system having a cache storage apparatus can be improved.

According to the third embodiment of the present invention, since means for temporarily stopping the output of cache data to a cache requester in accordance with a wait request issued by it and means for buffer means for storing cache data subjected to updating in the wait state of the cache data are provided in the apparatus according to the first embodiment, cache data can be sequentially updated regardless of occurrence of a wait request. In addition, cache data that has been subjected to updating can be accessed in the wait state, thereby improving operability more than in the apparatus of the second embodiment.

According to the fourth embodiment of the present invention, a means for determining the necessity of storing cache data to be stored in a buffer means is provided in the apparatus according to the third embodiment to store necessary cache data in the buffer means. Thus, the same effect as in the third embodiment can be achieved by a smaller amount of hardware than in the third embodiment.

Claims (8)

1. A cache memory device (100) for reading data corresponding to an input address information (CA) at high speed, wherein the cache memory device (100) is coupled to a main memory (130) for storing a plurality of data each corresponding to an address information, and wherein each address information has a high-order address part (TAG) and a low-order address part, and wherein the cache memory device (100) stores data that is a part of the plurality of data, wherein the cache memory device (100) has: a first register (114) for receiving, storing and outputting the input address information (CA); a first memory (111) for storing the high-order address parts (TAG) corresponding to respective ones of the data; a second memory (112) for storing the data; a first comparison circuit (113) for comparing the high-order address part of the input address information with the high-order address part stored in the first memory (111), the first comparison circuit (113) detecting whether these address parts match; an output circuit (115) for receiving and outputting data read from the second memory (112) when the first comparison circuit (113) detects that the address parts match; a second register (116) for storing the input address information only when the first comparison circuit (113) has detected that the address parts do not match; characterized in that the second register (116) is configured to generate a plurality of low-order address parts by using the low-order bits of the second register as a counter and output updated address information comprising the plurality of generated low-order address parts and the high-order address part of the stored address information for accessing the main memory (130); a second comparison circuit (150) compares an output of the first register (114) with the updated address information of the second register (116); the output circuit (115) is configured to receive and output data read from the main memory (130) in the event of a non- matching comparison result of the first comparison circuit (113) and a matching comparison result of the second comparison circuit (150). 2. The cache memory device (100) of claim 1, wherein the output circuit (115) comprises a third register. 3. Cache memory device (100) according to claim 1, wherein the updated address information of the second register (116) is for updating the first memory (111) with the high-order address part (TAG) and for updating the second memory (112) with data read from the main memory (130) that is accessed. 4. The cache memory device (200) of claim 1, wherein the cache memory device (200) further comprises a disabling circuit (203) for disabling receiving data read from the main memory (130) to the output circuit (115). 5. The cache memory device (200) of claim 1, wherein the cache memory device (200) further comprises a disabling circuit (202, 203) for disabling receiving data read from the main memory (130) to the output circuit (115) and generating the plurality of low order address parts of the second register (116). 6. The cache memory device (200) of claim 3, wherein the cache memory device (200) further comprises a disabling circuit (201, 202, 203) for disabling receiving the data read from the main memory (130) to the output circuit (115), generating the plurality of low-order address parts of the second register (116), and updating the first and second memories (111, 112). 7. The cache memory device (300) of claim 4, wherein the cache memory device (300) further comprises: Register (301) for storing the updated address information of the second register (116) and data read out from the main memory (130) according to the updated address information; a plurality of comparison circuits (302) for comparing the address information stored in the registers (301) with input address information further received from the first register (114); a plurality of three-state buffers (304, 305) for transferring the data stored in the registers (301) to the output circuit (115) according to the comparison result of one of the plurality of comparison circuits (302) and for deactivating the inhibit circuit (303). 8. The cache memory device (300) according to claim 7, wherein the cache memory (400) further comprises a monitoring circuit (400) for controlling the registers (301) for storing the updated address information and the data according to the updated address information, the monitoring circuit (401) making a determination according to the comparison result of the first and second comparison circuits (113, 150) and the comparison circuits (302).