DE3685622T2 - DATA TRANSFER CONTROL UNIT AND SYSTEM. - Google Patents

DATA TRANSFER CONTROL UNIT AND SYSTEM.

Info

Publication number
DE3685622T2
DE3685622T2 DE8686113402T DE3685622T DE3685622T2 DE 3685622 T2 DE3685622 T2 DE 3685622T2 DE 8686113402 T DE8686113402 T DE 8686113402T DE 3685622 T DE3685622 T DE 3685622T DE 3685622 T2 DE3685622 T2 DE 3685622T2
Authority
DE
Germany
Prior art keywords
control unit
data transfer
transfer control
data
unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8686113402T
Other languages
German (de)
Other versions
DE3685622D1 (en
Inventor
Masayuki Hanada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3685622D1 publication Critical patent/DE3685622D1/en
Publication of DE3685622T2 publication Critical patent/DE3685622T2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
DE8686113402T 1985-09-30 1986-09-30 DATA TRANSFER CONTROL UNIT AND SYSTEM. Expired - Lifetime DE3685622T2 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60217112A JPS6275860A (en) 1985-09-30 1985-09-30 Data transfer controller

Publications (2)

Publication Number Publication Date
DE3685622D1 DE3685622D1 (en) 1992-07-16
DE3685622T2 true DE3685622T2 (en) 1992-12-24

Family

ID=16699037

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686113402T Expired - Lifetime DE3685622T2 (en) 1985-09-30 1986-09-30 DATA TRANSFER CONTROL UNIT AND SYSTEM.

Country Status (4)

Country Link
US (1) US4864533A (en)
EP (1) EP0217350B1 (en)
JP (1) JPS6275860A (en)
DE (1) DE3685622T2 (en)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0303751B1 (en) * 1987-08-20 1992-05-20 International Business Machines Corporation Interface mechanism for controlling the exchange of information between two devices
US5129072A (en) * 1989-03-08 1992-07-07 Hewlett-Packard Company System for minimizing initiator processor interrupts by protocol controller in a computer bus system
JP2978539B2 (en) * 1989-07-24 1999-11-15 日本電気株式会社 Data transfer control device
EP0410382A3 (en) * 1989-07-24 1991-07-24 Nec Corporation Data transfer controller using direct memory access method
KR940009702B1 (en) * 1989-11-29 1994-10-17 마쯔시다덴기산교 가부시기가이샤 Data transmission apparatus
JPH0496163A (en) * 1990-08-08 1992-03-27 Nec Corp Dma controller
EP0558208B1 (en) * 1992-02-26 1998-12-16 Cirrus Logic, Inc. Digital video editing processing unit
US5423008A (en) * 1992-08-03 1995-06-06 Silicon Graphics, Inc. Apparatus and method for detecting the activities of a plurality of processors on a shared bus
US6185634B1 (en) * 1996-09-27 2001-02-06 Emc Corporation Address triggered DMA controller with an indicative signal including circuitry for calculating a new trigger address value based on the sum of the current trigger address and the descriptor register data with a trigger address register
JPH10124447A (en) * 1996-10-18 1998-05-15 Fujitsu Ltd Data transfer control method and device
FR2757306B1 (en) * 1996-12-17 1999-01-15 Sgs Thomson Microelectronics METHOD AND DEVICE FOR READING WITH PREDICTION OF A MEMORY

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4403282A (en) * 1978-01-23 1983-09-06 Data General Corporation Data processing system using a high speed data channel for providing direct memory access for block data transfers
US4479179A (en) * 1979-07-30 1984-10-23 International Business Machines Corporation Synchronous cycle steal mechanism for transferring data between a processor storage unit and a separate data handling unit
US4371932A (en) * 1979-07-30 1983-02-01 International Business Machines Corp. I/O Controller for transferring data between a host processor and multiple I/O units
US4417304A (en) * 1979-07-30 1983-11-22 International Business Machines Corporation Synchronous cycle steal mechanism for transferring data between a processor storage unit and a separate data handling unit
JPS573126A (en) * 1980-06-05 1982-01-08 Nec Corp Input and output controlling system
JPS5717049A (en) * 1980-07-04 1982-01-28 Hitachi Ltd Direct memory access controlling circuit and data processing system
JPS605397Y2 (en) * 1980-12-29 1985-02-19 富士通株式会社 Data transfer buffer circuit
US4407016A (en) * 1981-02-18 1983-09-27 Intel Corporation Microprocessor providing an interface between a peripheral subsystem and an object-oriented data processor
US4504902A (en) * 1982-03-25 1985-03-12 At&T Bell Laboratories Cache arrangement for direct memory access block transfer
US4490784A (en) * 1982-04-21 1984-12-25 Ives David C High-speed data transfer unit for digital data processing system
US4575814A (en) * 1982-05-26 1986-03-11 Westinghouse Electric Corp. Programmable interface memory
US4613954A (en) * 1982-11-16 1986-09-23 Burroughs Corporation Block counter system to monitor data transfers
US4607348A (en) * 1983-02-28 1986-08-19 Burroughs Corporation Transfer rate control system from tape peripheral to buffer memory of peripheral controller
JPS59231652A (en) * 1983-06-13 1984-12-26 Hitachi Ltd Detection system for memory access overlap
US4534013A (en) * 1983-06-30 1985-08-06 Burroughs Corporation Automatic write system for peripheral-controller
AU564271B2 (en) * 1983-09-22 1987-08-06 Digital Equipment Corporation Retry mechanism for releasing control of a communications path in a digital computer system
US4612542A (en) * 1984-12-20 1986-09-16 Honeywell Inc. Apparatus for arbitrating between a plurality of requestor elements
JPS61224051A (en) * 1985-03-29 1986-10-04 Fujitsu Ltd Buffer memory control system

Also Published As

Publication number Publication date
EP0217350A3 (en) 1989-06-07
JPH0556548B2 (en) 1993-08-19
EP0217350B1 (en) 1992-06-10
DE3685622D1 (en) 1992-07-16
US4864533A (en) 1989-09-05
JPS6275860A (en) 1987-04-07
EP0217350A2 (en) 1987-04-08

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)