FR2410937A1 - Procede et dispositif de montage de plaquette de circuit imprime pour sous-systeme de memoire - Google Patents

Procede et dispositif de montage de plaquette de circuit imprime pour sous-systeme de memoire

Info

Publication number
FR2410937A1
FR2410937A1 FR7831184A FR7831184A FR2410937A1 FR 2410937 A1 FR2410937 A1 FR 2410937A1 FR 7831184 A FR7831184 A FR 7831184A FR 7831184 A FR7831184 A FR 7831184A FR 2410937 A1 FR2410937 A1 FR 2410937A1
Authority
FR
France
Prior art keywords
printed circuit
circuit board
memory
holes
mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7831184A
Other languages
English (en)
Other versions
FR2410937B1 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Italia SpA
Bull HN Information Systems Inc
Original Assignee
Honeywell Information Systems Italia SpA
Honeywell Information Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Information Systems Italia SpA, Honeywell Information Systems Inc filed Critical Honeywell Information Systems Italia SpA
Publication of FR2410937A1 publication Critical patent/FR2410937A1/fr
Application granted granted Critical
Publication of FR2410937B1 publication Critical patent/FR2410937B1/fr
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H05K1/116—Lands, clearance holes or other lay-out details concerning the surrounding of a via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0286—Programmable, customizable or modifiable circuits
    • H05K1/029—Programmable, customizable or modifiable circuits having a programmable lay-out, i.e. adapted for choosing between a few possibilities
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0286—Programmable, customizable or modifiable circuits
    • H05K1/0295—Programmable, customizable or modifiable circuits adapted for choosing between different types or different locations of mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298—Multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09954—More mounting possibilities, e.g. on same place of PCB, or by using different sets of edge pads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10689—Leaded Integrated Circuit [IC] package, e.g. dual-in-line [DIL]

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Structure Of Printed Boards (AREA)
  • Numerical Control (AREA)
  • Dram (AREA)

Abstract

PROCEDE ET DISPOSITIF DE MONTAGE DE PLAQUETTE DE CIRCUIT IMPRIME POUR REALISER DES SOUS-SYSTEMES DE MEMOIRE AYANT DES CARACTERISTIQUES DIFFERENTES EN OPTION DANS UN SYSTEME DE TRAITEMENT DE DONNEES. CES SOUS-SYSTEMES DE MEMOIRE SONT REALISES SUR UNE MEME PLAQUETTE DE CIRCUIT IMPRIME A DEUX COUCHES MUNIES DE CONDUCTEURS HORIZONTAUX ET VERTICAUX PERMETTANT D'APPLIQUER DES SIGNAUX ELECTRIQUES A DES FILS DE SORTIE D'UN ENSEMBLE DE BOITIERS DE CIRCUITS INTEGRES DE CHAQUE SOUS-SYSTEME DE MEMOIRE, CET ENSEMBLE DE BOITIERS ETANT INSERE DANS UN ENSEMBLE DE TROUS SUR UNE PARTIE DE LA PLAQUETTE, AU MOINS UNE AUTRE PARTIE DE LA PLAQUETTE COMPRENANT UN SECOND ENSEMBLE DE TROUS DECALES D'UN GROUPE DU PREMIER ENSEMBLE DE TROUS POUR CONNECTER LES FILS DE SORTIE DE CERTAINS BOITIERS DUDIT ENSEMBLE DE BOITIERS CORRESPONDANT A UNE CARACTERISTIQUE DU SOUS-SYSTEME DE MEMOIRE CONSIDERE. APPLICATION A LA REALISATION D'UN SYSTEME DE MEMOIRE A PARTIR D'UN SEUL DESSIN DE MASQUE PHOTOGRAPHIQUE SUR PLAQUETTE DE CIRCUIT IMPRIME.
FR7831184A 1977-12-01 1978-11-03 Procede et dispositif de montage de plaquette de circuit imprime pour sous-systeme de memoire Expired FR2410937B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/856,433 US4190901A (en) 1977-12-01 1977-12-01 Printed circuit board apparatus which facilitates fabrication of units comprising a data processing system

Publications (2)

Publication Number Publication Date
FR2410937A1 true FR2410937A1 (fr) 1979-06-29
FR2410937B1 FR2410937B1 (fr) 1988-03-25

Family

ID=25323618

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7831184A Expired FR2410937B1 (fr) 1977-12-01 1978-11-03 Procede et dispositif de montage de plaquette de circuit imprime pour sous-systeme de memoire

Country Status (8)

Country Link
US (1) US4190901A (fr)
JP (1) JPS54151329A (fr)
AU (1) AU517165B2 (fr)
CA (1) CA1119314A (fr)
DE (1) DE2851608A1 (fr)
FR (1) FR2410937B1 (fr)
GB (1) GB2009517B (fr)
YU (1) YU39570B (fr)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4266285A (en) * 1979-06-28 1981-05-05 Honeywell Information Systems, Inc. Row selection circuits for memory circuits
WO1982000398A1 (fr) * 1980-07-10 1982-02-04 W Considine Procede de fabrication de representations de plaques de circuits imprimes, et procede et moyen de fabrication de plaques de circuits imprimes
US4339784A (en) * 1980-08-11 1982-07-13 Rca Corporation Solder draw pad
US4507127A (en) * 1981-12-21 1985-03-26 Nippon Furnace Kogyo Co., Ltd. System for recovering resources from sludge
US4613940A (en) * 1982-11-09 1986-09-23 International Microelectronic Products Method and structure for use in designing and building electronic systems in integrated circuits
JPS63211692A (ja) * 1987-02-27 1988-09-02 株式会社日立製作所 両面配線基板
US5066831A (en) * 1987-10-23 1991-11-19 Honeywell Inc. Universal semiconductor chip package
US4891789A (en) * 1988-03-03 1990-01-02 Bull Hn Information Systems, Inc. Surface mounted multilayer memory printed circuit board
US5036163A (en) * 1989-10-13 1991-07-30 Honeywell Inc. Universal semiconductor chip package
US5276832A (en) * 1990-06-19 1994-01-04 Dell U.S.A., L.P. Computer system having a selectable cache subsystem
US5130894A (en) * 1990-11-26 1992-07-14 At&T Bell Laboratories Three-dimensional circuit modules

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1590612A1 (de) * 1966-05-27 1970-04-16 Standard Elek K Lorenz Ag Verdrahtungsmatrix
DE1902494A1 (de) * 1969-01-18 1970-08-13 Kloeckner Moeller Elek Zitaets System elektronischer Funktions-Baueinheiten

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL7013032A (fr) * 1970-09-03 1972-03-07
US3917984A (en) * 1974-10-01 1975-11-04 Microsystems Int Ltd Printed circuit board for mounting and connecting a plurality of semiconductor devices
JPS5239440Y2 (fr) * 1974-10-17 1977-09-06

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1590612A1 (de) * 1966-05-27 1970-04-16 Standard Elek K Lorenz Ag Verdrahtungsmatrix
DE1902494A1 (de) * 1969-01-18 1970-08-13 Kloeckner Moeller Elek Zitaets System elektronischer Funktions-Baueinheiten

Also Published As

Publication number Publication date
YU39570B (en) 1984-12-31
AU4203678A (en) 1979-06-07
AU517165B2 (en) 1981-07-09
DE2851608C2 (fr) 1987-09-03
US4190901A (en) 1980-02-26
GB2009517B (en) 1982-02-10
CA1119314A (fr) 1982-03-02
DE2851608A1 (de) 1979-06-07
JPS54151329A (en) 1979-11-28
YU271878A (en) 1982-10-31
FR2410937B1 (fr) 1988-03-25
GB2009517A (en) 1979-06-13

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Legal Events

Date Code Title Description
ST Notification of lapse