FR2399125A1 - Integrated semiconductor data storage system - has capacitors in substrate region, and zone of second conductivity whose PN junction is blocked by bias voltage - Google Patents

Integrated semiconductor data storage system - has capacitors in substrate region, and zone of second conductivity whose PN junction is blocked by bias voltage

Info

Publication number
FR2399125A1
FR2399125A1 FR7822121A FR7822121A FR2399125A1 FR 2399125 A1 FR2399125 A1 FR 2399125A1 FR 7822121 A FR7822121 A FR 7822121A FR 7822121 A FR7822121 A FR 7822121A FR 2399125 A1 FR2399125 A1 FR 2399125A1
Authority
FR
France
Prior art keywords
zone
junction
bias voltage
capacitors
blocked
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7822121A
Other languages
French (fr)
Other versions
FR2399125B1 (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of FR2399125A1 publication Critical patent/FR2399125A1/en
Application granted granted Critical
Publication of FR2399125B1 publication Critical patent/FR2399125B1/fr
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/761PN junctions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107Substrate region of field-effect devices
    • H01L29/1075Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1087Substrate region of field-effect devices of field-effect transistors with insulated gate characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/30DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Abstract

The store has a semiconductor substrate which is of a first conduction type. There are several storage capacitors for charges corresponding to the signals to be stored, with each capacitor having a first zone which can store a charge in the substrates. There is a region in the substrate, in which the capacitor are produced close to each other. There is a second zone of the second conduction type opposite to that of the substrate. It is outside the above region and close to at least one of the first zones. A first device applies a bias voltage to the second zone, so that a p-n junction between the second zones and substrate is biased in the blocking sense.
FR7822121A 1977-07-28 1978-07-26 Integrated semiconductor data storage system - has capacitors in substrate region, and zone of second conductivity whose PN junction is blocked by bias voltage Granted FR2399125A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP52090864A JPS5819141B2 (en) 1977-07-28 1977-07-28 semiconductor equipment

Publications (2)

Publication Number Publication Date
FR2399125A1 true FR2399125A1 (en) 1979-02-23
FR2399125B1 FR2399125B1 (en) 1982-11-12

Family

ID=14010403

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7822121A Granted FR2399125A1 (en) 1977-07-28 1978-07-26 Integrated semiconductor data storage system - has capacitors in substrate region, and zone of second conductivity whose PN junction is blocked by bias voltage

Country Status (2)

Country Link
JP (1) JPS5819141B2 (en)
FR (1) FR2399125A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0770346A1 (en) 1995-10-27 1997-05-02 Le Crochet "X" Anglo-French Trading Co. Improved hook for a picture rail

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3387286A (en) * 1967-07-14 1968-06-04 Ibm Field-effect transistor memory
FR2336801A1 (en) * 1975-12-26 1977-07-22 Tokyo Shibaura Electric Co INTEGRATED CIRCUIT

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3387286A (en) * 1967-07-14 1968-06-04 Ibm Field-effect transistor memory
FR2336801A1 (en) * 1975-12-26 1977-07-22 Tokyo Shibaura Electric Co INTEGRATED CIRCUIT

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
NV700/74 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0770346A1 (en) 1995-10-27 1997-05-02 Le Crochet "X" Anglo-French Trading Co. Improved hook for a picture rail

Also Published As

Publication number Publication date
DE2832764C2 (en) 1982-04-15
DE2832764A1 (en) 1979-02-01
FR2399125B1 (en) 1982-11-12
JPS5819141B2 (en) 1983-04-16
JPS5425181A (en) 1979-02-24

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