DE2832764C2 - Integrated semiconductor memory device - Google Patents

Description

The invention relates to an integrated semiconductor memory device, and more particularly to a memory device, in which a plurality of memory cells with storage capacitors on a semiconductor substrate are integrated.

An integrated semiconductor memory is known and widely used because of its high integration density, in which a plurality of memory cells are integrated in a semiconductor substrate, each of which consists of one Storage capacitor with metal-insulator-semiconductor (MIS) structure and a transmission gate made of one MIS field effect transistor (FET) is made. This memory device is generally called a single transistor / cell memory device designated. The storage capacitor is between an electrode metal layer, which is on an insulating film on the surface of the Semiconductor substrate is formed, and an inversion layer formed on the semiconductor substrate surface is induced under the electrode. The transfer gate controls the transfer of charge between the Storage capacitor and a bit line by means of a signal emitted by a word line.

The charges stored in the storage capacitor according to the information to be stored are reduced over time by leakage current. Therefore, to keep the information, an operation is namely a refresh operation usually on a storage capacitor in which charges are stored are carried out by taking charges from an outer circle at any given period accordingly are given to the charges stored in the storage capacitor. It is desirable this Set the refresh period as long as possible. An integrated semiconductor memory device having a plurality of Memory cells in a semiconductor substrate must have such a charge storage characteristic that The storage capacitors of all memory cells do not have significant charges within the refresh period lose.

These different charge losses mean that the presence or absence of charges in the storage capacitor can no longer be differentiated, ie correct information reading is also not possible by refreshing it.
A large-sized integrated semiconductor memory device has a memory cell array in which several tens of thousands of memory cells are arranged in a partial area of a semiconductor substrate in the form of a matrix. If only one storage cell has a defective charge storage characteristic, namely if only one storage cell cannot hold the necessary amount of charge during the refresh period, the storage device with a large capacity can no longer be used. An average charge holding period of a storage capacitor is generally noticeably long, but the refreshing period is set to be short. For example, when the charge holding period is 1 to 10 seconds, the refresh period is set to a few milliseconds, for example. However, a part of the memory cells have very short charge holding periods compared with an average value, and the proportion of defective memory devices among all the memory devices manufactured is remarkably large.

To the capacity in order to improve

so to enlarge the charge storage characteristics of all storage capacitors, it is necessary to use the To make the size of the storage capacitor large, which has disadvantages such as deterioration the integration density of the storage device.

On the other hand, it is desirable to use the storage capacitors from the viewpoint of prevention unexpected defective refresh cells and the increase in the integration density are the same To give charge storage characteristics.

The invention is based on the object of creating an integrated semiconductor memory device, which does not easily lose the stored information and which has a high integration density.

In the case of the device of the type mentioned at the outset, this object is achieved with the aid of the in the characterizing part of claim 1 specified features solved. Advantageous refinements and developments of device according to the invention are the subclaims

to be found.

The memory device according to the invention should preferably have a significantly long refresh period can adjust.

In the case of the storage device according to the invention, all storage capacitors should preferably also be used can store the necessary charges within the refreshing period.

The semiconductor integrated memory device according to the invention has a high integration density and has a large number of storage capacitors small dimensions.

The invention can also prevent excessive leakage current from flowing into a part under many storage capacitors.

The integrated semiconductor memory device according to the invention also has the same charge storage characteristic on.

In the semiconductor integrated memory device according to the invention, there are a plurality of storage capacitors arranged side by side in the semiconductor substrate in order to achieve a high integration density. Charges corresponding to the information to be stored are generally in the inversion layer of the substrate area, which forms the storage capacitors, but this inversion layer can can also be replaced with a region which is formed inside the substrate and which has a conductivity type that is the same as the conductivity type of the substrate is opposite. This storage capacitor forms the storage cell in pairs with the transition gate, yes controls loading and unloading. Usually, a plurality of memory cells are in the form of a matrix and thus a memory cell array is formed on the substrate.

It has been found that in such an integrated semiconductor memory device, a storage capacitor mounted along the outside of the memory cell array has a very short charge storage period in comparison with a storage capacitor ao provided inside the array. The storage capacitors provided at the edge of the arrangement tend to generate comparatively significant leakage currents for the following reasons:

In the memory cell arrangement, storage capacitors are from adjacent storage capacitors surrounded, while the storage capacitors arranged at the edge of the arrangement to dtm area ways in which functional elements are not formed. On the outside of the inversion layer or the Area of a conductivity type, which is intended as the charge storage area of the arrangement Storage capacitor acts, the substrate area is with a conductivity type that of the i ^ charge storage area opposite is provided. In the substrate area, thermal carriers will always be generated spontaneously in a constant amount. The flow of these carriers into the charge storage area means the generation of a leakage current. The leakage current in the charge storage area results from the influx of minority carriers along the substrate surface. Since the on the edge of the arrangement intended charge storage area to the outer substrate area, which is wider than the internal Substrate area between storage areas in the arrangement is removed, the number of is spontaneous generated carriers which flow in along the surface of the substrate region are also noticeably large. In addition Charge storage area, which is provided within the arrangement, flows spontaneously in the carrier Substrate area are generated between adjacent charge storage areas, only to a lesser extent Lot. Since the inner substrate area present between adjacent charge storage areas is narrow, consequently, the number of carriers spontaneously generated therein is small as a whole. Thus, the on The charge storage area provided at the edge of the arrangement causes excessive leakage current. In particular is the leakage current in the charge storage areas provided at the corners of the arrangement is very substantial.

In addition to the accidental influx of thermally generated beams, there are other factors, soft generate a large leakage current in the charge storage area on the periphery of the arrangement is provided. One of the essential factors is a conductive layer that is on top of the An insulating layer is formed, which covers the substrate, and which extends to the outside of the area of the Memory cell array extends. Such a conductive layer is essential for controlling the memory cells necessary, which are selected by a peripheral circuit that is external to the memory cell array is provided. A voltage can be applied to this conductive layer which is sufficient to create a depletion layer on the surface of the substrate under the conductive layer. If the Depletion layer occupies a large area in contact with the charge storage area, the in the substrate spontaneously generated minority carriers are concentrated on this surface and flow to the Charge storage area, which creates excessive leakage current across the depletion layer. In In the vicinity of the memory cell arrangement, however, the conductive layer extends over the substrate area on the outside of an arrangement on the other side of the storage capacitors or next to the area in front of it remotely via the storage capacitors. Therefore, the depletion layer can extend over a large area extending along the surface under the conductive layer from the charge storage region. For these reasons the charge storage area can generate excessive leakage current. Even if a depletion layer is not generated, a voltage is also applied to the conductive layer so that in minority carriers generated on the substrate in the substrate surface immediately below the conductive layer are concentrated, and a large amount of minority carriers flow into the charge storage area along the area under the conductive layer.

According to the invention, an excessive leakage current occurs at the edge of the memory cell array provided charge storage area is controlled by the area having a conductivity type that that of the substrate is opposite, and that is provided in the substrate near the outside of the assembly is. This leak suppressing area is formed in such a way that it extends to the inside of the Surface of the substrate extends, which allows the application of such a potential that a bias in the reverse direction is applied to the PN junction between the substrate and this region. This has this area has the function of the carriers generated in the substrate, in particular minority carriers, the cause the leakage current to be absorbed. To prevent excessive leakage current, the

Leak suppression area can be arranged so that it is not more than 15 μ from the charge storage area away. In order to reduce the leakage current at the charge storage areas on the edge and on the inside of the To make memory cell arrays the same, it is desirable to reduce the distance between the leakage suppressing area and the adjacent charge storage area compared to the distance between adjacent charge storage areas on the inside of the arrangement, mostly equal to or smaller do.

On the other hand, the leak suppressing area should be arranged so that it is electrically from the Charge storage area is isolated in order to protect the function of the storage capacitor from interference. There the distance between adjacent charge storage areas in a storage device with high Integration density is made as small as possible, it is desirable to reduce the distance between the leakage suppression area and to make the charge storage area adjacent thereto as small as mentioned above.

The leak suppression area according to the invention is particularly effective when it is along the The outside of the storage capacitors is arranged, which are located at the corners of the memory cell arrangement where a leakage current occurs particularly easily. In addition, it is also effective in the Provide a leak suppressing area in the area immediately below the conductive layer corresponding to the Area of the arrangement is adjacent. to avoid the generation of excessive leakage current due to the To prevent depletion layer that is formed under the conductive layer that extends from the Inside of the area of the arrangement extends outwards. It is also effective to suppress the leakage area to be provided on the outside of the arrangement near at least one charge storage area, which is within the scope of the memory cell array, but it is even more desirable to use the To arrange leak suppression area so that it surrounds the memory cell array.

A potential applied to the leakage suppression region results in a reverse bias of the PN junction. which is formed between the substrate and the leak suppressing region. In a practical MIS memory device, the drain supply voltage can be applied directly to the leak suppression region. In the case of a MIS memory device in which a different potential with respect to ground w applied to the substrate area: approx. ie a so-called rear gate bias voltage is applied to the area, the earth potential can also be applied to the leakage suppression area.

The invention is illustrated by way of example with reference to the drawing described in which are

F i g. 1 is a Tefl cross section of the memory device according to the invention,

F i g. 2 shows an equivalent circuit of the circuit shown in FIG. 1 memory cell shown,

F i g. 3 is an illustration of an example of an overall arrangement of an integrated semiconductor memory device; in which the invention is applied,

Fig. 4 is a partial plan view of the arrangement of the Storage device of the invention,

F i g. Fig. 5 is a partial plan view showing the arrangement of the memory device of another embodiment the invention,

Fig. 6 is a partial plan view showing the arrangement of the memory device of another embodiment the invention,

F i g. 7 is a partial enlargement of FIG. 4,

Fig. 3 is a section along the line X-X 'in Fig. 7 and 9 to 13 cross sections of substrates for Explanation of the successive steps of the manufacturing method of the memory device of FIG

ίο F i g. 8 illustrated embodiment of the invention.

F i g. 1 shows memory cells which are located at the corners of the memory cell array. The area of the P-type silicon substrate is covered by the field insulating film 2 made of silicon oxide. The thickness of the Field insulating film 2 is generally about 1 μm. the Memory line looks from the transfer gate i'ö and the storage capacitor 20. In the area in which the functional element that forms the storage cells, is arranged, a window is formed in the field insulating film 2 and a thin insulating film 2 'made of silicon oxide is formed in it. The N areas 3 and 4 are the functional element that forms the transmission gate 10 are provided for source and drain in the P-type sub-substrate and the gate electrode 5 is provided on the insulating film 2 '. These Elements form an insulated gate field effect transistor (IG FET) for the transmission gate 10. The Electrode 6 for forming the storage capacitor 20 is placed on the insulating film 2 'near the transfer gate 10 formed. The thickness of the insulating film 2 'is

usually about 1000 Å and as electrodes 5 and 6 polycrystalline silicon layers can be used. A voltage higher than the Invasion Threshold level is, usually a voltage of the drain power supply, the electrode 6 for the Storage capacitor supplied, whereby the N inversion layer 21 on the substrate surface of the area in the storage capacitor 20 is induced. Charges in accordance with the information to be stored are entered via the transmission gate 10 and stored in the inversion layer 21.

The insulating film 7 covers the functional element and the electrode 8. which are in ohmic contact with the N region 3 stands above the electrode window formed in the insulating films 2 and 7 on the insulating film 7 The insulating film 7 can for example consist of phosphosilicate glass (PSG) in a thickness of about 1 μ and the electrode 8 can be formed by an aluminum layer with a thickness of, for example, 0.5 to 1 μ. The insulating layer 7 extends on the substrate 1 to the outside of the memory cell arrangement, which is not shown in FIG F i g. 1 is shown. The electrode 8 can also extend on the insulating film 7 to the outside of the memory cell arrangement extend.

According to the equivalent circuit diagram of FIG. 2, the transfer gate 10 is connected to the bit line B , which consists of the electrode 8, while the gate electrode 5 forms the word line W. The transfer gate 10 'transfers the charges on the bit line B into the storage capacitor 20' in accordance with a signal voltage given to the gate electrode 5 via the word line W , or outputs the charges in the storage capacitor 20 'to the bit line B , thereby controlling charging and discharging of the storage capacitor 20'.

In the memory cell array are memory cells, each of which is composed of a transmission port 10 and a storage capacitor 20, see Fig. 1, - arranged side by side in a matrix The distance

between adjacent charge storage areas, namely the inversion layers 21, is 5 μ or less for a high density memory device. The thermally in the P-substrate 1 generated carriers, in particular electrons of the minority carriers, are therefore dispersed in the plurality Inversion layers absorbed, with the result that in the inversion layer 21 there is no large leakage current can occur. In addition, if the depletion layer is generated on the substrate surface when a Voltage is applied to the electrode 8 is a divergence of the depletion layer to a narrow one Limited area between memory cells. Therefore, excessive leakage of the inversion layer does not occur 21 on.

On the contrary, a large number of thermally flow in the substrate on the outside of the arrangement generated electrons concentrically in the inversion layer 21 at the edge of the arrangement along the Substrate area, which leads to a noticeable leakage current in the inversion layer 21. When the electrode 8 extends to the outside of the assembly, a large depletion layer may extend to the outside of the Arrangement of the inversion layer 21 at the edge of the arrangement on the substrate surface along the electrode 8 extend. In this case, a noticeable leakage current may also flow to the inversion layer 21 at the Edge of the assembly due to a large leakage current due to the concentration of minority carriers in the Depletion layer are given. Such a large leakage current can also be caused by the action of the electrons are generated, which are minority carriers, which are in the substrate surface immediately below the electrode 8 are stored.

According to the invention, the above-mentioned excessive leakage current through the N region 9 is prevented, which is provided on the outside along the edge of the memory cell array. To the N region 9 is applied a positive potential relative to the substrate, creating the PN junction between the P substrate 1 and the N region is reverse biased. With such a storage device, when -5 V is applied to the P-substrate as a reverse bias, the grounded potential are applied to the N region 9, see Fig. 1. When the P substrate 1 is grounded, a voltage should can be applied to the N-area 9 with a positive value. It is desirable the supply voltage to be applied directly to the N-area 9 in order to achieve constant leakage suppression.

The N region 9, to which the particular potential is applied, absorbs electrons that are in the P-substrate 1 can be generated on the outside of the memory cell array, resulting in an excessive Leakage current of the inversion layer 21 prevents. In addition, the N region 9 interrupts minority carriers flow along the depletion layer, which is directed to the substrate surface by applying a voltage to the Electrode 8 can extend and suppress generation of excessive leakage current.

The leak suppressing area 9 is so arranged be that it is a distance of more than 15 μ from the inversion layer 21, i.e. the charge storage area, has as carriers that are between the leak suppression area 9 and the inversion layer 21 or the depletion layer extending therein are generated, become the cause of a leakage current. It is Desirably, the distance between the N region 9 and the inversion layer 21 is equal to the distance should be between adjacent inversion layers 21 in the memory cell arrangement, for example 5 μ or less.

The N inversion layer 21 can be replaced with the N region formed by introducing an N impurity is formed. In such a case, too, the corner suppressing area 9 is as effective as the above described case. The transmission gate may take a different form than that shown in FIG. 1 is shown. For example, if the electrodes 5 and 6 are arranged sufficiently close, the N region 4 can be omitted will.

According to FIG. 3, which shows, as an embodiment of the invention, the memory cell array and the peripheral Circles for driving the circuit shown are two on the main surface of the semiconductor substrate 30 Memory cell arrays 31 and 32 arranged. Each of the memory cell arrays 31 and 32 includes one large number of memory cells, which are each arranged in a matrix. To the memory cell arrays 31 and 32, the peripheral circles are provided, consisting of an input and output circuit 33, an input and Output controller 34, address buffers 35 and 36, a clock generator 37, a row decoder 38, column decoders 39 and 40 and sense amplifiers 41 to 44 exist. The operation and circuit configuration of the memory cell array and the peripheral circles correspond to those in a known memory device.

FIG. 4, which shows an enlarged part of a corner of the memory cell array in FIG. 3, will be described with reference to FIG. The P semiconductor substrate 101 is covered by the field insulating film 102. In the area in which the memory cells are to be formed, a window is provided in the field insulating film 102, while a thin insulating film 102 'is formed in the window. The electrode 105 forming the word line extends to and crosses the thin insulating film 102 'in each memory cell, and functions as a gate electrode of the transfer gate in each memory cell. The electrode 106 for the storage capacitor also extends as far as and crosses the area in which the inversion layer for the storage capacitor is to be formed in each memory cell arrangement, and is connected in a desired manner to the drain voltage source VDD. The electrodes 105 and 106 are formed by a polycrystalline silicon layer. In the P substrate 101 under the thin insulating film 102 'except for the area masked by the electrodes 105 and 106 made of polycrystalline silicon, the N areas are formed. In this way, the transmission gate 110 and the storage capacitor 120 are formed, and each memory cell is paired with an adjacent memory cell in the form of a symmetrical pattern. In Fig. 4 six pairs of memory cells are shown, namely a total of 12 memory cells.

On the substrate 101, an insulating film (not shown) such as a PSG film is formed which covers electrodes 105 and 106 and is in the N region in the middle of each memory cell pair Electrode windows 130 formed on the PSG film and the thin insulating film 102 '. The aluminum electrode 108, which forms the bit line, extends on the PSG film and is in ohmic contact with the N region across the electrode window 130.

■ ü S si

According to the invention, on the outside of the memory cell array, the N region 109 is formed so as to extend into the substrate 101 from the surface thereof. This N region 109 surrounds the memory cell arrangement. The space between the inversion layer induced under the insulating thin film 102 'under the electrode 106 and the N region 109 in the memory cell provided around the memory cell array is equal to the space between adjacent inversion layers, namely, the distance between adjacent ones thin insulating films 102 '. For example, the space is 5 μ. The insulating film on the N region 109 is provided with an electrode window 131 and an electrode 132 which is in ohmic contact with the N region formed through the electrode window 131. The electrode 132 is connected to the terminal of the drain voltage source VDD , which outputs a positive voltage. On the other hand, the ground potential or a negative gate bias potential is applied to the substrate 101 in the reverse direction, causing the N region 109 to be reverse biased toward the P substrate 101. In this way, the N region 109 prevents spontaneously generated electrons from flowing into the array from the outside of the memory cell array along the face of the P substrate 101. The storage capacitors provided at the edge of the arrangement also have very good charge storage properties like those within the arrangement.

In Fig. 5 is part of the corner of the in FIG. 3 shown memory cell arrangements 31 and 32 is shown. The design of the memory cell arrangement corresponds to that in FIG. 4 shown device. In the memory cell device of FIG. 5, the electrode 51 extends. which consists of polycrystalline silicon to form the storage capacitor, to the outside of the memory cell arrangement. On the outside of the memory cell arrangement, the wiring layer 152, which consists of aluminum, is connected to the electrode 151 for the storage capacitor via the contact windows 153 formed in the PSG film. The wiring layer 152 is connected to the terminal of the drain voltage source, and thereby the drain supply voltage VDD, which is suitable for inducing the inversion layer for charge storage under the insulating thin film 102 'in each storage cell, is supplied to the electrode 151 for the storage capacitor during operation of the storage device

According to the invention, the N-area 154 is provided on the surface of the P-substrate 101 under the electrode 151, which extends to the outside of the assembly The aluminum wiring layer 152, which is connected to the drain supply voltage connection VDD , is in ohmic contact with each N-area 154 via the contact window 155 which is formed in the insulating layer at the N-area 154 As a result, the PN junction between the N region 154 and the P substrate 101 is reverse biased during operation. The ^j N region 154 therefore functions to cause the electrodes to flow into the inner part of the outside of the device the area of the substrate 101 under the electrode 151.

According to FIG. 6, the design of which corresponds to the memory cell arrangement of the device according to FIG. 4, the N-region 161 is provided on the outside of the memory cell arrangement and extends into the substrate 10t from the surface. The aluminum wiring layer 162 connected to the drain supply voltage terminal VDD is in ohmic contact with the N region 161 via the electrode window 163 formed in the insulating film on the N region 161. This N-area 161 operates during the operation of the memory cell in such a way that a leakage current of the storage capacitor, which can occur at the corner of the memory cell arrangement, is suppressed. This storage device differs from that in FIG. 4 in that the N region for suppressing the leakage current does not completely surround the cell arrangement. The device of FIG. 4 is more advantageous under the weighting point of suppressing excessive leakage for all storage capacitors provided on the edge of the cell arrangement. However, the N area functioning as the functional element of the memory device often extends to the outside from the inside of the cell array, and in this case, the N area for leakage suppression cannot surround the cell assembly because the N area for cell suppression is separated from the area which works as a functional element of the storage device. In such a case, the invention can be practiced as shown in FIG. 6 is shown.

F i g. 7 shows an enlarged view of the memory cell pair at the corner of the memory cell array in the training shown in Figure 4 and a part of the leak suppressing area 109.

Referring to Fig. 8, the N regions 103 and 104 for forming the transfer gate are on the P silicon substrate 101 is formed and the P region 180 with a comparatively high concentration of impurities is on the surface of the Substrate 101 is provided under a thick field insulating film 102, which is not shown in Fig. 4. Of the P-region 180 acts as a channel boundary region to electrically close the memory elements in the substrate separate. The N inversion layer 121, which functions as a charge storage region, is induced when a positive voltage is applied to electrode 106 during operation of the memory device.

The manufacturing steps described with reference to FIGS. 9 to 13 in FIGS. 7 and 8 The embodiment shown can also be used in the manufacture of the storage device shown in FIGS be applied.

In the first step shown in FIG. 9, a silicon nitride film 190 is formed on the surface of the P-type silicon substrate 101. This silicon nitride film 190 is deposited by a chemical vapor deposition (CVD) method and patterned to mask the memory cell area and the leakage suppression area by photolithography. The impurity concentration of the P-type silicon substrate 101 is in the range of 10 ¹⁴ to 10 ¹⁵ c ^-3 . The thickness of the silicon nitride film 190 is about 1000 Å. Here, boron ions [B ⁺ ] are implanted into the substrate 101 using the silicon nitride film as a mask, and then the substrate 101 is subjected to a thermal oxidation treatment. As a result, the field silicon dioxide film 102 is formed on the surface of the substrate 101 where it is not masked by the silicon nitride film 190

Field oxide film 102 , the P-region 180 with a comparatively high concentration of impurities is formed by means of the boron ion implantation for the channel trimming. The thermal oxidation conditions are set so that the thickness of the field oxide film 102 becomes about 8000 Å.

Then, the silicon nitride film 190 is removed by etching and the substrate 101 is subjected to thermal oxidation again. As a result, the Siliziumdioxydfilm 102 'having a thickness of 1000 _{Å,) 0} see Fig. 11, formed on the substrate surface in the region which is not masked by the field oxide film 102.

The polycrystalline silicon is then deposited to a thickness of 4000 Å on the substrate by chemical vapor deposition. Referring to Fig. 12, this polycrystalline silicon layer is left in the form of the gate electrode 105 of the IG FET and the storage capacitor electrode 106 which constitute the transfer gate by using photolithography. Then, an etching treatment of silicon oxide is carried out on the substrate in such a sufficient manner that the silicon oxide is removed from the substrate to a thickness of 1000 Å. During this etching treatment, the polycrystalline silicon layers 105 and 106 act as a mask and only the exposed part of the thin silicon oxide film 102 ' is removed. As a result, the surface of the substrate 101 is exposed in the area that is not deposited by the polycrystalline silicon layers 105 and 106 or the field oxide film 102 . At this time, the N impurity is diffused into the substrate 101. For this foreign matter diffusion, phosphorus diffusion using POCI3 can be applied. In addition, a PSG film formed on the substrate by chemical vapor deposition can be used as a diffusion source. The N-impurity is introduced into the exposed area of the substrate in a concentration of 10 ²¹¹ CHi - 'or more.

13, the substrate 101 is coated with a PSG film 107 to a thickness of 1μ which is deposited by chemical vapor. This PSG film 107 is provided to separate the aluminum wiring layer and the polycrystalline silicon layers 105 and 106 formed thereon, and can also be used as a phosphorus diffusion source. By diffusing the N impurity, the N regions 103 and 104 and the leak suppressing N region 109, which constitute the transfer gate, are formed on the substrate. The foreign matter is also introduced into the polycrystalline silicon layers! 05 and! 06 at the same time with the formation of these N-regions, and as a result, the electrodes 105 and 106 become low in conductivity.

After the electrode window is formed on the PSG film by photolithography, the aluminum diffusion layer 108 shown in Figures 7 and 8 is formed. The aluminum wiring layer 108 can be formed by vacuum evaporation of aluminum or photolithography. An electrode window is formed in a portion (not shown) of the PSG film 107 formed on the leak suppressing N-area 109 , and the aluminum wiring layer for supplying the bias voltage that makes η ohmic contact with the N-area becomes formed at this step.

The invention can also be applied to a P-channel memory device using an N-type semiconductor substrate can be applied, in which case the leakage suppression region is formed by the P region with a potential applied thereto having negative polarity relative to the N substrate.

In addition 7 sheets of drawings

Claims (7)

Patent claims: 1. Integrated semiconductor memory device with a semiconductor substrate of a first conductivity type, with a plurality of storage capacitors for storing charges to be stored accordingly, each storage capacitor having a first area that can store a charge in the substrate, and with a region in the substrate in which the storage capacitors are arranged close to one another, characterized by a second region (9, 109, 154, 161) of a second conductivity type (n ) which is opposite to the first conductivity type (p) of the substrate (1, 101), the second region outside the region (20; 120) of the storage capacitors and near at least one of the first regions (21; 121), and by means for applying a bias potential to the second region in such a way that a PN junction between the second region and the substrate is reverse biased. 2. Apparatus according to claim 1, characterized in that the second area is arranged so that its distance from the first area is not more than 15 μ. 3. Apparatus according to claim 1, characterized in that the second area is the area with the Surrounds storage capacitors. 4. Apparatus according to claim 1, characterized in that the first area is the second Has conductivity type. 5. The device according to claim 1, characterized in that the first area by a Inversion layer is formed. 6. Apparatus according to claim 1, characterized in that each storage capacitor further an insulating film covering the substrate and a conductive layer on the insulating film, the is arranged in the first region. 7. Apparatus according to claim 6, characterized by a second device for applying a Voltage to the conductive layer, so that an inversion layer, which acts as the first area, on an area of the substrate under the conductive layer.