FR2399097A1 - Element de memoire - Google Patents
Element de memoireInfo
- Publication number
- FR2399097A1 FR2399097A1 FR7820291A FR7820291A FR2399097A1 FR 2399097 A1 FR2399097 A1 FR 2399097A1 FR 7820291 A FR7820291 A FR 7820291A FR 7820291 A FR7820291 A FR 7820291A FR 2399097 A1 FR2399097 A1 FR 2399097A1
- Authority
- FR
- France
- Prior art keywords
- memory element
- electrode
- conductor
- substrate
- isolated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 230000015654 memory Effects 0.000 title abstract 4
- 239000004020 conductor Substances 0.000 abstract 2
- 239000004065 semiconductor Substances 0.000 abstract 2
- 239000000758 substrate Substances 0.000 abstract 2
- 230000005669 field effect Effects 0.000 abstract 1
- 230000003068 static effect Effects 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/35—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices with charge storage in a depletion layer, e.g. charge coupled devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
- G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Memories (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
L'invention concerne un élément de mémoire. Dans cet élément de mémoire, qui comporte une région de source 2 raccordée à un conducteur de bits BL, une région de drain 3 et une porte 4 d'un transistor à effet de champ T raccordé à un conducteur de mots WL, ainsi qu'une électrode de mémorisation 8 au-dessus d'un substrat semi-conducteur 1, il est prévu une électrode 11, 11a isolée et à potentiel libre, au-dessous de laquelle le substrat 1 est dopé de façon supplémentaire, et une électrode de débordement commandable 13. Application notamment aux mémoires numériques statiques à semi-conducteurs.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19772734354 DE2734354A1 (de) | 1977-07-29 | 1977-07-29 | Speicherelement |
Publications (1)
Publication Number | Publication Date |
---|---|
FR2399097A1 true FR2399097A1 (fr) | 1979-02-23 |
Family
ID=6015208
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR7820291A Withdrawn FR2399097A1 (fr) | 1977-07-29 | 1978-07-07 | Element de memoire |
Country Status (9)
Country | Link |
---|---|
US (1) | US4224635A (fr) |
JP (1) | JPS5426671A (fr) |
BE (1) | BE869373A (fr) |
CA (1) | CA1124858A (fr) |
DE (1) | DE2734354A1 (fr) |
FR (1) | FR2399097A1 (fr) |
GB (1) | GB2001801B (fr) |
IT (1) | IT1097163B (fr) |
NL (1) | NL7808029A (fr) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5593252A (en) * | 1979-01-05 | 1980-07-15 | Mitsubishi Electric Corp | Substrate potential generating apparatus |
DE3235835A1 (de) * | 1982-09-28 | 1984-03-29 | Siemens AG, 1000 Berlin und 8000 München | Halbleiter-speicherzelle |
US5244825A (en) * | 1983-02-23 | 1993-09-14 | Texas Instruments Incorporated | DRAM process with improved poly-to-poly capacitor |
JPS59171279U (ja) * | 1983-04-30 | 1984-11-15 | 三和テッキ株式会社 | 速度感応型慣性制振装置 |
US4922312A (en) * | 1986-04-30 | 1990-05-01 | Texas Instruments Incorporated | DRAM process with improved polysilicon-to-polysilicon capacitor and the capacitor |
US5003361A (en) * | 1987-08-31 | 1991-03-26 | At&T Bell Laboratories | Active dynamic memory cell |
JP2825135B2 (ja) * | 1990-03-06 | 1998-11-18 | 富士通株式会社 | 半導体記憶装置及びその情報書込読出消去方法 |
US7064034B2 (en) * | 2002-07-02 | 2006-06-20 | Sandisk Corporation | Technique for fabricating logic elements using multiple gate layers |
US7700984B2 (en) * | 2005-05-20 | 2010-04-20 | Semiconductor Energy Laboratory Co., Ltd | Semiconductor device including memory cell |
-
1977
- 1977-07-29 DE DE19772734354 patent/DE2734354A1/de not_active Withdrawn
-
1978
- 1978-07-07 FR FR7820291A patent/FR2399097A1/fr not_active Withdrawn
- 1978-07-07 US US05/922,747 patent/US4224635A/en not_active Expired - Lifetime
- 1978-07-17 IT IT25762/78A patent/IT1097163B/it active
- 1978-07-26 JP JP9138578A patent/JPS5426671A/ja active Pending
- 1978-07-28 CA CA308,358A patent/CA1124858A/fr not_active Expired
- 1978-07-28 BE BE189588A patent/BE869373A/fr unknown
- 1978-07-28 GB GB787831479A patent/GB2001801B/en not_active Expired
- 1978-07-28 NL NL7808029A patent/NL7808029A/xx not_active Application Discontinuation
Non-Patent Citations (2)
Title |
---|
EXBK/72 * |
EXBK/76 * |
Also Published As
Publication number | Publication date |
---|---|
NL7808029A (nl) | 1979-01-31 |
BE869373A (fr) | 1978-11-16 |
CA1124858A (fr) | 1982-06-01 |
US4224635A (en) | 1980-09-23 |
GB2001801B (en) | 1982-02-03 |
DE2734354A1 (de) | 1979-02-08 |
IT1097163B (it) | 1985-08-26 |
JPS5426671A (en) | 1979-02-28 |
GB2001801A (en) | 1979-02-07 |
IT7825762A0 (it) | 1978-07-17 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |