FR2390007A1 - - Google Patents
Info
- Publication number
- FR2390007A1 FR2390007A1 FR7810337A FR7810337A FR2390007A1 FR 2390007 A1 FR2390007 A1 FR 2390007A1 FR 7810337 A FR7810337 A FR 7810337A FR 7810337 A FR7810337 A FR 7810337A FR 2390007 A1 FR2390007 A1 FR 2390007A1
- Authority
- FR
- France
- Prior art keywords
- layer
- silicon
- depositing
- photoresist material
- protected region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Weting (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
L'invention concerne la fabrication de circuits intégrés. Le procédé consiste à : - déposer une première couche de silicium polycristallin 18 sur le substrat 1 -12; - placer sur cette premiere couche de silicium une couche de matériau photorésistant 25 présentant une configuration particulière définissant une région protégée dans la premiere couche de silicium; - retirer au moins une partie de la première couche de silicium en dehors de la région protégée; - déposer une seconde couche de silicium 20' sur la surface résultant de l'étape précédente; - retirer la couche de matériau photorésistant et la partie de la seconde couche de silicium qui se trouvait déposée dessus; et - oxyder les parties restantes de la première et de la seconde couche de silicium pour former des segments de silicium polycristallin isolés les uns des autres sans recouvrement.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US05/793,217 US4123300A (en) | 1977-05-02 | 1977-05-02 | Integrated circuit process utilizing lift-off techniques |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2390007A1 true FR2390007A1 (fr) | 1978-12-01 |
FR2390007B1 FR2390007B1 (fr) | 1982-05-14 |
Family
ID=25159410
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR7810337A Expired FR2390007B1 (fr) | 1977-05-02 | 1978-03-31 |
Country Status (8)
Country | Link |
---|---|
US (1) | US4123300A (fr) |
JP (1) | JPS5856267B2 (fr) |
DE (1) | DE2818525A1 (fr) |
FR (1) | FR2390007B1 (fr) |
GB (1) | GB1600048A (fr) |
IT (1) | IT1112624B (fr) |
NL (1) | NL7804517A (fr) |
SE (1) | SE7804921L (fr) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0021133A2 (fr) * | 1979-06-06 | 1981-01-07 | Kabushiki Kaisha Toshiba | Dispositif à semiconducteur comprenant une électrode d'interconnexion et procédé pour sa fabrication |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4305760A (en) * | 1978-12-22 | 1981-12-15 | Ncr Corporation | Polysilicon-to-substrate contact processing |
US4240845A (en) * | 1980-02-04 | 1980-12-23 | International Business Machines Corporation | Method of fabricating random access memory device |
JPS56116670A (en) * | 1980-02-20 | 1981-09-12 | Hitachi Ltd | Semiconductor integrated circuit device and manufacture thereof |
JPS5736844A (en) * | 1980-08-15 | 1982-02-27 | Hitachi Ltd | Semiconductor device |
US4358326A (en) * | 1980-11-03 | 1982-11-09 | International Business Machines Corporation | Epitaxially extended polycrystalline structures utilizing a predeposit of amorphous silicon with subsequent annealing |
US4814285A (en) * | 1985-09-23 | 1989-03-21 | Harris Corp. | Method for forming planarized interconnect level using selective deposition and ion implantation |
US5075817A (en) * | 1990-06-22 | 1991-12-24 | Ramtron Corporation | Trench capacitor for large scale integrated memory |
US5104822A (en) * | 1990-07-30 | 1992-04-14 | Ramtron Corporation | Method for creating self-aligned, non-patterned contact areas and stacked capacitors using the method |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2409664A1 (de) * | 1973-02-28 | 1974-10-17 | Hitachi Ltd | Ladungsueberfuehrungs-halbleiterstruktur und verfahren zu ihrer herstellung |
US3847687A (en) * | 1972-11-15 | 1974-11-12 | Motorola Inc | Methods of forming self aligned transistor structure having polycrystalline contacts |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4055885A (en) * | 1973-02-28 | 1977-11-01 | Hitachi, Ltd. | Charge transfer semiconductor device with electrodes separated by oxide region therebetween and method for fabricating the same |
-
1977
- 1977-05-02 US US05/793,217 patent/US4123300A/en not_active Expired - Lifetime
-
1978
- 1978-03-28 JP JP53034960A patent/JPS5856267B2/ja not_active Expired
- 1978-03-31 FR FR7810337A patent/FR2390007B1/fr not_active Expired
- 1978-04-19 GB GB15487/78A patent/GB1600048A/en not_active Expired
- 1978-04-27 DE DE19782818525 patent/DE2818525A1/de not_active Withdrawn
- 1978-04-27 NL NL7804517A patent/NL7804517A/xx not_active Application Discontinuation
- 1978-04-28 IT IT22794/78A patent/IT1112624B/it active
- 1978-04-28 SE SE7804921A patent/SE7804921L/xx unknown
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3847687A (en) * | 1972-11-15 | 1974-11-12 | Motorola Inc | Methods of forming self aligned transistor structure having polycrystalline contacts |
DE2409664A1 (de) * | 1973-02-28 | 1974-10-17 | Hitachi Ltd | Ladungsueberfuehrungs-halbleiterstruktur und verfahren zu ihrer herstellung |
Non-Patent Citations (2)
Title |
---|
EXBK/75 * |
EXBK/76 * |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0021133A2 (fr) * | 1979-06-06 | 1981-01-07 | Kabushiki Kaisha Toshiba | Dispositif à semiconducteur comprenant une électrode d'interconnexion et procédé pour sa fabrication |
EP0021133A3 (en) * | 1979-06-06 | 1983-07-20 | Tokyo Shibaura Denki Kabushiki Kaisha | Semiconductor device comprising an interconnection electrode and method of manufacturing the same |
Also Published As
Publication number | Publication date |
---|---|
NL7804517A (nl) | 1978-11-06 |
IT1112624B (it) | 1986-01-20 |
FR2390007B1 (fr) | 1982-05-14 |
JPS5856267B2 (ja) | 1983-12-14 |
SE7804921L (sv) | 1978-11-03 |
US4123300A (en) | 1978-10-31 |
DE2818525A1 (de) | 1978-11-09 |
JPS53136494A (en) | 1978-11-29 |
IT7822794A0 (it) | 1978-04-28 |
GB1600048A (en) | 1981-10-14 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR900002455A (ko) | 반도체 집적 소자 제조방법 | |
FR2390007A1 (fr) | ||
JPS6414949A (en) | Semiconductor device and manufacture of the same | |
KR860001476A (ko) | P-형 반도체 합금을 연속적으로 제조하는 방법 | |
EP0146427A3 (fr) | Procédé de fabrication de structures intégrées de silicium sur ilots isolés du substrat | |
KR890012364A (ko) | 복합 반도체 결정체 | |
FR2542500B1 (fr) | Procede de fabrication d'un dispositif semiconducteur du type comprenant au moins une couche de silicium deposee sur un substrat isolant | |
KR910003829A (ko) | 고전압 반도체 장치 및 제조 과정 | |
EP0170560A3 (fr) | Procédé de piégeage sur la face arrière d'un substrat en silicium | |
JPS6450439A (en) | Manufacture of semiconductor device | |
FR2384315A1 (fr) | Plate-forme comportant au moins un transducteur integre et procede de fabrication de ladite plate-forme | |
KR930008994A (ko) | 웨이퍼 결합 기술 | |
FR2543581B1 (fr) | Procede pour former une couche d'oxyde sur la surface d'un substrat en materiau semiconducteur | |
JPS5650533A (en) | Semiconductor device | |
KR880009426A (ko) | 반도체 메모리장치 및 그 제조방법 | |
EP0335632A3 (fr) | Transistor en couche mince à fort courant | |
JPS57204146A (en) | Manufacture of semiconductor device | |
JPS5740967A (en) | Integrated circuit device | |
FR2370363A1 (fr) | Condensateur de memoire | |
FR2363184A1 (fr) | Procede de fabrication d'une electrode-grille | |
KR940007528A (ko) | 단결정 산화주석을 이용한 가스센서의 제조방법 및 구조 | |
JPS6489527A (en) | Schottky diode | |
JP2615926B2 (ja) | 薄膜e▲上2▼prom | |
JPS6037163A (ja) | 半導体装置 | |
JPS5771171A (en) | Semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |