FR2385224A1 - Procede de realisation de reseaux de connexion pour circuits integres et circuits integres comportant des reseaux realises par un tel procede - Google Patents

Procede de realisation de reseaux de connexion pour circuits integres et circuits integres comportant des reseaux realises par un tel procede

Info

Publication number
FR2385224A1
FR2385224A1 FR7708999A FR7708999A FR2385224A1 FR 2385224 A1 FR2385224 A1 FR 2385224A1 FR 7708999 A FR7708999 A FR 7708999A FR 7708999 A FR7708999 A FR 7708999A FR 2385224 A1 FR2385224 A1 FR 2385224A1
Authority
FR
France
Prior art keywords
layer
sio2
block
aluminium
deposition
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7708999A
Other languages
English (en)
Other versions
FR2385224B1 (fr
Inventor
Marcel Roche
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thales SA
Original Assignee
Thomson CSF SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson CSF SA filed Critical Thomson CSF SA
Priority to FR7708999A priority Critical patent/FR2385224A1/fr
Publication of FR2385224A1 publication Critical patent/FR2385224A1/fr
Application granted granted Critical
Publication of FR2385224B1 publication Critical patent/FR2385224B1/fr
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

L'invention se rapporte aux procédés de réalisation de couches de silice de haute qualité d'adhérence pour circuits intégrés. Elle fait appel à la création, dans une gamme de températures comprises entre 200 degrés et 400 degrés , d'une couche métallique d'aluminium dopé au silicium sur une couche préalable de silice formée sur le substrat semi-conducteur, suivie d'un enlèvement de cette couche métallique par un agent chimique qui ne laisse subsister que le silicium, suivant un dépôt d'une granulométrie particulière, particulièrement apte à constituer une couche d'accrochage pour une future couche de silice. Les applications font notamment partie du domaine des circuits intégrés à réseaux d'interconnexion à multi-étages.
FR7708999A 1977-03-25 1977-03-25 Procede de realisation de reseaux de connexion pour circuits integres et circuits integres comportant des reseaux realises par un tel procede Granted FR2385224A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR7708999A FR2385224A1 (fr) 1977-03-25 1977-03-25 Procede de realisation de reseaux de connexion pour circuits integres et circuits integres comportant des reseaux realises par un tel procede

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7708999A FR2385224A1 (fr) 1977-03-25 1977-03-25 Procede de realisation de reseaux de connexion pour circuits integres et circuits integres comportant des reseaux realises par un tel procede

Publications (2)

Publication Number Publication Date
FR2385224A1 true FR2385224A1 (fr) 1978-10-20
FR2385224B1 FR2385224B1 (fr) 1980-04-18

Family

ID=9188592

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7708999A Granted FR2385224A1 (fr) 1977-03-25 1977-03-25 Procede de realisation de reseaux de connexion pour circuits integres et circuits integres comportant des reseaux realises par un tel procede

Country Status (1)

Country Link
FR (1) FR2385224A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2542922A1 (fr) * 1983-03-18 1984-09-21 Efcis Procede de fabrication de circuits integres a plusieurs couches metalliques d'interconnexion et circuit realise par ce procede

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2542922A1 (fr) * 1983-03-18 1984-09-21 Efcis Procede de fabrication de circuits integres a plusieurs couches metalliques d'interconnexion et circuit realise par ce procede

Also Published As

Publication number Publication date
FR2385224B1 (fr) 1980-04-18

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Legal Events

Date Code Title Description
ST Notification of lapse