FR2362443A1 - Circuit logique programmable - Google Patents

Circuit logique programmable

Info

Publication number
FR2362443A1
FR2362443A1 FR7724534A FR7724534A FR2362443A1 FR 2362443 A1 FR2362443 A1 FR 2362443A1 FR 7724534 A FR7724534 A FR 7724534A FR 7724534 A FR7724534 A FR 7724534A FR 2362443 A1 FR2362443 A1 FR 2362443A1
Authority
FR
France
Prior art keywords
logic circuit
programmable logic
logic
programmable
logic circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7724534A
Other languages
English (en)
Other versions
FR2362443B1 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
Western Electric Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Western Electric Co Inc filed Critical Western Electric Co Inc
Publication of FR2362443A1 publication Critical patent/FR2362443A1/fr
Application granted granted Critical
Publication of FR2362443B1 publication Critical patent/FR2362443B1/fr
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/06—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using diode elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Logic Circuits (AREA)
  • Read Only Memory (AREA)

Abstract

L'invention concerne les circuits logiques qui peuvent être programmés de façon électrique. Le circuit logique 100 comporte une matrice d'éléments logiques de mémoire 101 qui sont programmables et reprogrammables de façon électrique, et qui permettent de définir des fonctions logiques d'un grand nombre de variables. Le circuit de conduction de chaque élément de mémoire est branché en série avec une diode 102 pour supprimer les chemins parasites. Application aux circuits logiques programmables.
FR7724534A 1976-08-16 1977-08-09 Circuit logique programmable Granted FR2362443A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/714,650 US4056807A (en) 1976-08-16 1976-08-16 Electronically alterable diode logic circuit

Publications (2)

Publication Number Publication Date
FR2362443A1 true FR2362443A1 (fr) 1978-03-17
FR2362443B1 FR2362443B1 (fr) 1982-12-17

Family

ID=24870914

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7724534A Granted FR2362443A1 (fr) 1976-08-16 1977-08-09 Circuit logique programmable

Country Status (12)

Country Link
US (1) US4056807A (fr)
JP (1) JPS5323531A (fr)
BE (1) BE857711A (fr)
CA (1) CA1073057A (fr)
CH (1) CH621657A5 (fr)
DE (1) DE2735976C3 (fr)
ES (1) ES461619A1 (fr)
FR (1) FR2362443A1 (fr)
GB (1) GB1536374A (fr)
IT (1) IT1083910B (fr)
NL (1) NL7708974A (fr)
SE (1) SE414569B (fr)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4307379A (en) * 1977-11-10 1981-12-22 Raytheon Company Integrated circuit component
JPS5619651A (en) * 1979-07-26 1981-02-24 Fujitsu Ltd Semiconductor ic device
JPS5750545Y2 (fr) * 1979-10-05 1982-11-05
US4329685A (en) * 1980-06-09 1982-05-11 Burroughs Corporation Controlled selective disconnect system for wafer scale integrated circuits
US4578771A (en) * 1980-12-29 1986-03-25 International Business Machines Corporation Dynamically reprogrammable array logic system
JPS57192067A (en) * 1981-05-22 1982-11-26 Hitachi Ltd Erasable and programmable read only memory unit
US4431928A (en) * 1981-06-22 1984-02-14 Hewlett-Packard Company Symmetrical programmable logic array
US4661922A (en) * 1982-12-08 1987-04-28 American Telephone And Telegraph Company Programmed logic array with two-level control timing
US4791603A (en) * 1986-07-18 1988-12-13 Honeywell Inc. Dynamically reconfigurable array logic
US5680518A (en) * 1994-08-26 1997-10-21 Hangartner; Ricky D. Probabilistic computing methods and apparatus
US6874136B2 (en) * 2002-01-10 2005-03-29 M2000 Crossbar device with reduced parasitic capacitive loading and usage of crossbar devices in reconfigurable circuits
US7269046B2 (en) * 2005-05-10 2007-09-11 Georgia Tech Research Corporation Systems and methods for programming floating-gate transistors
WO2006124953A2 (fr) 2005-05-16 2006-11-23 Georgia Tech Research Corporation Systemes et procedes de programmation de matrices analogiques programmables par l'utilisateur de grande echelle
US8661394B1 (en) 2008-09-24 2014-02-25 Iowa State University Research Foundation, Inc. Depth-optimal mapping of logic chains in reconfigurable fabrics
US8438522B1 (en) 2008-09-24 2013-05-07 Iowa State University Research Foundation, Inc. Logic element architecture for generic logic chains in programmable devices
GB202215844D0 (en) * 2022-10-26 2022-12-07 Nicoventures Trading Ltd Computing device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3624618A (en) * 1967-12-14 1971-11-30 Sperry Rand Corp A high-speed memory array using variable threshold transistors
US3728695A (en) * 1971-10-06 1973-04-17 Intel Corp Random-access floating gate mos memory array
US3818452A (en) * 1972-04-28 1974-06-18 Gen Electric Electrically programmable logic circuits

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3623023A (en) * 1967-12-01 1971-11-23 Sperry Rand Corp Variable threshold transistor memory using pulse coincident writing
JPS4844581B1 (fr) * 1969-03-15 1973-12-25
US3686644A (en) * 1971-04-29 1972-08-22 Alton O Christensen Gated diode memory
JPS4873039A (fr) * 1971-12-20 1973-10-02
US3875567A (en) * 1971-12-29 1975-04-01 Sony Corp Memory circuit using variable threshold level field-effect device
US3877054A (en) * 1973-03-01 1975-04-08 Bell Telephone Labor Inc Semiconductor memory apparatus with a multilayer insulator contacting the semiconductor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3624618A (en) * 1967-12-14 1971-11-30 Sperry Rand Corp A high-speed memory array using variable threshold transistors
US3728695A (en) * 1971-10-06 1973-04-17 Intel Corp Random-access floating gate mos memory array
US3818452A (en) * 1972-04-28 1974-06-18 Gen Electric Electrically programmable logic circuits

Also Published As

Publication number Publication date
ES461619A1 (es) 1978-07-01
DE2735976C3 (de) 1981-12-03
JPS5323531A (en) 1978-03-04
BE857711A (fr) 1977-12-01
SE7709146L (sv) 1978-02-17
FR2362443B1 (fr) 1982-12-17
GB1536374A (en) 1978-12-20
IT1083910B (it) 1985-05-25
CH621657A5 (fr) 1981-02-13
CA1073057A (fr) 1980-03-04
DE2735976A1 (de) 1978-02-23
DE2735976B2 (de) 1981-01-08
SE414569B (sv) 1980-08-04
NL7708974A (nl) 1978-02-20
US4056807A (en) 1977-11-01

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Legal Events

Date Code Title Description
ST Notification of lapse