ES461619A1 - Perfeccionamientos en aparatos semiconductores. - Google Patents
Perfeccionamientos en aparatos semiconductores.Info
- Publication number
- ES461619A1 ES461619A1 ES461619A ES461619A ES461619A1 ES 461619 A1 ES461619 A1 ES 461619A1 ES 461619 A ES461619 A ES 461619A ES 461619 A ES461619 A ES 461619A ES 461619 A1 ES461619 A1 ES 461619A1
- Authority
- ES
- Spain
- Prior art keywords
- logic
- function
- diode
- array
- computing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/06—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using diode elements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Logic Circuits (AREA)
- Read Only Memory (AREA)
Abstract
Perfeccionamientos en aparatos semiconductores, del tipo de aparatos que comprenden una formación MxN de filas y columnas de células lógicas de 3 terminales, teniendo cada célula un primer terminal diferente de célula de corriente elevada y un segundo terminal diferente de célula de corriente elevada y un segundo terminal diferente de célula de corriente elevada, definiendo por lo tanto un trayecto de corriente elevada separado por cada célula, consistiendo cada célula esencialmente en un elemento de memoria semiconductor eléctricamente programable diferente en serie con un elemento inhibidor unidireccional separado para pasar corriente elevada a través de la célula lógica entre el primer y segundo terminales de célula de corriente elevada solamente en un sentido de dirección e inhibir la corriente en el otro sentido de dirección.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US05/714,650 US4056807A (en) | 1976-08-16 | 1976-08-16 | Electronically alterable diode logic circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
ES461619A1 true ES461619A1 (es) | 1978-07-01 |
Family
ID=24870914
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ES461619A Expired ES461619A1 (es) | 1976-08-16 | 1977-08-16 | Perfeccionamientos en aparatos semiconductores. |
Country Status (12)
Country | Link |
---|---|
US (1) | US4056807A (es) |
JP (1) | JPS5323531A (es) |
BE (1) | BE857711A (es) |
CA (1) | CA1073057A (es) |
CH (1) | CH621657A5 (es) |
DE (1) | DE2735976C3 (es) |
ES (1) | ES461619A1 (es) |
FR (1) | FR2362443A1 (es) |
GB (1) | GB1536374A (es) |
IT (1) | IT1083910B (es) |
NL (1) | NL7708974A (es) |
SE (1) | SE414569B (es) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4307379A (en) * | 1977-11-10 | 1981-12-22 | Raytheon Company | Integrated circuit component |
JPS5619651A (en) * | 1979-07-26 | 1981-02-24 | Fujitsu Ltd | Semiconductor ic device |
JPS5750545Y2 (es) * | 1979-10-05 | 1982-11-05 | ||
US4329685A (en) * | 1980-06-09 | 1982-05-11 | Burroughs Corporation | Controlled selective disconnect system for wafer scale integrated circuits |
US4578771A (en) * | 1980-12-29 | 1986-03-25 | International Business Machines Corporation | Dynamically reprogrammable array logic system |
JPS57192067A (en) * | 1981-05-22 | 1982-11-26 | Hitachi Ltd | Erasable and programmable read only memory unit |
US4431928A (en) * | 1981-06-22 | 1984-02-14 | Hewlett-Packard Company | Symmetrical programmable logic array |
US4661922A (en) * | 1982-12-08 | 1987-04-28 | American Telephone And Telegraph Company | Programmed logic array with two-level control timing |
US4791603A (en) * | 1986-07-18 | 1988-12-13 | Honeywell Inc. | Dynamically reconfigurable array logic |
US5680518A (en) * | 1994-08-26 | 1997-10-21 | Hangartner; Ricky D. | Probabilistic computing methods and apparatus |
US6874136B2 (en) * | 2002-01-10 | 2005-03-29 | M2000 | Crossbar device with reduced parasitic capacitive loading and usage of crossbar devices in reconfigurable circuits |
WO2006122271A2 (en) * | 2005-05-10 | 2006-11-16 | Georgia Tech Research Corporation | Systems and methods for programming floating-gate transistors |
WO2006124953A2 (en) | 2005-05-16 | 2006-11-23 | Georgia Tech Research Corporation | Systems and methods for programming large-scale field-programmable analog arrays |
US8438522B1 (en) | 2008-09-24 | 2013-05-07 | Iowa State University Research Foundation, Inc. | Logic element architecture for generic logic chains in programmable devices |
US8661394B1 (en) | 2008-09-24 | 2014-02-25 | Iowa State University Research Foundation, Inc. | Depth-optimal mapping of logic chains in reconfigurable fabrics |
GB202215844D0 (en) * | 2022-10-26 | 2022-12-07 | Nicoventures Trading Ltd | Computing device |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3623023A (en) * | 1967-12-01 | 1971-11-23 | Sperry Rand Corp | Variable threshold transistor memory using pulse coincident writing |
US3624618A (en) * | 1967-12-14 | 1971-11-30 | Sperry Rand Corp | A high-speed memory array using variable threshold transistors |
JPS4844581B1 (es) * | 1969-03-15 | 1973-12-25 | ||
US3686644A (en) * | 1971-04-29 | 1972-08-22 | Alton O Christensen | Gated diode memory |
US3728695A (en) * | 1971-10-06 | 1973-04-17 | Intel Corp | Random-access floating gate mos memory array |
JPS4873039A (es) * | 1971-12-20 | 1973-10-02 | ||
US3875567A (en) * | 1971-12-29 | 1975-04-01 | Sony Corp | Memory circuit using variable threshold level field-effect device |
US3818452A (en) * | 1972-04-28 | 1974-06-18 | Gen Electric | Electrically programmable logic circuits |
US3877054A (en) * | 1973-03-01 | 1975-04-08 | Bell Telephone Labor Inc | Semiconductor memory apparatus with a multilayer insulator contacting the semiconductor |
-
1976
- 1976-08-16 US US05/714,650 patent/US4056807A/en not_active Expired - Lifetime
-
1977
- 1977-06-22 CA CA281,137A patent/CA1073057A/en not_active Expired
- 1977-08-09 FR FR7724534A patent/FR2362443A1/fr active Granted
- 1977-08-10 DE DE2735976A patent/DE2735976C3/de not_active Expired
- 1977-08-11 BE BE180103A patent/BE857711A/xx not_active IP Right Cessation
- 1977-08-11 IT IT26649/77A patent/IT1083910B/it active
- 1977-08-12 SE SE7709146A patent/SE414569B/xx unknown
- 1977-08-15 CH CH996477A patent/CH621657A5/de not_active IP Right Cessation
- 1977-08-15 NL NL7708974A patent/NL7708974A/xx not_active Application Discontinuation
- 1977-08-16 GB GB34308/77A patent/GB1536374A/en not_active Expired
- 1977-08-16 JP JP9756277A patent/JPS5323531A/ja active Pending
- 1977-08-16 ES ES461619A patent/ES461619A1/es not_active Expired
Also Published As
Publication number | Publication date |
---|---|
SE414569B (sv) | 1980-08-04 |
SE7709146L (sv) | 1978-02-17 |
FR2362443A1 (fr) | 1978-03-17 |
DE2735976B2 (de) | 1981-01-08 |
GB1536374A (en) | 1978-12-20 |
IT1083910B (it) | 1985-05-25 |
FR2362443B1 (es) | 1982-12-17 |
BE857711A (fr) | 1977-12-01 |
NL7708974A (nl) | 1978-02-20 |
US4056807A (en) | 1977-11-01 |
DE2735976A1 (de) | 1978-02-23 |
CA1073057A (en) | 1980-03-04 |
CH621657A5 (es) | 1981-02-13 |
DE2735976C3 (de) | 1981-12-03 |
JPS5323531A (en) | 1978-03-04 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
FD1A | Patent lapsed |
Effective date: 19990601 |