FR2357112A1 - Trame logique programmable fonctionnant sur une base de temps partage - Google Patents
Trame logique programmable fonctionnant sur une base de temps partageInfo
- Publication number
- FR2357112A1 FR2357112A1 FR7716237A FR7716237A FR2357112A1 FR 2357112 A1 FR2357112 A1 FR 2357112A1 FR 7716237 A FR7716237 A FR 7716237A FR 7716237 A FR7716237 A FR 7716237A FR 2357112 A1 FR2357112 A1 FR 2357112A1
- Authority
- FR
- France
- Prior art keywords
- programmable logic
- time base
- shared time
- frame operating
- logic frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
- H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
- H03K19/17712—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays one of the matrices at least being reprogrammable
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
Landscapes
- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Logic Circuits (AREA)
Abstract
Circuit logique permettant la réalisation d'une ou plusieurs fonctions logiques. Des lignes d'entrée 12a-c sont reliées à la porte de transistors MNOS, la source à la sortie du circuit logique, tandis que le drain est toujours connecté, connectée de temps à autre, et jamais connecté à la masse. Quand le drain est en l'air, il n'y a pas de fonction réalisée; reliés à la masse à travers un commutateur, les transistors ne fonctionnent que si les commutateurs sont conducteurs. Utilisable dans les systèmes arithmétiques et logiques.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US70144476A | 1976-06-30 | 1976-06-30 |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2357112A1 true FR2357112A1 (fr) | 1978-01-27 |
FR2357112B1 FR2357112B1 (fr) | 1978-11-03 |
Family
ID=24817408
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR7716237A Granted FR2357112A1 (fr) | 1976-06-30 | 1977-05-23 | Trame logique programmable fonctionnant sur une base de temps partage |
Country Status (7)
Country | Link |
---|---|
US (1) | US4084152A (fr) |
JP (1) | JPS609373B2 (fr) |
CA (1) | CA1092664A (fr) |
DE (1) | DE2726094C2 (fr) |
FR (1) | FR2357112A1 (fr) |
GB (1) | GB1523859A (fr) |
IT (1) | IT1115342B (fr) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0031431A2 (fr) * | 1979-12-26 | 1981-07-08 | International Business Machines Corporation | Réseau logique séquentiel programmable |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4123669A (en) * | 1977-09-08 | 1978-10-31 | International Business Machines Corporation | Logical OR circuit for programmed logic arrays |
US4218747A (en) * | 1978-06-05 | 1980-08-19 | Fujitsu Limited | Arithmetic and logic unit using basic cells |
JPS558135A (en) * | 1978-07-04 | 1980-01-21 | Mamoru Tanaka | Rewritable programable logic array |
US4245324A (en) * | 1978-12-15 | 1981-01-13 | International Business Machines Corporation | Compact programmable logic read array having multiple outputs |
US4356413A (en) * | 1980-08-20 | 1982-10-26 | Ibm Corporation | MOSFET Convolved logic |
GB2089160B (en) * | 1980-12-05 | 1985-04-17 | Rca Corp | Programmable logic gates and networks |
US4495427A (en) * | 1980-12-05 | 1985-01-22 | Rca Corporation | Programmable logic gates and networks |
JPS57125527A (en) * | 1980-12-31 | 1982-08-04 | Ibm | Programmable lock array |
US4495590A (en) * | 1980-12-31 | 1985-01-22 | International Business Machines Corporation | PLA With time division multiplex feature for improved density |
DE3121562A1 (de) * | 1981-05-30 | 1983-01-05 | Ibm Deutschland Gmbh, 7000 Stuttgart | Programmierbare logische hochintegrierte schaltungsanordnung |
US4467439A (en) * | 1981-06-30 | 1984-08-21 | Ibm Corporation | OR Product term function in the search array of a PLA |
US4429238A (en) * | 1981-08-14 | 1984-01-31 | Bell Telephone Laboratories, Incorporated | Structured logic array |
DE3215671C2 (de) * | 1982-04-27 | 1984-05-03 | Siemens AG, 1000 Berlin und 8000 München | Programmierbare Logikanordnung |
US4661922A (en) * | 1982-12-08 | 1987-04-28 | American Telephone And Telegraph Company | Programmed logic array with two-level control timing |
US4567385A (en) * | 1983-06-22 | 1986-01-28 | Harris Corporation | Power switched logic gates |
JPS6077577A (ja) * | 1983-10-05 | 1985-05-02 | Pioneer Electronic Corp | 水平偏向位置調整回路 |
JPS6088958U (ja) * | 1983-11-24 | 1985-06-18 | 田窪 宜彦 | 手指の柔軟運動の回数測定用度数計付き回転体 |
US4554640A (en) * | 1984-01-30 | 1985-11-19 | Monolithic Memories, Inc. | Programmable array logic circuit with shared product terms |
USRE34363E (en) * | 1984-03-12 | 1993-08-31 | Xilinx, Inc. | Configurable electrical circuit having configurable logic elements and configurable interconnects |
US4761768A (en) * | 1985-03-04 | 1988-08-02 | Lattice Semiconductor Corporation | Programmable logic device |
US4675556A (en) * | 1986-06-09 | 1987-06-23 | Intel Corporation | Binomially-encoded finite state machine |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3987286A (en) * | 1974-12-20 | 1976-10-19 | International Business Machines Corporation | Time split array logic element and method of operation |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3895360A (en) * | 1974-01-29 | 1975-07-15 | Westinghouse Electric Corp | Block oriented random access memory |
US3922647A (en) * | 1974-06-03 | 1975-11-25 | Motorola Inc | External exclusive OR type circuit for inverting cell MOS RAM |
IT1042852B (it) * | 1974-09-30 | 1980-01-30 | Siemens Ag | Disposizione di circuiti logici integrata e programmabile |
US3975623A (en) * | 1974-12-30 | 1976-08-17 | Ibm Corporation | Logic array with multiple readout tables |
IT1063025B (it) * | 1975-04-29 | 1985-02-11 | Siemens Ag | Disposizione circuitale logica integrata e programmabile |
JPS51131256A (en) * | 1975-05-12 | 1976-11-15 | Tsubakimoto Chain Co | Diode matrix circuit |
-
1977
- 1977-04-04 US US05/784,744 patent/US4084152A/en not_active Expired - Lifetime
- 1977-05-18 GB GB20896/77A patent/GB1523859A/en not_active Expired
- 1977-05-20 CA CA278,844A patent/CA1092664A/fr not_active Expired
- 1977-05-23 FR FR7716237A patent/FR2357112A1/fr active Granted
- 1977-05-24 JP JP52059474A patent/JPS609373B2/ja not_active Expired
- 1977-06-07 IT IT24419/77A patent/IT1115342B/it active
- 1977-06-10 DE DE2726094A patent/DE2726094C2/de not_active Expired
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3987286A (en) * | 1974-12-20 | 1976-10-19 | International Business Machines Corporation | Time split array logic element and method of operation |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0031431A2 (fr) * | 1979-12-26 | 1981-07-08 | International Business Machines Corporation | Réseau logique séquentiel programmable |
EP0031431B1 (fr) * | 1979-12-26 | 1984-03-07 | International Business Machines Corporation | Réseau logique séquentiel programmable |
Also Published As
Publication number | Publication date |
---|---|
FR2357112B1 (fr) | 1978-11-03 |
GB1523859A (en) | 1978-09-06 |
JPS533039A (en) | 1978-01-12 |
DE2726094C2 (de) | 1983-05-26 |
US4084152A (en) | 1978-04-11 |
CA1092664A (fr) | 1980-12-30 |
JPS609373B2 (ja) | 1985-03-09 |
IT1115342B (it) | 1986-02-03 |
DE2726094A1 (de) | 1978-01-12 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |