FR2354595A1 - Systeme calculateur - Google Patents

Systeme calculateur

Info

Publication number
FR2354595A1
FR2354595A1 FR7716918A FR7716918A FR2354595A1 FR 2354595 A1 FR2354595 A1 FR 2354595A1 FR 7716918 A FR7716918 A FR 7716918A FR 7716918 A FR7716918 A FR 7716918A FR 2354595 A1 FR2354595 A1 FR 2354595A1
Authority
FR
France
Prior art keywords
signal
address
address signal
register
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
FR7716918A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Honeywell Inc
Original Assignee
Honeywell Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Inc filed Critical Honeywell Inc
Publication of FR2354595A1 publication Critical patent/FR2354595A1/fr
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/362—Software debugging
    • G06F11/3648—Software debugging using additional hardware
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/02—Input arrangements using manually operated switches, e.g. using keyboards or dials
    • G06F3/0227—Cooperation and interconnection of the input arrangement with other functional units of a computer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/26—Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements
    • G06F9/262—Arrangements for next microinstruction selection
    • G06F9/268—Microinstruction selection not based on processing results, e.g. interrupt, patch, first cycle store, diagnostic programs

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Human Computer Interaction (AREA)
  • Debugging And Monitoring (AREA)

Abstract

L'invention concerne une commande de séquence d'instructions exécutées dans un système calculateur. Ce systeme comporte une unité d'exécution d'instruction 8, une unité de mémoire 6, une unité de demande 2, un registre d'adresse en mémoire 4, des moyens pour appliquer le signal d'adresse aux unités de mémoire adressables, des moyens de contrôle de signal pour surveiller le signal d'adresse stocké dans le registre 4, des moyens de comparaison pour comparer ledit signal d'adresse avec un signal de référence numérique préajusté et des moyens 14 pour signaler une situation d'alarme en réponse au signal de sortie de comparaison. Application aux systèmes calculateurs.
FR7716918A 1976-06-08 1977-06-02 Systeme calculateur Pending FR2354595A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/693,857 US4063081A (en) 1976-06-08 1976-06-08 Computer apparatus

Publications (1)

Publication Number Publication Date
FR2354595A1 true FR2354595A1 (fr) 1978-01-06

Family

ID=24786398

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7716918A Pending FR2354595A1 (fr) 1976-06-08 1977-06-02 Systeme calculateur

Country Status (6)

Country Link
US (1) US4063081A (fr)
JP (1) JPS52149935A (fr)
CA (1) CA1069619A (fr)
DE (1) DE2725077A1 (fr)
FR (1) FR2354595A1 (fr)
GB (1) GB1584423A (fr)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4241416A (en) * 1977-07-01 1980-12-23 Systron-Donner Corporation Monitoring apparatus for processor controlled equipment
JPS5489444A (en) * 1977-12-27 1979-07-16 Fujitsu Ltd Associative memory processing system
US4258417A (en) * 1978-10-23 1981-03-24 International Business Machines Corporation System for interfacing between main store memory and a central processor
US4484307A (en) * 1979-05-09 1984-11-20 F.M.E. Corporation Electronic postage meter having improved security and fault tolerance features
DE2937777C2 (de) * 1979-09-19 1982-04-08 Ibm Deutschland Gmbh, 7000 Stuttgart Steuereinrichtung in einer elektronischen Datenverarbeitungsanlage zur Programmunterbrechung und für die Durchführung erzwungener Operationen
JPS57157359A (en) * 1981-03-25 1982-09-28 Hitachi Ltd Data processor
US4495565A (en) * 1981-11-09 1985-01-22 At&T Bell Laboratories Computer memory address matcher and process
SE430199B (sv) * 1982-02-12 1983-10-24 Ellemtel Utvecklings Ab Sett och anordning for att ge identitet at och utpeka en av ett antal funktionsenheter
JPS5927313A (ja) * 1982-08-05 1984-02-13 Fanuc Ltd 機能診断方式
US4517671A (en) * 1982-11-30 1985-05-14 Lewis James D Apparatus for operational analysis of computers
US4961067A (en) * 1986-07-28 1990-10-02 Motorola, Inc. Pattern driven interrupt in a digital data processor
US4905779A (en) * 1987-06-01 1990-03-06 Yamato Scale Company, Limited Operation condition collator and methods
DE69323076T2 (de) * 1993-07-26 1999-06-24 St Microelectronics Srl Verfahren zur Erkennung fehlerhafter Elemente eines redundanten Halbleiterspeichers
EP0778524A1 (fr) * 1995-11-17 1997-06-11 Nec Corporation Procédé et dispositif pour l'évaluation d'un programme

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3340539A (en) * 1964-10-27 1967-09-05 Anelex Corp Stored data protection system
US3422402A (en) * 1965-12-29 1969-01-14 Ibm Memory systems for using storage devices containing defective bits
US3579199A (en) * 1969-02-03 1971-05-18 Gen Motors Corp Method and apparatus for fault testing a digital computer memory
FR2109452A5 (fr) * 1970-10-16 1972-05-26 Honeywell Bull Soc Ind
US3798612A (en) * 1971-09-13 1974-03-19 Allen Bradly Co Controller programmer
US3794818A (en) * 1972-07-03 1974-02-26 Us Navy Automatic memory test and correction system
US3806716A (en) * 1972-07-17 1974-04-23 Sperry Rand Corp Parity error recovery

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
EXBK/70 *

Also Published As

Publication number Publication date
GB1584423A (en) 1981-02-11
US4063081A (en) 1977-12-13
JPS52149935A (en) 1977-12-13
DE2725077A1 (de) 1977-12-22
CA1069619A (fr) 1980-01-08

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