FR2355331A1 - Dispositif d'appel d'instructions a cadence rapide et normale dans un systeme de traitement de donnees - Google Patents

Dispositif d'appel d'instructions a cadence rapide et normale dans un systeme de traitement de donnees

Info

Publication number
FR2355331A1
FR2355331A1 FR7714007A FR7714007A FR2355331A1 FR 2355331 A1 FR2355331 A1 FR 2355331A1 FR 7714007 A FR7714007 A FR 7714007A FR 7714007 A FR7714007 A FR 7714007A FR 2355331 A1 FR2355331 A1 FR 2355331A1
Authority
FR
France
Prior art keywords
instructions
quick
data processing
processing system
call device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7714007A
Other languages
English (en)
Other versions
FR2355331B1 (fr
Inventor
Charles R Masog
Jerome U Petrie
Yasutsugu Mishima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of FR2355331A1 publication Critical patent/FR2355331A1/fr
Application granted granted Critical
Publication of FR2355331B1 publication Critical patent/FR2355331B1/fr
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G06F9/3869—Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)
  • Bus Control (AREA)

Abstract

Dispositif pour appeler les différents segments d'une instruction de mémoire. Pour les instructions d'un premier type (instructions à 1 ou 2 adresses) deux segments d'instructions (I-OP et I-Q) sont appelés durant le meme cycle CPU. Pour les instructions d'un second type (certaines instructions de commande et d'entrée/ sortie) l'appel du deuxième segment pendant le cycle est inhibé. Dispositif pouvant être incorporé dans un système existant pour augmenter la cadence d'appel des instructions.
FR7714007A 1976-06-15 1977-05-03 Dispositif d'appel d'instructions a cadence rapide et normale dans un systeme de traitement de donnees Granted FR2355331A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/696,446 US4093983A (en) 1976-06-15 1976-06-15 Fast and normal rate instruction fetching

Publications (2)

Publication Number Publication Date
FR2355331A1 true FR2355331A1 (fr) 1978-01-13
FR2355331B1 FR2355331B1 (fr) 1979-03-23

Family

ID=24797099

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7714007A Granted FR2355331A1 (fr) 1976-06-15 1977-05-03 Dispositif d'appel d'instructions a cadence rapide et normale dans un systeme de traitement de donnees

Country Status (5)

Country Link
US (1) US4093983A (fr)
JP (1) JPS52153635A (fr)
DE (1) DE2725614A1 (fr)
FR (1) FR2355331A1 (fr)
GB (1) GB1520206A (fr)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4262330A (en) * 1978-10-23 1981-04-14 International Business Machines Corporation I-phase controls for a computer
US4390963A (en) * 1980-09-15 1983-06-28 Motorola, Inc. Interface adapter architecture
US4434461A (en) 1980-09-15 1984-02-28 Motorola, Inc. Microprocessor with duplicate registers for processing interrupts
US4486624A (en) * 1980-09-15 1984-12-04 Motorola, Inc. Microprocessor controlled radiotelephone transceiver
US4455606A (en) * 1981-09-14 1984-06-19 Honeywell Information Systems Inc. Logic control system for efficient memory to CPU transfers
US4514804A (en) * 1981-11-25 1985-04-30 Nippon Electric Co., Ltd. Information handling apparatus having a high speed instruction-executing function
US4577282A (en) * 1982-02-22 1986-03-18 Texas Instruments Incorporated Microcomputer system for digital signal processing
US4740911A (en) * 1984-10-12 1988-04-26 Elxsi International Dynamically controlled interleaving
US5983328A (en) * 1987-03-13 1999-11-09 Texas Instruments Incorporated Data processing device with time-multiplexed memory bus
US5907864A (en) * 1995-06-07 1999-05-25 Texas Instruments Incorporated Data processing device with time-multiplexed memory bus
US7558900B2 (en) * 2004-09-27 2009-07-07 Winbound Electronics Corporation Serial flash semiconductor memory

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3408630A (en) * 1966-03-25 1968-10-29 Burroughs Corp Digital computer having high speed branch operation
US3657705A (en) * 1969-11-12 1972-04-18 Honeywell Inc Instruction translation control with extended address prefix decoding
US3828327A (en) * 1973-04-30 1974-08-06 Ibm Simplified storage protection and address translation under system mode control in a data processing system
US3990052A (en) * 1974-09-25 1976-11-02 Data General Corporation Central processing unit employing microprogrammable control for use in a data processing system

Also Published As

Publication number Publication date
DE2725614A1 (de) 1977-12-29
JPS5433940B2 (fr) 1979-10-24
GB1520206A (en) 1978-08-02
FR2355331B1 (fr) 1979-03-23
US4093983A (en) 1978-06-06
JPS52153635A (en) 1977-12-20
DE2725614C2 (fr) 1988-06-16

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Legal Events

Date Code Title Description
ST Notification of lapse