FR2334199A1 - Procede pour realiser des angles de talus determines pour des bords de structures, realisees par attaque chimique - Google Patents

Procede pour realiser des angles de talus determines pour des bords de structures, realisees par attaque chimique

Info

Publication number
FR2334199A1
FR2334199A1 FR7635519A FR7635519A FR2334199A1 FR 2334199 A1 FR2334199 A1 FR 2334199A1 FR 7635519 A FR7635519 A FR 7635519A FR 7635519 A FR7635519 A FR 7635519A FR 2334199 A1 FR2334199 A1 FR 2334199A1
Authority
FR
France
Prior art keywords
edges
structures
chemical attack
slope angles
determined slope
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7635519A
Other languages
English (en)
French (fr)
Other versions
FR2334199B1 (show.php
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens Corp
Original Assignee
Siemens Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Corp filed Critical Siemens Corp
Publication of FR2334199A1 publication Critical patent/FR2334199A1/fr
Application granted granted Critical
Publication of FR2334199B1 publication Critical patent/FR2334199B1/fr
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P70/00—Cleaning of wafers, substrates or parts of devices
    • H10P70/20—Cleaning during device manufacture
    • H10P70/27—Cleaning during device manufacture during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers
    • H10P70/273—Cleaning during device manufacture during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers the processing being a delineation of conductive layers, e.g. by RIE
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
    • H10P50/264—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
    • H10P50/266—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only
    • H10P50/267—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas
    • H10P50/268—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas of silicon-containing layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/60—Wet etching
    • H10P50/66—Wet etching of conductive or resistive materials
    • H10P50/663—Wet etching of conductive or resistive materials by chemical means only
    • H10P50/667—Wet etching of conductive or resistive materials by chemical means only by liquid etching only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/082—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts the openings being tapered via holes
FR7635519A 1975-12-04 1976-11-25 Procede pour realiser des angles de talus determines pour des bords de structures, realisees par attaque chimique Granted FR2334199A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19752554638 DE2554638A1 (de) 1975-12-04 1975-12-04 Verfahren zur erzeugung definierter boeschungswinkel bei einer aetzkante

Publications (2)

Publication Number Publication Date
FR2334199A1 true FR2334199A1 (fr) 1977-07-01
FR2334199B1 FR2334199B1 (show.php) 1979-04-06

Family

ID=5963486

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7635519A Granted FR2334199A1 (fr) 1975-12-04 1976-11-25 Procede pour realiser des angles de talus determines pour des bords de structures, realisees par attaque chimique

Country Status (7)

Country Link
JP (1) JPS5269576A (show.php)
BE (1) BE849065A (show.php)
DE (1) DE2554638A1 (show.php)
FR (1) FR2334199A1 (show.php)
GB (1) GB1551290A (show.php)
IT (1) IT1065165B (show.php)
NL (1) NL7613275A (show.php)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2340565A1 (fr) * 1976-02-04 1977-09-02 Kom Funkwerk Erfurt Procede et installation pour la fabrication de composants semi-conducteurs
FR2569494A1 (fr) * 1984-08-25 1986-02-28 Ricoh Kk Procede de fabrication de dessins d'interconnexion pour dispositif a semi-conducteur, et dispositifs formes par sa mise en oeuvre
EP0148448A3 (en) * 1983-12-16 1987-08-12 Hitachi, Ltd. Etching method
EP0363099A1 (en) * 1988-10-02 1990-04-11 Canon Kabushiki Kaisha Fine working method of crystalline material
EP0545411A3 (en) * 1991-12-06 1993-07-21 Texas Instruments Deutschland Gmbh Method for improving the step coverage at contact windows

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2754549A1 (de) * 1977-12-07 1979-06-13 Siemens Ag Optoelektronischer sensor nach dem prinzip der ladungsinjektion
DE2837485A1 (de) * 1978-08-28 1980-04-17 Siemens Ag Verfahren zur herstellung einer ladungsgekoppelten anordnung fuer sensoren und speicher
JPS55157234A (en) * 1979-05-25 1980-12-06 Chiyou Lsi Gijutsu Kenkyu Kumiai Manufacture of semiconductor device
DE19837395C2 (de) * 1998-08-18 2001-07-19 Infineon Technologies Ag Verfahren zur Herstellung eines eine strukturierte Isolationsschicht enthaltenden Halbleiterbauelements
US6352934B1 (en) * 1999-08-26 2002-03-05 Infineon Technologies Ag Sidewall oxide process for improved shallow junction formation in support region
US20060175670A1 (en) * 2005-02-10 2006-08-10 Nec Compound Semiconductor Device, Ltd. Field effect transistor and method of manufacturing a field effect transistor
JP2011243657A (ja) * 2010-05-14 2011-12-01 Mitsumi Electric Co Ltd 半導体装置の製造方法

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2340565A1 (fr) * 1976-02-04 1977-09-02 Kom Funkwerk Erfurt Procede et installation pour la fabrication de composants semi-conducteurs
EP0148448A3 (en) * 1983-12-16 1987-08-12 Hitachi, Ltd. Etching method
FR2569494A1 (fr) * 1984-08-25 1986-02-28 Ricoh Kk Procede de fabrication de dessins d'interconnexion pour dispositif a semi-conducteur, et dispositifs formes par sa mise en oeuvre
EP0363099A1 (en) * 1988-10-02 1990-04-11 Canon Kabushiki Kaisha Fine working method of crystalline material
US4999083A (en) * 1988-10-02 1991-03-12 Canon Kabushiki Kaisha Method of etching crystalline material with etchant injection inlet
EP0545411A3 (en) * 1991-12-06 1993-07-21 Texas Instruments Deutschland Gmbh Method for improving the step coverage at contact windows

Also Published As

Publication number Publication date
FR2334199B1 (show.php) 1979-04-06
NL7613275A (nl) 1977-06-07
DE2554638A1 (de) 1977-06-16
JPS5269576A (en) 1977-06-09
BE849065A (fr) 1977-04-01
GB1551290A (en) 1979-08-30
IT1065165B (it) 1985-02-25

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Legal Events

Date Code Title Description
ST Notification of lapse