IT1065165B - Procedimento per formare orli di incisione con un angolo di declivio definito,particolarmente utile per produrre fori di contatto e,o piste conduttrici in circuiti a semiconduttori integrati - Google Patents

Procedimento per formare orli di incisione con un angolo di declivio definito,particolarmente utile per produrre fori di contatto e,o piste conduttrici in circuiti a semiconduttori integrati

Info

Publication number
IT1065165B
IT1065165B IT30064/76A IT3006476A IT1065165B IT 1065165 B IT1065165 B IT 1065165B IT 30064/76 A IT30064/76 A IT 30064/76A IT 3006476 A IT3006476 A IT 3006476A IT 1065165 B IT1065165 B IT 1065165B
Authority
IT
Italy
Prior art keywords
declive
rims
slopes
circuits
conductive
Prior art date
Application number
IT30064/76A
Other languages
English (en)
Original Assignee
Siemens Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag filed Critical Siemens Ag
Application granted granted Critical
Publication of IT1065165B publication Critical patent/IT1065165B/it

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P70/00—Cleaning of wafers, substrates or parts of devices
    • H10P70/20—Cleaning during device manufacture
    • H10P70/27—Cleaning during device manufacture during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers
    • H10P70/273—Cleaning during device manufacture during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers the processing being a delineation of conductive layers, e.g. by RIE
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
    • H10P50/264—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
    • H10P50/266—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only
    • H10P50/267—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas
    • H10P50/268—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas of silicon-containing layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/60—Wet etching
    • H10P50/66—Wet etching of conductive or resistive materials
    • H10P50/663—Wet etching of conductive or resistive materials by chemical means only
    • H10P50/667—Wet etching of conductive or resistive materials by chemical means only by liquid etching only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/082—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts the openings being tapered via holes
IT30064/76A 1975-12-04 1976-12-03 Procedimento per formare orli di incisione con un angolo di declivio definito,particolarmente utile per produrre fori di contatto e,o piste conduttrici in circuiti a semiconduttori integrati IT1065165B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19752554638 DE2554638A1 (de) 1975-12-04 1975-12-04 Verfahren zur erzeugung definierter boeschungswinkel bei einer aetzkante

Publications (1)

Publication Number Publication Date
IT1065165B true IT1065165B (it) 1985-02-25

Family

ID=5963486

Family Applications (1)

Application Number Title Priority Date Filing Date
IT30064/76A IT1065165B (it) 1975-12-04 1976-12-03 Procedimento per formare orli di incisione con un angolo di declivio definito,particolarmente utile per produrre fori di contatto e,o piste conduttrici in circuiti a semiconduttori integrati

Country Status (7)

Country Link
JP (1) JPS5269576A (it)
BE (1) BE849065A (it)
DE (1) DE2554638A1 (it)
FR (1) FR2334199A1 (it)
GB (1) GB1551290A (it)
IT (1) IT1065165B (it)
NL (1) NL7613275A (it)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DD136670A1 (de) * 1976-02-04 1979-07-18 Rudolf Sacher Verfahren und vorrichtung zur herstellung von halbleiterstrukturen
DE2754549A1 (de) * 1977-12-07 1979-06-13 Siemens Ag Optoelektronischer sensor nach dem prinzip der ladungsinjektion
DE2837485A1 (de) * 1978-08-28 1980-04-17 Siemens Ag Verfahren zur herstellung einer ladungsgekoppelten anordnung fuer sensoren und speicher
JPS55157234A (en) * 1979-05-25 1980-12-06 Chiyou Lsi Gijutsu Kenkyu Kumiai Manufacture of semiconductor device
JPS60128622A (ja) * 1983-12-16 1985-07-09 Hitachi Ltd エツチング法
GB2165692B (en) * 1984-08-25 1989-05-04 Ricoh Kk Manufacture of interconnection patterns
EP0363099B1 (en) * 1988-10-02 1996-02-28 Canon Kabushiki Kaisha Fine working method of crystalline material
DE4140330C1 (it) * 1991-12-06 1993-03-18 Texas Instruments Deutschland Gmbh, 8050 Freising, De
DE19837395C2 (de) * 1998-08-18 2001-07-19 Infineon Technologies Ag Verfahren zur Herstellung eines eine strukturierte Isolationsschicht enthaltenden Halbleiterbauelements
US6352934B1 (en) * 1999-08-26 2002-03-05 Infineon Technologies Ag Sidewall oxide process for improved shallow junction formation in support region
US20060175670A1 (en) * 2005-02-10 2006-08-10 Nec Compound Semiconductor Device, Ltd. Field effect transistor and method of manufacturing a field effect transistor
JP2011243657A (ja) * 2010-05-14 2011-12-01 Mitsumi Electric Co Ltd 半導体装置の製造方法

Also Published As

Publication number Publication date
FR2334199B1 (it) 1979-04-06
NL7613275A (nl) 1977-06-07
DE2554638A1 (de) 1977-06-16
FR2334199A1 (fr) 1977-07-01
JPS5269576A (en) 1977-06-09
BE849065A (fr) 1977-04-01
GB1551290A (en) 1979-08-30

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