FR2334199A1 - PROCESS FOR MAKING DETERMINED SLOPE ANGLES FOR EDGES OF STRUCTURES, MADE BY CHEMICAL ATTACK - Google Patents

PROCESS FOR MAKING DETERMINED SLOPE ANGLES FOR EDGES OF STRUCTURES, MADE BY CHEMICAL ATTACK

Info

Publication number
FR2334199A1
FR2334199A1 FR7635519A FR7635519A FR2334199A1 FR 2334199 A1 FR2334199 A1 FR 2334199A1 FR 7635519 A FR7635519 A FR 7635519A FR 7635519 A FR7635519 A FR 7635519A FR 2334199 A1 FR2334199 A1 FR 2334199A1
Authority
FR
France
Prior art keywords
edges
structures
chemical attack
slope angles
determined slope
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7635519A
Other languages
French (fr)
Other versions
FR2334199B1 (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of FR2334199A1 publication Critical patent/FR2334199A1/en
Application granted granted Critical
Publication of FR2334199B1 publication Critical patent/FR2334199B1/fr
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H01L21/02071—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a delineation, e.g. RIE, of conductive layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Plasma & Fusion (AREA)
  • Weting (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
FR7635519A 1975-12-04 1976-11-25 PROCESS FOR MAKING DETERMINED SLOPE ANGLES FOR EDGES OF STRUCTURES, MADE BY CHEMICAL ATTACK Granted FR2334199A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19752554638 DE2554638A1 (en) 1975-12-04 1975-12-04 PROCESS FOR GENERATING DEFINED BOOT ANGLES FOR AN ETCHED EDGE

Publications (2)

Publication Number Publication Date
FR2334199A1 true FR2334199A1 (en) 1977-07-01
FR2334199B1 FR2334199B1 (en) 1979-04-06

Family

ID=5963486

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7635519A Granted FR2334199A1 (en) 1975-12-04 1976-11-25 PROCESS FOR MAKING DETERMINED SLOPE ANGLES FOR EDGES OF STRUCTURES, MADE BY CHEMICAL ATTACK

Country Status (7)

Country Link
JP (1) JPS5269576A (en)
BE (1) BE849065A (en)
DE (1) DE2554638A1 (en)
FR (1) FR2334199A1 (en)
GB (1) GB1551290A (en)
IT (1) IT1065165B (en)
NL (1) NL7613275A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2340565A1 (en) * 1976-02-04 1977-09-02 Kom Funkwerk Erfurt PROCESS AND INSTALLATION FOR THE MANUFACTURING OF SEMICONDUCTOR COMPONENTS
EP0148448A2 (en) * 1983-12-16 1985-07-17 Hitachi, Ltd. Etching method
FR2569494A1 (en) * 1984-08-25 1986-02-28 Ricoh Kk METHOD FOR MANUFACTURING INTERCONNECTION DRAWINGS FOR SEMICONDUCTOR DEVICE, AND DEVICES FORMED BY ITS IMPLEMENTATION
EP0363099A1 (en) * 1988-10-02 1990-04-11 Canon Kabushiki Kaisha Fine working method of crystalline material
EP0545411A2 (en) * 1991-12-06 1993-06-09 Texas Instruments Deutschland Gmbh Method for improving the step coverage at contact windows

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2754549A1 (en) * 1977-12-07 1979-06-13 Siemens Ag OPTOELECTRONIC SENSOR ACCORDING TO THE PRINCIPLE OF CHARGE INJECTION
DE2837485A1 (en) * 1978-08-28 1980-04-17 Siemens Ag METHOD FOR PRODUCING A CHARGED-COUPLED ARRANGEMENT FOR SENSORS AND STORAGE
JPS55157234A (en) * 1979-05-25 1980-12-06 Chiyou Lsi Gijutsu Kenkyu Kumiai Manufacture of semiconductor device
DE19837395C2 (en) * 1998-08-18 2001-07-19 Infineon Technologies Ag Method for producing a semiconductor component containing a structured insulation layer
US6352934B1 (en) * 1999-08-26 2002-03-05 Infineon Technologies Ag Sidewall oxide process for improved shallow junction formation in support region
US20060175670A1 (en) * 2005-02-10 2006-08-10 Nec Compound Semiconductor Device, Ltd. Field effect transistor and method of manufacturing a field effect transistor
JP2011243657A (en) * 2010-05-14 2011-12-01 Mitsumi Electric Co Ltd Semiconductor device manufacturing method

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2340565A1 (en) * 1976-02-04 1977-09-02 Kom Funkwerk Erfurt PROCESS AND INSTALLATION FOR THE MANUFACTURING OF SEMICONDUCTOR COMPONENTS
EP0148448A2 (en) * 1983-12-16 1985-07-17 Hitachi, Ltd. Etching method
EP0148448A3 (en) * 1983-12-16 1987-08-12 Hitachi, Ltd. Etching method
FR2569494A1 (en) * 1984-08-25 1986-02-28 Ricoh Kk METHOD FOR MANUFACTURING INTERCONNECTION DRAWINGS FOR SEMICONDUCTOR DEVICE, AND DEVICES FORMED BY ITS IMPLEMENTATION
EP0363099A1 (en) * 1988-10-02 1990-04-11 Canon Kabushiki Kaisha Fine working method of crystalline material
US4999083A (en) * 1988-10-02 1991-03-12 Canon Kabushiki Kaisha Method of etching crystalline material with etchant injection inlet
EP0545411A2 (en) * 1991-12-06 1993-06-09 Texas Instruments Deutschland Gmbh Method for improving the step coverage at contact windows
EP0545411A3 (en) * 1991-12-06 1993-07-21 Texas Instruments Deutschland Gmbh Method for improving the step coverage at contact windows

Also Published As

Publication number Publication date
DE2554638A1 (en) 1977-06-16
BE849065A (en) 1977-04-01
FR2334199B1 (en) 1979-04-06
GB1551290A (en) 1979-08-30
NL7613275A (en) 1977-06-07
JPS5269576A (en) 1977-06-09
IT1065165B (en) 1985-02-25

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Legal Events

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