FR2333347A1 - Procede de fabrication de dispositifs semiconducteurs pour fusion de zone a gradient de temperature - Google Patents

Procede de fabrication de dispositifs semiconducteurs pour fusion de zone a gradient de temperature

Info

Publication number
FR2333347A1
FR2333347A1 FR7635061A FR7635061A FR2333347A1 FR 2333347 A1 FR2333347 A1 FR 2333347A1 FR 7635061 A FR7635061 A FR 7635061A FR 7635061 A FR7635061 A FR 7635061A FR 2333347 A1 FR2333347 A1 FR 2333347A1
Authority
FR
France
Prior art keywords
semiconductor devices
temperature gradient
manufacturing semiconductor
gradient zone
zone fusion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
FR7635061A
Other languages
English (en)
Inventor
Mike Fushing Chang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
General Electric Co
Original Assignee
General Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by General Electric Co filed Critical General Electric Co
Publication of FR2333347A1 publication Critical patent/FR2333347A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/24—Alloying of impurity materials, e.g. doping materials, electrode materials, with a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Weting (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Element Separation (AREA)
  • Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)
FR7635061A 1975-11-26 1976-11-22 Procede de fabrication de dispositifs semiconducteurs pour fusion de zone a gradient de temperature Withdrawn FR2333347A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/635,327 US4042448A (en) 1975-11-26 1975-11-26 Post TGZM surface etch

Publications (1)

Publication Number Publication Date
FR2333347A1 true FR2333347A1 (fr) 1977-06-24

Family

ID=24547343

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7635061A Withdrawn FR2333347A1 (fr) 1975-11-26 1976-11-22 Procede de fabrication de dispositifs semiconducteurs pour fusion de zone a gradient de temperature

Country Status (6)

Country Link
US (1) US4042448A (fr)
JP (1) JPS5275173A (fr)
DE (1) DE2653287A1 (fr)
FR (1) FR2333347A1 (fr)
GB (1) GB1557300A (fr)
SE (1) SE7613232L (fr)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4076559A (en) * 1977-03-18 1978-02-28 General Electric Company Temperature gradient zone melting through an oxide layer
US6727527B1 (en) 1995-07-31 2004-04-27 Ixys Corporation Reverse blocking IGBT
US20040061170A1 (en) * 1995-07-31 2004-04-01 Ixys Corporation Reverse blocking IGBT
US5698454A (en) * 1995-07-31 1997-12-16 Ixys Corporation Method of making a reverse blocking IGBT
FR2815470A1 (fr) * 2000-10-12 2002-04-19 St Microelectronics Sa Procede de fabrication de composants de puissance verticaux
US6936908B2 (en) 2001-05-03 2005-08-30 Ixys Corporation Forward and reverse blocking devices
US20040188385A1 (en) * 2003-03-26 2004-09-30 Kenji Yamada Etching agent composition for thin films having high permittivity and process for etching
DE102004021228B4 (de) * 2004-04-30 2009-01-08 Infineon Technologies Ag Verfahren zum Einbringen eines Grabens in einen Halbleiterkörper eines Kompensationsbauelementes

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2249443A1 (fr) * 1973-10-30 1975-05-23 Gen Electric

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3272748A (en) * 1964-06-29 1966-09-13 Western Electric Co Etching of silicon and germanium
US3379584A (en) * 1964-09-04 1968-04-23 Texas Instruments Inc Semiconductor wafer with at least one epitaxial layer and methods of making same
US3608186A (en) * 1969-10-30 1971-09-28 Jearld L Hutson Semiconductor device manufacture with junction passivation
US3699402A (en) * 1970-07-27 1972-10-17 Gen Electric Hybrid circuit power module
US3901736A (en) * 1973-10-30 1975-08-26 Gen Electric Method of making deep diode devices
US3920482A (en) * 1974-03-13 1975-11-18 Signetics Corp Method for forming a semiconductor structure having islands isolated by adjacent moats

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2249443A1 (fr) * 1973-10-30 1975-05-23 Gen Electric

Also Published As

Publication number Publication date
GB1557300A (en) 1979-12-05
SE7613232L (sv) 1977-05-27
JPS5275173A (en) 1977-06-23
DE2653287A1 (de) 1977-06-08
US4042448A (en) 1977-08-16

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Legal Events

Date Code Title Description
ST Notification of lapse