FR2290000A1 - Memoire a acces aleatoire a semi-conducteur - Google Patents

Memoire a acces aleatoire a semi-conducteur

Info

Publication number
FR2290000A1
FR2290000A1 FR7533398A FR7533398A FR2290000A1 FR 2290000 A1 FR2290000 A1 FR 2290000A1 FR 7533398 A FR7533398 A FR 7533398A FR 7533398 A FR7533398 A FR 7533398A FR 2290000 A1 FR2290000 A1 FR 2290000A1
Authority
FR
France
Prior art keywords
semiconductor
memory
random access
random
access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7533398A
Other languages
English (en)
Other versions
FR2290000B3 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of FR2290000A1 publication Critical patent/FR2290000A1/fr
Application granted granted Critical
Publication of FR2290000B3 publication Critical patent/FR2290000B3/fr
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4082—Address Buffers; level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4087—Address decoders, e.g. bit - or word line decoders; Multiple line decoders
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/01855—Interface arrangements synchronous, i.e. using clock signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Dram (AREA)
  • Read Only Memory (AREA)
  • Static Random-Access Memory (AREA)
FR7533398A 1974-11-04 1975-10-31 Memoire a acces aleatoire a semi-conducteur Granted FR2290000A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/520,797 US3959781A (en) 1974-11-04 1974-11-04 Semiconductor random access memory

Publications (2)

Publication Number Publication Date
FR2290000A1 true FR2290000A1 (fr) 1976-05-28
FR2290000B3 FR2290000B3 (fr) 1977-11-18

Family

ID=24074109

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7533398A Granted FR2290000A1 (fr) 1974-11-04 1975-10-31 Memoire a acces aleatoire a semi-conducteur

Country Status (4)

Country Link
US (1) US3959781A (fr)
JP (1) JPS5165841A (fr)
DE (1) DE2548564A1 (fr)
FR (1) FR2290000A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2346773A1 (fr) * 1976-03-30 1977-10-28 Honeywell Inf Systems Echantillonnage de puissance pour la realisation d'un triple-etat
FR2346774A1 (fr) * 1976-03-31 1977-10-28 Honeywell Inf Systems Interface de memoire de calculateur
FR2365246A1 (fr) * 1976-09-16 1978-04-14 Siemens Ag Decodeur comportant des transistors mos

Families Citing this family (60)

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FR2258783B1 (fr) * 1974-01-25 1977-09-16 Valentin Camille
JPS51130154A (en) * 1975-05-07 1976-11-12 Nec Corp Flip-flop circuit
JPS51139247A (en) * 1975-05-28 1976-12-01 Hitachi Ltd Mos logic circuit
US4195238A (en) * 1975-06-04 1980-03-25 Hitachi, Ltd. Address buffer circuit in semiconductor memory
JPS51142925A (en) * 1975-06-04 1976-12-08 Hitachi Ltd Address buffer circuit
JPS526044A (en) * 1975-07-04 1977-01-18 Toko Inc Dynamic decoder circuit
DE2634089C3 (de) * 1975-08-11 1988-09-08 Nippon Telegraph And Telephone Corp., Tokio/Tokyo Schaltungsanordnung zum Erfassen schwacher Signale
DE2639555C2 (de) * 1975-09-04 1985-07-04 Plessey Overseas Ltd., Ilford, Essex Elektrische integrierte Schaltung
JPS5268334A (en) * 1975-12-05 1977-06-07 Toshiba Corp Semiconductor memory
US4006469A (en) * 1975-12-16 1977-02-01 International Business Machines Corporation Data storage cell with transistors operating at different threshold voltages
US4096402A (en) * 1975-12-29 1978-06-20 Mostek Corporation MOSFET buffer for TTL logic input and method of operation
US4075606A (en) * 1976-02-13 1978-02-21 E-Systems, Inc. Self-memorizing data bus system for random access data transfer
US4038646A (en) * 1976-03-12 1977-07-26 Intel Corporation Dynamic mos ram
US4038567A (en) * 1976-03-22 1977-07-26 International Business Machines Corporation Memory input signal buffer circuit
JPS52119160A (en) * 1976-03-31 1977-10-06 Nec Corp Semiconductor circuit with insulating gate type field dffect transisto r
DE2623219B2 (de) * 1976-05-24 1978-10-12 Siemens Ag, 1000 Berlin Und 8000 Muenchen Verfahren zum Betreiben einer Leseverstärkerschaltung für einen dynamischen MOS-Speicher und Anordnung zur Durchführung dieses Verfahrens
US4110639A (en) * 1976-12-09 1978-08-29 Texas Instruments Incorporated Address buffer circuit for high speed semiconductor memory
US4077031A (en) * 1976-08-23 1978-02-28 Texas Instruments Incorporated High speed address buffer for semiconductor memory
DE2724646A1 (de) 1976-06-01 1977-12-15 Texas Instruments Inc Halbleiterspeicheranordnung
DE2760462C2 (de) * 1976-06-01 1994-06-30 Texas Instruments Inc Halbleiterspeicheranordnung
SU928405A1 (ru) * 1976-08-05 1982-05-15 Предприятие П/Я Р-6429 Усилитель считывани дл интегрального запоминающего устройства
JPS6012717B2 (ja) * 1976-09-10 1985-04-03 日本電気株式会社 絶縁ゲ−ト型電界効果トランジスタを用いた半導体回路
US4081699A (en) * 1976-09-14 1978-03-28 Mos Technology, Inc. Depletion mode coupling device for a memory line driving circuit
US4094012A (en) * 1976-10-01 1978-06-06 Intel Corporation Electrically programmable MOS read-only memory with isolated decoders
JPS5938670B2 (ja) * 1976-10-15 1984-09-18 日本電気株式会社 差信号増巾回路
US4508980A (en) * 1976-11-11 1985-04-02 Signetics Corporation Sense and refresh amplifier circuit
US4129793A (en) * 1977-06-16 1978-12-12 International Business Machines Corporation High speed true/complement driver
US4149268A (en) * 1977-08-09 1979-04-10 Harris Corporation Dual function memory
DE2738187C2 (de) * 1977-08-24 1979-02-15 Siemens Ag, 1000 Berlin Und 8000 Muenchen Schaltungsanordnung für mehrere auf einem Bipolar-Baustein angeordnete Speicherzellen mit einer Regelschaltung zur Kennlinien-Anpassung der Speicherzellen
US4146802A (en) * 1977-09-19 1979-03-27 Motorola, Inc. Self latching buffer
US4216395A (en) * 1978-01-16 1980-08-05 Bell Telephone Laboratories, Incorporated Detector circuitry
US4169233A (en) * 1978-02-24 1979-09-25 Rockwell International Corporation High performance CMOS sense amplifier
US4328558A (en) * 1978-03-09 1982-05-04 Motorola, Inc. RAM Address enable circuit for a microprocessor having an on-chip RAM
EP0005601B1 (fr) * 1978-05-11 1983-03-02 Nippon Telegraph and Telephone Public Corporation Circuit semiconducteur intégré à mémoire
JPS5826179B2 (ja) * 1978-06-14 1983-06-01 富士通株式会社 半導体集積回路装置
DE2964801D1 (en) * 1978-06-30 1983-03-24 Fujitsu Ltd Semiconductor integrated circuit device
US4216389A (en) * 1978-09-25 1980-08-05 Motorola, Inc. Bus driver/latch with second stage stack input
US4255679A (en) * 1978-10-30 1981-03-10 Texas Instruments Incorporated Depletion load dynamic sense amplifier for MOS random access memory
US4228528B2 (en) * 1979-02-09 1992-10-06 Memory with redundant rows and columns
US4337525A (en) * 1979-04-17 1982-06-29 Nippon Electric Co., Ltd. Asynchronous circuit responsive to changes in logic level
US4333020A (en) * 1979-05-23 1982-06-01 Motorola, Inc. MOS Latch circuit
JPS5842556B2 (ja) * 1979-08-30 1983-09-20 富士通株式会社 半導体記憶装置
US4270189A (en) * 1979-11-06 1981-05-26 International Business Machines Corporation Read only memory circuit
JPS56101694A (en) * 1980-01-18 1981-08-14 Nec Corp Semiconductor circuit
US4401904A (en) * 1980-03-24 1983-08-30 Texas Instruments Incorporated Delay circuit used in semiconductor memory device
US4485317A (en) * 1981-10-02 1984-11-27 Fairchild Camera & Instrument Corp. Dynamic TTL input comparator for CMOS devices
JPS5862893A (ja) * 1981-10-09 1983-04-14 Mitsubishi Electric Corp Ｍｏｓダイナミツクメモリ
US4433252A (en) * 1982-01-18 1984-02-21 International Business Machines Corporation Input signal responsive pulse generating and biasing circuit for integrated circuits
US4471240A (en) * 1982-08-19 1984-09-11 Motorola, Inc. Power-saving decoder for memories
DE3380678D1 (en) * 1983-05-25 1989-11-09 Ibm Deutschland Semiconductor memory
JPS60224329A (ja) * 1984-04-20 1985-11-08 Sharp Corp Ｍｏｓ集積回路素子の入力回路
ATE47928T1 (de) * 1984-05-14 1989-11-15 Ibm Halbleiterspeicher.
US5018111A (en) * 1988-12-27 1991-05-21 Intel Corporation Timing circuit for memory employing reset function
US5307356A (en) * 1990-04-16 1994-04-26 International Business Machines Corporation Interlocked on-chip ECC system
KR930003929B1 (ko) * 1990-08-09 1993-05-15 삼성전자 주식회사 데이타 출력버퍼
DE4228213C2 (de) * 1991-09-19 1997-05-15 Siemens Ag Integrierte Halbleiterspeicherschaltung und Verfahren zu ihrem Betreiben
EP0733976A1 (fr) * 1995-03-23 1996-09-25 Canon Kabushiki Kaisha Générateur de signal de sélection de puces
FR2768847B1 (fr) * 1997-09-23 2001-05-18 St Microelectronics Sa Dispositif et procede de lecture/re-ecriture d'une cellule-memoire vive dynamique
US6044024A (en) * 1998-01-14 2000-03-28 International Business Machines Corporation Interactive method for self-adjusted access on embedded DRAM memory macros
KR100299183B1 (ko) * 1999-09-10 2001-11-07 윤종용 고속 파이프 라인장치 및 그 제어신호 발생방법

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US3387286A (en) * 1967-07-14 1968-06-04 Ibm Field-effect transistor memory
US3699537A (en) * 1969-05-16 1972-10-17 Shell Oil Co Single-rail mosfet memory with capacitive storage

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2346773A1 (fr) * 1976-03-30 1977-10-28 Honeywell Inf Systems Echantillonnage de puissance pour la realisation d'un triple-etat
FR2346774A1 (fr) * 1976-03-31 1977-10-28 Honeywell Inf Systems Interface de memoire de calculateur
FR2365246A1 (fr) * 1976-09-16 1978-04-14 Siemens Ag Decodeur comportant des transistors mos

Also Published As

Publication number Publication date
JPS5165841A (en) 1976-06-07
FR2290000B3 (fr) 1977-11-18
US3959781A (en) 1976-05-25
DE2548564A1 (de) 1976-05-26

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Legal Events

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ST Notification of lapse