IT1039147B - Memoria associativa perfezionata - Google Patents

Memoria associativa perfezionata

Info

Publication number
IT1039147B
IT1039147B IT24576/75A IT2457675A IT1039147B IT 1039147 B IT1039147 B IT 1039147B IT 24576/75 A IT24576/75 A IT 24576/75A IT 2457675 A IT2457675 A IT 2457675A IT 1039147 B IT1039147 B IT 1039147B
Authority
IT
Italy
Prior art keywords
associative memory
improved associative
improved
memory
associative
Prior art date
Application number
IT24576/75A
Other languages
English (en)
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of IT1039147B publication Critical patent/IT1039147B/it

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
    • G11C15/04—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
IT24576/75A 1974-08-06 1975-06-20 Memoria associativa perfezionata IT1039147B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US495165A US3924243A (en) 1974-08-06 1974-08-06 Cross-field-partitioning in array logic modules

Publications (1)

Publication Number Publication Date
IT1039147B true IT1039147B (it) 1979-12-10

Family

ID=23967529

Family Applications (1)

Application Number Title Priority Date Filing Date
IT24576/75A IT1039147B (it) 1974-08-06 1975-06-20 Memoria associativa perfezionata

Country Status (5)

Country Link
US (1) US3924243A (it)
JP (1) JPS5756158B2 (it)
DE (1) DE2532125C2 (it)
FR (1) FR2281628A1 (it)
IT (1) IT1039147B (it)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1042852B (it) * 1974-09-30 1980-01-30 Siemens Ag Disposizione di circuiti logici integrata e programmabile
DE2455178C2 (de) * 1974-11-21 1982-12-23 Siemens AG, 1000 Berlin und 8000 München Integrierte, programmierbare Logikanordnung
IT1063025B (it) * 1975-04-29 1985-02-11 Siemens Ag Disposizione circuitale logica integrata e programmabile
US4123669A (en) * 1977-09-08 1978-10-31 International Business Machines Corporation Logical OR circuit for programmed logic arrays
US4506341A (en) * 1982-06-10 1985-03-19 International Business Machines Corporation Interlaced programmable logic array having shared elements
JPH06101232B2 (ja) * 1984-10-24 1994-12-12 日本電気株式会社 連想記憶装置
US4761768A (en) * 1985-03-04 1988-08-02 Lattice Semiconductor Corporation Programmable logic device
US4876640A (en) * 1986-02-07 1989-10-24 Advanced Micro Devices, Inc. Logic controller having programmable logic "and" array using a programmable gray-code counter
US5235221A (en) * 1992-04-08 1993-08-10 Micron Technology, Inc. Field programmable logic array with speed optimized architecture
US5384500A (en) * 1992-05-15 1995-01-24 Micron Semiconductor, Inc. Programmable logic device macrocell with an exclusive feedback and an exclusive external input line for a combinatorial mode and accommodating two separate programmable or planes
US5331227A (en) * 1992-05-15 1994-07-19 Micron Semiconductor, Inc. Programmable logic device macrocell with an exclusive feedback line and an exclusive external input line
US5287017A (en) * 1992-05-15 1994-02-15 Micron Technology, Inc. Programmable logic device macrocell with two OR array inputs
US5220215A (en) * 1992-05-15 1993-06-15 Micron Technology, Inc. Field programmable logic array with two or planes
US5300830A (en) * 1992-05-15 1994-04-05 Micron Semiconductor, Inc. Programmable logic device macrocell with an exclusive feedback and exclusive external input lines for registered and combinatorial modes using a dedicated product term for control
US5298803A (en) * 1992-07-15 1994-03-29 Micron Semiconductor, Inc. Programmable logic device having low power microcells with selectable registered and combinatorial output signals
US6856527B1 (en) 2003-05-30 2005-02-15 Netlogic Microsystems, Inc. Multi-compare content addressable memory cell
US6842360B1 (en) 2003-05-30 2005-01-11 Netlogic Microsystems, Inc. High-density content addressable memory cell
US7174419B1 (en) 2003-05-30 2007-02-06 Netlogic Microsystems, Inc Content addressable memory device with source-selecting data translator

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1229717A (it) * 1969-11-27 1971-04-28
US3593317A (en) * 1969-12-30 1971-07-13 Ibm Partitioning logic operations in a generalized matrix system
GB1367358A (en) * 1971-08-10 1974-09-18 Drexel Equipment Ltd Pawls
US3742460A (en) * 1971-12-20 1973-06-26 Sperry Rand Corp Search memory
US3761902A (en) * 1971-12-30 1973-09-25 Ibm Functional memory using multi-state associative cells
GB1372926A (en) * 1972-01-17 1974-11-06 Ibm Associative store
US3809884A (en) * 1972-11-15 1974-05-07 Honeywell Inf Systems Apparatus and method for a variable memory cycle in a data processing unit
DE2357654C2 (de) * 1972-11-21 1981-10-29 Aleksej Davidovič Ljubercy Moskovskaja oblast'i Gvinepadze Assoziativspeicher

Also Published As

Publication number Publication date
DE2532125A1 (de) 1976-02-26
US3924243A (en) 1975-12-02
JPS5756158B2 (it) 1982-11-27
FR2281628B1 (it) 1977-12-16
FR2281628A1 (fr) 1976-03-05
DE2532125C2 (de) 1983-10-27
JPS5136045A (it) 1976-03-26

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