JPS5756158B2 - - Google Patents

Info

Publication number
JPS5756158B2
JPS5756158B2 JP50086760A JP8676075A JPS5756158B2 JP S5756158 B2 JPS5756158 B2 JP S5756158B2 JP 50086760 A JP50086760 A JP 50086760A JP 8676075 A JP8676075 A JP 8676075A JP S5756158 B2 JPS5756158 B2 JP S5756158B2
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP50086760A
Other versions
JPS5136045A (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPS5136045A publication Critical patent/JPS5136045A/ja
Publication of JPS5756158B2 publication Critical patent/JPS5756158B2/ja
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H03K19/17708Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C15/00Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
    • G11C15/04Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
JP50086760A 1974-08-06 1975-07-17 Expired JPS5756158B2 (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US495165A US3924243A (en) 1974-08-06 1974-08-06 Cross-field-partitioning in array logic modules

Publications (2)

Publication Number Publication Date
JPS5136045A JPS5136045A (ja) 1976-03-26
JPS5756158B2 true JPS5756158B2 (ja) 1982-11-27

Family

ID=23967529

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50086760A Expired JPS5756158B2 (ja) 1974-08-06 1975-07-17

Country Status (5)

Country Link
US (1) US3924243A (ja)
JP (1) JPS5756158B2 (ja)
DE (1) DE2532125C2 (ja)
FR (1) FR2281628A1 (ja)
IT (1) IT1039147B (ja)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1042852B (it) * 1974-09-30 1980-01-30 Siemens Ag Disposizione di circuiti logici integrata e programmabile
DE2455178C2 (de) * 1974-11-21 1982-12-23 Siemens AG, 1000 Berlin und 8000 München Integrierte, programmierbare Logikanordnung
IT1063025B (it) * 1975-04-29 1985-02-11 Siemens Ag Disposizione circuitale logica integrata e programmabile
US4123669A (en) * 1977-09-08 1978-10-31 International Business Machines Corporation Logical OR circuit for programmed logic arrays
US4506341A (en) * 1982-06-10 1985-03-19 International Business Machines Corporation Interlaced programmable logic array having shared elements
JPH06101232B2 (ja) * 1984-10-24 1994-12-12 日本電気株式会社 連想記憶装置
US4761768A (en) * 1985-03-04 1988-08-02 Lattice Semiconductor Corporation Programmable logic device
US4876640A (en) * 1986-02-07 1989-10-24 Advanced Micro Devices, Inc. Logic controller having programmable logic "and" array using a programmable gray-code counter
US5235221A (en) * 1992-04-08 1993-08-10 Micron Technology, Inc. Field programmable logic array with speed optimized architecture
US5300830A (en) * 1992-05-15 1994-04-05 Micron Semiconductor, Inc. Programmable logic device macrocell with an exclusive feedback and exclusive external input lines for registered and combinatorial modes using a dedicated product term for control
US5220215A (en) * 1992-05-15 1993-06-15 Micron Technology, Inc. Field programmable logic array with two or planes
US5287017A (en) * 1992-05-15 1994-02-15 Micron Technology, Inc. Programmable logic device macrocell with two OR array inputs
US5384500A (en) * 1992-05-15 1995-01-24 Micron Semiconductor, Inc. Programmable logic device macrocell with an exclusive feedback and an exclusive external input line for a combinatorial mode and accommodating two separate programmable or planes
US5331227A (en) * 1992-05-15 1994-07-19 Micron Semiconductor, Inc. Programmable logic device macrocell with an exclusive feedback line and an exclusive external input line
US5298803A (en) * 1992-07-15 1994-03-29 Micron Semiconductor, Inc. Programmable logic device having low power microcells with selectable registered and combinatorial output signals
US6842360B1 (en) 2003-05-30 2005-01-11 Netlogic Microsystems, Inc. High-density content addressable memory cell
US6856527B1 (en) 2003-05-30 2005-02-15 Netlogic Microsystems, Inc. Multi-compare content addressable memory cell
US7174419B1 (en) 2003-05-30 2007-02-06 Netlogic Microsystems, Inc Content addressable memory device with source-selecting data translator

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3593317A (en) * 1969-12-30 1971-07-13 Ibm Partitioning logic operations in a generalized matrix system
JPS4827486A (ja) * 1971-08-10 1973-04-11

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1229717A (ja) * 1969-11-27 1971-04-28
US3742460A (en) * 1971-12-20 1973-06-26 Sperry Rand Corp Search memory
US3761902A (en) * 1971-12-30 1973-09-25 Ibm Functional memory using multi-state associative cells
GB1372926A (en) * 1972-01-17 1974-11-06 Ibm Associative store
US3809884A (en) * 1972-11-15 1974-05-07 Honeywell Inf Systems Apparatus and method for a variable memory cycle in a data processing unit
DE2357654C2 (de) * 1972-11-21 1981-10-29 Aleksej Davidovič Ljubercy Moskovskaja oblast'i Gvinepadze Assoziativspeicher

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3593317A (en) * 1969-12-30 1971-07-13 Ibm Partitioning logic operations in a generalized matrix system
JPS4827486A (ja) * 1971-08-10 1973-04-11

Also Published As

Publication number Publication date
FR2281628B1 (ja) 1977-12-16
IT1039147B (it) 1979-12-10
DE2532125A1 (de) 1976-02-26
FR2281628A1 (fr) 1976-03-05
US3924243A (en) 1975-12-02
DE2532125C2 (de) 1983-10-27
JPS5136045A (ja) 1976-03-26

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