FR2287067A1 - Dispositif de tamponnage d'informations entre un processeur et sa memoire principale - Google Patents

Dispositif de tamponnage d'informations entre un processeur et sa memoire principale

Info

Publication number
FR2287067A1
FR2287067A1 FR7433602A FR7433602A FR2287067A1 FR 2287067 A1 FR2287067 A1 FR 2287067A1 FR 7433602 A FR7433602 A FR 7433602A FR 7433602 A FR7433602 A FR 7433602A FR 2287067 A1 FR2287067 A1 FR 2287067A1
Authority
FR
France
Prior art keywords
memory
principal memory
principal
buffer
processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7433602A
Other languages
English (en)
Other versions
FR2287067B1 (fr
Inventor
Daniel Rene Vinot
Jacques Bienvenu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull SA
Original Assignee
Societe Industrielle Honeywell Bull
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to FR111566D priority Critical patent/FR111566A/fr
Application filed by Societe Industrielle Honeywell Bull filed Critical Societe Industrielle Honeywell Bull
Priority to FR7433602A priority patent/FR2287067A1/fr
Priority to JP50119033A priority patent/JPS5191634A/ja
Publication of FR2287067A1 publication Critical patent/FR2287067A1/fr
Application granted granted Critical
Publication of FR2287067B1 publication Critical patent/FR2287067B1/fr
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G06F12/0859—Overlapped cache accessing, e.g. pipeline with reload from main memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
FR7433602A 1974-10-04 1974-10-04 Dispositif de tamponnage d'informations entre un processeur et sa memoire principale Granted FR2287067A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
FR111566D FR111566A (fr) 1974-10-04
FR7433602A FR2287067A1 (fr) 1974-10-04 1974-10-04 Dispositif de tamponnage d'informations entre un processeur et sa memoire principale
JP50119033A JPS5191634A (fr) 1974-10-04 1975-10-03

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7433602A FR2287067A1 (fr) 1974-10-04 1974-10-04 Dispositif de tamponnage d'informations entre un processeur et sa memoire principale

Publications (2)

Publication Number Publication Date
FR2287067A1 true FR2287067A1 (fr) 1976-04-30
FR2287067B1 FR2287067B1 (fr) 1977-11-04

Family

ID=9143790

Family Applications (2)

Application Number Title Priority Date Filing Date
FR111566D Active FR111566A (fr) 1974-10-04
FR7433602A Granted FR2287067A1 (fr) 1974-10-04 1974-10-04 Dispositif de tamponnage d'informations entre un processeur et sa memoire principale

Family Applications Before (1)

Application Number Title Priority Date Filing Date
FR111566D Active FR111566A (fr) 1974-10-04

Country Status (2)

Country Link
JP (1) JPS5191634A (fr)
FR (2) FR2287067A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2412139A1 (fr) * 1977-12-16 1979-07-13 Honeywell Inf Systems Circuits de directives d'antememoire
FR2489021A1 (fr) * 1980-08-22 1982-02-26 Nippon Electric Co Agencement d'antememoires comprenant une antememoire tampon en combinaison avec une paire d'antememoires
EP0149392A2 (fr) * 1983-12-29 1985-07-24 Fujitsu Limited Système d'ordinateur numérique

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4309754A (en) * 1979-07-30 1982-01-05 International Business Machines Corp. Data interface mechanism for interfacing bit-parallel data buses of different bit width

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2211146A5 (fr) * 1972-12-15 1974-07-12 Siemens Ag

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2211146A5 (fr) * 1972-12-15 1974-07-12 Siemens Ag

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2412139A1 (fr) * 1977-12-16 1979-07-13 Honeywell Inf Systems Circuits de directives d'antememoire
FR2489021A1 (fr) * 1980-08-22 1982-02-26 Nippon Electric Co Agencement d'antememoires comprenant une antememoire tampon en combinaison avec une paire d'antememoires
EP0149392A2 (fr) * 1983-12-29 1985-07-24 Fujitsu Limited Système d'ordinateur numérique
EP0149392A3 (en) * 1983-12-29 1987-09-16 Fujitsu Limited Digital computer system

Also Published As

Publication number Publication date
JPS5191634A (fr) 1976-08-11
FR2287067B1 (fr) 1977-11-04
FR111566A (fr)

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Legal Events

Date Code Title Description
ST Notification of lapse