FR2133692A1 - - Google Patents

Info

Publication number
FR2133692A1
FR2133692A1 FR7213006A FR7213006A FR2133692A1 FR 2133692 A1 FR2133692 A1 FR 2133692A1 FR 7213006 A FR7213006 A FR 7213006A FR 7213006 A FR7213006 A FR 7213006A FR 2133692 A1 FR2133692 A1 FR 2133692A1
Authority
FR
France
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7213006A
Other languages
French (fr)
Other versions
FR2133692B1 (enExample
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Gloeilampenfabrieken NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Gloeilampenfabrieken NV filed Critical Philips Gloeilampenfabrieken NV
Publication of FR2133692A1 publication Critical patent/FR2133692A1/fr
Application granted granted Critical
Publication of FR2133692B1 publication Critical patent/FR2133692B1/fr
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W15/00Highly-doped buried regions of integrated devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/60Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
    • H10D84/67Complementary BJTs
    • H10D84/673Vertical complementary BJTs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/87Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of PN-junction gate FETs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01Manufacture or treatment
    • H10W10/011Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H10W10/0121Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] in regions recessed from the surface, e.g. in trenches or grooves
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01Manufacture or treatment
    • H10W10/011Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H10W10/0125Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] comprising introducing electrical impurities in local oxidation regions, e.g. to alter LOCOS oxide growth characteristics
    • H10W10/0126Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] comprising introducing electrical impurities in local oxidation regions, e.g. to alter LOCOS oxide growth characteristics introducing electrical active impurities in local oxidation regions to create channel stoppers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10Isolation regions comprising dielectric materials
    • H10W10/13Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W15/00Highly-doped buried regions of integrated devices
    • H10W15/01Manufacture or treatment
FR7213006A 1971-04-14 1972-04-13 Expired FR2133692B1 (enExample)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL7105000A NL7105000A (enExample) 1971-04-14 1971-04-14

Publications (2)

Publication Number Publication Date
FR2133692A1 true FR2133692A1 (enExample) 1972-12-01
FR2133692B1 FR2133692B1 (enExample) 1977-08-19

Family

ID=19812915

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7213006A Expired FR2133692B1 (enExample) 1971-04-14 1972-04-13

Country Status (11)

Country Link
AU (1) AU470407B2 (enExample)
BE (1) BE782012A (enExample)
BR (1) BR7202251D0 (enExample)
CH (1) CH539952A (enExample)
DE (1) DE2216642C3 (enExample)
ES (1) ES401687A1 (enExample)
FR (1) FR2133692B1 (enExample)
GB (1) GB1387021A (enExample)
IT (1) IT951314B (enExample)
NL (1) NL7105000A (enExample)
SE (1) SE383582B (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL161301C (nl) * 1972-12-29 1980-01-15 Philips Nv Halfgeleiderinrichting en werkwijze voor de vervaar- diging daarvan.
JPS5534619U (enExample) * 1978-08-25 1980-03-06

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2030578A6 (fr) * 1967-12-05 1970-11-13 Sony Corp Procédé de fabrication de circuits semi-conducteurs intégrés et circuits ainsi obtenus

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2030578A6 (fr) * 1967-12-05 1970-11-13 Sony Corp Procédé de fabrication de circuits semi-conducteurs intégrés et circuits ainsi obtenus

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
(REVUE US:"ELECTRONICS",VOL.44,NO5,1 MARS 1971"ISOLATION METHOD SHRINKS BIPOLAR CELLS FOR FAST, DENSEMEMORIES" *
D.PELTZER ET B.HERNDON,PAGES 53-55.) *
DENSEMEMORIES" *
REVUE US:"ELECTRONICS",VOL.44,NO5,1 MARS 1971"ISOLATION METHOD SHRINKS BIPOLAR CELLS FOR FAST, *

Also Published As

Publication number Publication date
GB1387021A (en) 1975-03-12
IT951314B (it) 1973-06-30
DE2216642A1 (de) 1972-10-19
BR7202251D0 (pt) 1973-06-07
DE2216642B2 (de) 1979-04-12
AU470407B2 (en) 1973-10-18
DE2216642C3 (de) 1979-12-13
ES401687A1 (es) 1975-03-16
AU4093672A (en) 1973-10-18
CH539952A (de) 1973-07-31
NL7105000A (enExample) 1972-10-17
FR2133692B1 (enExample) 1977-08-19
BE782012A (fr) 1972-10-13
SE383582B (sv) 1976-03-15

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Legal Events

Date Code Title Description
ST Notification of lapse