GB1387021A - Semiconductor device manufacture - Google Patents

Semiconductor device manufacture

Info

Publication number
GB1387021A
GB1387021A GB1660972A GB1660972A GB1387021A GB 1387021 A GB1387021 A GB 1387021A GB 1660972 A GB1660972 A GB 1660972A GB 1660972 A GB1660972 A GB 1660972A GB 1387021 A GB1387021 A GB 1387021A
Authority
GB
United Kingdom
Prior art keywords
type
layer
island
semi
diffusion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB1660972A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Philips Electronics UK Ltd
Original Assignee
Philips Electronic and Associated Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Electronic and Associated Industries Ltd filed Critical Philips Electronic and Associated Industries Ltd
Publication of GB1387021A publication Critical patent/GB1387021A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
    • H01L27/0823—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only including vertical bipolar transistors only
    • H01L27/0826—Combination of vertical complementary transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/098—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being PN junction gate field-effect transistors

Abstract

1387021 Semi-conductor devices PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd 11 April 1972 [14 April 1971] 16609/72 Heading H1K A semi-conductor device region, e.g. containing active zones 7, 8, is isolated from the remainder of a semiconductor layer 3 and from the substrate 1, 2 by an inset ring 5A of insulating material and by two superposed buried layers 4, 9 of opposite conductivity type and wherein the isolated semi-conductor layer region is divided into two island-shaped regions I, II by a further insulating material region 5B that does not extend through the topmost buried layer 9, in one of which island-shaped regions (I) the semi-conductor circuit element is at least partly provided. The arrangement enables complementary circuit elements, e.g. bipolar transistors, P-N junction FET's, IGFET's or P-N-P-N structures, to be insulated both from each other and from the substrate and constructed as a compact monolithic integrated circuit. In the manufacture of the arrangement shown, boron is diffused into an N-type Si plate 1 to form P-type layers 4, 11 using a thermally grown oxide mask. N-type Si layer 2 is epitaxially grown thereover and N-type layer 9 is formed by diffusing arsenic into the region 4. N-type epitaxial Si layer 3 is then grown and a masking layer of silicon nitride formed thereover and, through holes etched through the silicon nitride, the Si layer 3 is oxidized at 1000‹ C. in moist oxygen to form the inset oxide pattern 5, thus forming island-shaped regions I to V in the layer 3. The island IV is made fully P-type by deep boron diffusion, and P-type zones 13, 7, 14 are formed by less deep boron diffusionwith these diffusions the inset oxide 5 acts as a diffusion mask. Using an apertured oxide layer formed by thermal conversion of SiH4 and O2 N-type zones 8, 15 and N-type contact regions in base zone 12 and island II are formed by phosphorus diffusion. Al contacts 16-25 are formed by vapour deposition and photolithographic etching. Thus two complementary bipolar transistors are provided which may have mutually comparable doping concentrations. P-type zone 7, for example, forming the base zone of a bipolar transistor may have a homogeneous or a varying dopant concentration profile. The buried layers 4, 11 need not be separate and, if desired, may be maintained at a floating potential. The doping of the various regions may alternatively be carried out by ion implantation or by diffusion out of a doped oxide layer.
GB1660972A 1971-04-14 1972-04-11 Semiconductor device manufacture Expired GB1387021A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL7105000A NL7105000A (en) 1971-04-14 1971-04-14

Publications (1)

Publication Number Publication Date
GB1387021A true GB1387021A (en) 1975-03-12

Family

ID=19812915

Family Applications (1)

Application Number Title Priority Date Filing Date
GB1660972A Expired GB1387021A (en) 1971-04-14 1972-04-11 Semiconductor device manufacture

Country Status (11)

Country Link
AU (1) AU470407B2 (en)
BE (1) BE782012A (en)
BR (1) BR7202251D0 (en)
CH (1) CH539952A (en)
DE (1) DE2216642C3 (en)
ES (1) ES401687A1 (en)
FR (1) FR2133692B1 (en)
GB (1) GB1387021A (en)
IT (1) IT951314B (en)
NL (1) NL7105000A (en)
SE (1) SE383582B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL161301C (en) * 1972-12-29 1980-01-15 Philips Nv SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURE THEREOF.
JPS5534619U (en) * 1978-08-25 1980-03-06

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE740938A (en) * 1967-12-05 1970-04-01

Also Published As

Publication number Publication date
BE782012A (en) 1972-10-13
DE2216642C3 (en) 1979-12-13
FR2133692B1 (en) 1977-08-19
SE383582B (en) 1976-03-15
DE2216642A1 (en) 1972-10-19
FR2133692A1 (en) 1972-12-01
ES401687A1 (en) 1975-03-16
AU4093672A (en) 1973-10-18
CH539952A (en) 1973-07-31
AU470407B2 (en) 1973-10-18
DE2216642B2 (en) 1979-04-12
IT951314B (en) 1973-06-30
BR7202251D0 (en) 1973-06-07
NL7105000A (en) 1972-10-17

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Legal Events

Date Code Title Description
PS Patent sealed
PCNP Patent ceased through non-payment of renewal fee