FI964196A - Menetelmä ja laite muistin ohjaamiseksi - Google Patents

Menetelmä ja laite muistin ohjaamiseksi Download PDF

Info

Publication number
FI964196A
FI964196A FI964196A FI964196A FI964196A FI 964196 A FI964196 A FI 964196A FI 964196 A FI964196 A FI 964196A FI 964196 A FI964196 A FI 964196A FI 964196 A FI964196 A FI 964196A
Authority
FI
Finland
Prior art keywords
memory
bit positions
control
digital information
sum
Prior art date
Application number
FI964196A
Other languages
English (en)
Swedish (sv)
Other versions
FI964196A0 (fi
Inventor
Eva Charlotte Westerlund
Original Assignee
Ericsson Telefon Ab L M
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson Telefon Ab L M filed Critical Ericsson Telefon Ab L M
Publication of FI964196A publication Critical patent/FI964196A/fi
Publication of FI964196A0 publication Critical patent/FI964196A0/fi

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G06F11/1016—Error in accessing a memory location, i.e. addressing error

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Electrotherapy Devices (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Detection And Correction Of Errors (AREA)
  • Debugging And Monitoring (AREA)
  • Selective Calling Equipment (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
  • Sliding-Contact Bearings (AREA)
  • Communication Control (AREA)
  • Warehouses Or Storage Devices (AREA)
FI964196A 1994-04-19 1996-10-18 Menetelmä ja laite muistin ohjaamiseksi FI964196A0 (fi)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SE9401318A SE503316C2 (sv) 1994-04-19 1994-04-19 Förfarande för övervakning av ett minne samt kretsanordning härför
PCT/SE1995/000420 WO1995028674A2 (en) 1994-04-19 1995-04-18 Method and device to control a memory

Publications (2)

Publication Number Publication Date
FI964196A true FI964196A (fi) 1996-10-18
FI964196A0 FI964196A0 (fi) 1996-10-18

Family

ID=20393700

Family Applications (1)

Application Number Title Priority Date Filing Date
FI964196A FI964196A0 (fi) 1994-04-19 1996-10-18 Menetelmä ja laite muistin ohjaamiseksi

Country Status (14)

Country Link
US (1) US5577055A (fi)
EP (1) EP0756727B1 (fi)
JP (1) JP2989669B2 (fi)
KR (1) KR100301098B1 (fi)
CN (1) CN1146248A (fi)
AT (1) ATE212455T1 (fi)
AU (1) AU682767B2 (fi)
BR (1) BR9507465A (fi)
CA (1) CA2186977C (fi)
DE (1) DE69525154T2 (fi)
FI (1) FI964196A0 (fi)
NO (1) NO964401L (fi)
SE (1) SE503316C2 (fi)
WO (1) WO1995028674A2 (fi)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19650993A1 (de) * 1996-11-26 1998-05-28 Francotyp Postalia Gmbh Anordnung und Verfahren zur Verbesserung der Datensicherheit mittels Ringpuffer
US20020133769A1 (en) * 2001-03-15 2002-09-19 Cowles Timothy B. Circuit and method for test and repair
US6904552B2 (en) * 2001-03-15 2005-06-07 Micron Technolgy, Inc. Circuit and method for test and repair
JP2002288041A (ja) * 2001-03-23 2002-10-04 Sony Corp 情報処理装置および方法、プログラム格納媒体、並びにプログラム
CN100338600C (zh) * 2003-01-03 2007-09-19 宇东科技股份有限公司 读取传感器的方法
US8583971B2 (en) * 2010-12-23 2013-11-12 Advanced Micro Devices, Inc. Error detection in FIFO queues using signature bits
US9311975B1 (en) * 2014-10-07 2016-04-12 Stmicroelectronics S.R.L. Bi-synchronous electronic device and FIFO memory circuit with jump candidates and related methods
JP2016167210A (ja) * 2015-03-10 2016-09-15 株式会社東芝 メモリコントローラ、データストレージデバイス、及び、データ書き込み方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4019033A (en) * 1975-12-29 1977-04-19 Honeywell Information Systems, Inc. Control store checking system and method
US4271521A (en) * 1979-07-09 1981-06-02 The Anaconda Company Address parity check system
IL67664A (en) * 1982-01-19 1987-01-30 Tandem Computers Inc Computer memory system with data,address and operation error detection
US4692893A (en) * 1984-12-24 1987-09-08 International Business Machines Corp. Buffer system using parity checking of address counter bit for detection of read/write failures
US4809278A (en) * 1986-04-21 1989-02-28 Unisys Corporation Specialized parity detection system for wide memory structure
US5047927A (en) * 1988-10-28 1991-09-10 National Semiconductor Corporation Memory management in packet data mode systems
EP0463210B1 (en) * 1990-06-27 1995-05-31 International Business Machines Corporation Method and apparatus for checking the address and contents of a memory array
DE4104198A1 (de) * 1991-02-12 1992-08-13 Basf Ag Verfahren zur herstellung von formteilen mit guten oberflaecheneigenschaften
DE69129851T2 (de) * 1991-09-13 1999-03-25 International Business Machines Corp., Armonk, N.Y. Konfigurierbare gigabit/s Vermittlunganpassungseinrichtung
US5426639A (en) * 1991-11-29 1995-06-20 At&T Corp. Multiple virtual FIFO arrangement
DE69124743T2 (de) * 1991-11-29 1997-08-14 Ibm Vorrichtung zur Speicherung und Durchschaltung und Verfahren zur Datensicherung während der Speicherung
US5477553A (en) * 1994-07-22 1995-12-19 Professional Computer Systems, Inc. Compressed memory address parity checking apparatus and method

Also Published As

Publication number Publication date
EP0756727A1 (en) 1997-02-05
DE69525154D1 (de) 2002-03-14
CN1146248A (zh) 1997-03-26
WO1995028674A2 (en) 1995-10-26
SE9401318D0 (sv) 1994-04-19
AU682767B2 (en) 1997-10-16
US5577055A (en) 1996-11-19
EP0756727B1 (en) 2002-01-23
CA2186977A1 (en) 1995-10-26
BR9507465A (pt) 1997-09-16
CA2186977C (en) 2000-10-03
AU2378495A (en) 1995-11-10
JP2989669B2 (ja) 1999-12-13
NO964401D0 (no) 1996-10-16
DE69525154T2 (de) 2002-09-05
WO1995028674A3 (en) 1995-11-30
JPH09505680A (ja) 1997-06-03
ATE212455T1 (de) 2002-02-15
KR970702525A (ko) 1997-05-13
KR100301098B1 (ko) 2001-10-26
SE503316C2 (sv) 1996-05-13
FI964196A0 (fi) 1996-10-18
SE9401318L (sv) 1995-10-20
NO964401L (no) 1996-12-13

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