FI115006B - Metod och anordning för ankoppling förbättrad gränsskikt i mellan av dataskärm och processor - Google Patents

Metod och anordning för ankoppling förbättrad gränsskikt i mellan av dataskärm och processor Download PDF

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Publication number
FI115006B
FI115006B FI20035096A FI20035096A FI115006B FI 115006 B FI115006 B FI 115006B FI 20035096 A FI20035096 A FI 20035096A FI 20035096 A FI20035096 A FI 20035096A FI 115006 B FI115006 B FI 115006B
Authority
FI
Finland
Prior art keywords
interface
processor
signaling
display
display device
Prior art date
Application number
FI20035096A
Other languages
English (en)
Finnish (fi)
Other versions
FI20035096A0 (sv
FI20035096A (sv
Inventor
Kauko Laakkonen
Original Assignee
Nokia Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nokia Corp filed Critical Nokia Corp
Priority to FI20035096A priority Critical patent/FI115006B/sv
Publication of FI20035096A0 publication Critical patent/FI20035096A0/sv
Priority to CNB2004800163041A priority patent/CN100429615C/zh
Priority to PCT/FI2004/050092 priority patent/WO2004111829A1/en
Priority to JP2006516247A priority patent/JP2006527403A/ja
Priority to EP04742242A priority patent/EP1636691A1/en
Priority to KR1020057023784A priority patent/KR100693127B1/ko
Priority to US10/560,408 priority patent/US20070115203A1/en
Publication of FI20035096A publication Critical patent/FI20035096A/sv
Application granted granted Critical
Publication of FI115006B publication Critical patent/FI115006B/sv

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/04—Exchange of auxiliary data, i.e. other than image data, between monitor and graphics controller

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Computer Hardware Design (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Digital Computer Display Output (AREA)
  • Controls And Circuits For Display Device (AREA)
FI20035096A 2003-06-13 2003-06-13 Metod och anordning för ankoppling förbättrad gränsskikt i mellan av dataskärm och processor FI115006B (sv)

Priority Applications (7)

Application Number Priority Date Filing Date Title
FI20035096A FI115006B (sv) 2003-06-13 2003-06-13 Metod och anordning för ankoppling förbättrad gränsskikt i mellan av dataskärm och processor
CNB2004800163041A CN100429615C (zh) 2003-06-13 2004-06-14 将改进的显示设备接口安装在显示设备与处理器之间的方法和装置
PCT/FI2004/050092 WO2004111829A1 (en) 2003-06-13 2004-06-14 Method and arrangement for fitting an improved display device interface between a dispaly device and a processor
JP2006516247A JP2006527403A (ja) 2003-06-13 2004-06-14 ディスプレイ装置とプロセッサとの間に改良ディスプレイ装置インターフェースを適合するための方法及び装置
EP04742242A EP1636691A1 (en) 2003-06-13 2004-06-14 Method and arrangement for fitting an improved display device interface between a dispaly device and a processor
KR1020057023784A KR100693127B1 (ko) 2003-06-13 2004-06-14 디스플레이 디바이스 및 프로세서 간에 개선된 디스플레이디바이스 인터페이스를 피팅하기 위한 방법 및 장치
US10/560,408 US20070115203A1 (en) 2003-06-13 2004-06-14 Method and arrangement for fitting an improved display device interface between a display device and a processor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FI20035096 2003-06-13
FI20035096A FI115006B (sv) 2003-06-13 2003-06-13 Metod och anordning för ankoppling förbättrad gränsskikt i mellan av dataskärm och processor

Publications (3)

Publication Number Publication Date
FI20035096A0 FI20035096A0 (sv) 2003-06-13
FI20035096A FI20035096A (sv) 2004-12-14
FI115006B true FI115006B (sv) 2005-02-15

Family

ID=8566429

Family Applications (1)

Application Number Title Priority Date Filing Date
FI20035096A FI115006B (sv) 2003-06-13 2003-06-13 Metod och anordning för ankoppling förbättrad gränsskikt i mellan av dataskärm och processor

Country Status (7)

Country Link
US (1) US20070115203A1 (sv)
EP (1) EP1636691A1 (sv)
JP (1) JP2006527403A (sv)
KR (1) KR100693127B1 (sv)
CN (1) CN100429615C (sv)
FI (1) FI115006B (sv)
WO (1) WO2004111829A1 (sv)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114328311B (zh) * 2021-12-15 2024-09-06 珠海一微半导体股份有限公司 一种存储控制器架构、数据处理电路及数据处理方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0762794B2 (ja) * 1985-09-13 1995-07-05 株式会社日立製作所 グラフイツク表示装置
US5250940A (en) * 1991-01-18 1993-10-05 National Semiconductor Corporation Multi-mode home terminal system that utilizes a single embedded general purpose/DSP processor and a single random access memory
US5450542A (en) * 1993-11-30 1995-09-12 Vlsi Technology, Inc. Bus interface with graphics and system paths for an integrated memory system
JP3106872B2 (ja) * 1994-09-02 2000-11-06 株式会社日立製作所 画像処理プロセッサ及びそれを用いたデータ処理システム
US5790881A (en) * 1995-02-07 1998-08-04 Sigma Designs, Inc. Computer system including coprocessor devices simulating memory interfaces
US5854637A (en) * 1995-08-17 1998-12-29 Intel Corporation Method and apparatus for managing access to a computer system memory shared by a graphics controller and a memory controller
US6760444B1 (en) * 1999-01-08 2004-07-06 Cisco Technology, Inc. Mobile IP authentication
US6597329B1 (en) * 1999-01-08 2003-07-22 Intel Corporation Readable matrix addressable display system
JP3105884B2 (ja) * 1999-03-31 2000-11-06 新潟日本電気株式会社 メモリ性表示装置用表示コントローラ
JP4058888B2 (ja) * 1999-11-29 2008-03-12 セイコーエプソン株式会社 Ｒａｍ内蔵ドライバ並びにそれを用いた表示ユニットおよび電子機器
JP2002311918A (ja) * 2001-04-18 2002-10-25 Seiko Epson Corp 液晶表示装置
EP1318457B1 (en) * 2001-12-07 2007-07-18 Renesas Technology Europe Limited Bus bridge with a burst transfer mode bus and a single transfer mode bus

Also Published As

Publication number Publication date
EP1636691A1 (en) 2006-03-22
CN100429615C (zh) 2008-10-29
KR100693127B1 (ko) 2007-03-13
JP2006527403A (ja) 2006-11-30
FI20035096A0 (sv) 2003-06-13
US20070115203A1 (en) 2007-05-24
CN1806223A (zh) 2006-07-19
WO2004111829A1 (en) 2004-12-23
KR20060023553A (ko) 2006-03-14
FI20035096A (sv) 2004-12-14

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