ES8307054A1 - Sistema de procesamiento de errores para un deposito de memoria de tipo buffer. - Google Patents

Sistema de procesamiento de errores para un deposito de memoria de tipo buffer.

Info

Publication number
ES8307054A1
ES8307054A1 ES515283A ES515283A ES8307054A1 ES 8307054 A1 ES8307054 A1 ES 8307054A1 ES 515283 A ES515283 A ES 515283A ES 515283 A ES515283 A ES 515283A ES 8307054 A1 ES8307054 A1 ES 8307054A1
Authority
ES
Spain
Prior art keywords
block
replaced
processing system
error processing
buffer store
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES515283A
Other languages
English (en)
Other versions
ES515283A0 (es
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of ES8307054A1 publication Critical patent/ES8307054A1/es
Publication of ES515283A0 publication Critical patent/ES515283A0/es
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/126—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1032—Reliability improvement, data loss prevention, degraded operation etc

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Debugging And Monitoring (AREA)

Abstract

SISTEMA DE PROCESAMIENTO DE ERRORES PARA UN DEPOSITO DE MEMORIA DE TIPO BUFFER. COMPRENDE: MEDIOS DETECTORES DE ERROR PARESTADO, EN QUE LOS MEDIOS DESIGNADORES DE BLOQUE A REEMPLAZAR NO DESIGNAN EL BLOQUE QUE DEBE SER REEMPLAZADO; Y SEGUNDOS MEDIOS DESIGNADORES DE BLOQUE A REEMPLAZAR, PARA DESIGNAR UN BLOQUE QUE DEBA SER REEMPLAZADO, BASADO EN LOGICA DIFERENTE DE LA LOGICA LRU. EL BLOQUE DESIGNADO POR EL SEGUNDO MEDIO DESIGNADOR SE DESIGNA COMO BLOQUE A REEMPLAZAR EN RESPUESTA A LA DETECCION DE UN ERROR POR EL DETECTOR.
ES515283A 1981-08-27 1982-08-26 Sistema de procesamiento de errores para un deposito de memoria de tipo buffer. Granted ES515283A0 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56134572A JPS6049950B2 (ja) 1981-08-27 1981-08-27 Ｌｒｕエラ−処理方式

Publications (2)

Publication Number Publication Date
ES8307054A1 true ES8307054A1 (es) 1983-06-16
ES515283A0 ES515283A0 (es) 1983-06-16

Family

ID=15131476

Family Applications (1)

Application Number Title Priority Date Filing Date
ES515283A Granted ES515283A0 (es) 1981-08-27 1982-08-26 Sistema de procesamiento de errores para un deposito de memoria de tipo buffer.

Country Status (9)

Country Link
US (1) US4507729A (es)
EP (1) EP0073666B1 (es)
JP (1) JPS6049950B2 (es)
KR (1) KR880000300B1 (es)
AU (1) AU553410B2 (es)
BR (1) BR8205042A (es)
CA (1) CA1182925A (es)
DE (1) DE3277555D1 (es)
ES (1) ES515283A0 (es)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0173556A3 (en) * 1984-08-31 1987-05-27 Texas Instruments Incorporated Hierarchical architecture for determining the least recently used cache memory
US5146604A (en) * 1986-06-06 1992-09-08 Canon Kabushiki Kaisha Information filing apparatus that stores and erases information based on frequency of its use
JPH0679297B2 (ja) * 1987-02-09 1994-10-05 日本電気アイシーマイコンシステム株式会社 順序記憶制御回路
JPS63240959A (ja) * 1987-03-28 1988-10-06 Toshio Takagi 散水用ノズル
JPS63257854A (ja) * 1987-04-15 1988-10-25 Nec Corp Ｌｒｕメモリ障害検出回路
US5136706A (en) * 1987-04-30 1992-08-04 Texas Instruments Incorporated Adaptive memory management system for collection of garbage in a digital computer
JPH01314359A (ja) * 1988-06-14 1989-12-19 Mitsubishi Electric Corp 最優劣決定回路
US5140690A (en) * 1988-06-14 1992-08-18 Mitsubishi Denki Kabushiki Kaisha Least-recently-used circuit
FR2645986B1 (fr) * 1989-04-13 1994-06-17 Bull Sa Procede pour accelerer les acces memoire d'un systeme informatique et systeme pour la mise en oeuvre du procede
JPH0640977B2 (ja) * 1992-02-13 1994-06-01 寿雄 高城 散水用ノズル
US5471605A (en) * 1992-08-27 1995-11-28 Intel Corporation Apparatus for updating a multi-way set associative cache memory status array
US5606688A (en) * 1994-08-31 1997-02-25 International Business Machines Corporation Method and apparatus for dynamic cache memory allocation via single-reference residency times
US5978888A (en) * 1997-04-14 1999-11-02 International Business Machines Corporation Hardware-managed programmable associativity caching mechanism monitoring cache misses to selectively implement multiple associativity levels
US6026470A (en) * 1997-04-14 2000-02-15 International Business Machines Corporation Software-managed programmable associativity caching mechanism monitoring cache misses to selectively implement multiple associativity levels
US6571317B2 (en) * 2001-05-01 2003-05-27 Broadcom Corporation Replacement data error detector
JP4369524B2 (ja) 2006-02-27 2009-11-25 富士通株式会社 Ｌｒｕ制御装置およびｌｒｕ制御プログラム
US8806294B2 (en) * 2012-04-20 2014-08-12 Freescale Semiconductor, Inc. Error detection within a memory

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3588829A (en) * 1968-11-14 1971-06-28 Ibm Integrated memory system with block transfer to a buffer store
FR116049A (es) * 1975-03-20
US4092713A (en) * 1977-06-13 1978-05-30 Sperry Rand Corporation Post-write address word correction in cache memory system
US4168541A (en) * 1978-09-25 1979-09-18 Sperry Rand Corporation Paired least recently used block replacement system
JPS55157181A (en) * 1979-05-25 1980-12-06 Nec Corp Buffer memory control system

Also Published As

Publication number Publication date
CA1182925A (en) 1985-02-19
EP0073666A2 (en) 1983-03-09
EP0073666B1 (en) 1987-10-28
JPS6049950B2 (ja) 1985-11-06
KR840001349A (ko) 1984-04-30
DE3277555D1 (en) 1987-12-03
BR8205042A (pt) 1983-08-09
AU8775182A (en) 1983-03-03
AU553410B2 (en) 1986-07-17
US4507729A (en) 1985-03-26
KR880000300B1 (ko) 1988-03-19
JPS5845682A (ja) 1983-03-16
EP0073666A3 (en) 1984-09-05
ES515283A0 (es) 1983-06-16

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Legal Events

Date Code Title Description
FD1A Patent lapsed

Effective date: 20040601