ES458311A1 - Unos controles de anticipacion de traductor para uso con unamemoria principal dotada de una pluralidad de distintas uni-dades de almacenaje o memoria. - Google Patents

Unos controles de anticipacion de traductor para uso con unamemoria principal dotada de una pluralidad de distintas uni-dades de almacenaje o memoria.

Info

Publication number
ES458311A1
ES458311A1 ES458311A ES458311A ES458311A1 ES 458311 A1 ES458311 A1 ES 458311A1 ES 458311 A ES458311 A ES 458311A ES 458311 A ES458311 A ES 458311A ES 458311 A1 ES458311 A1 ES 458311A1
Authority
ES
Spain
Prior art keywords
lookahead
translator
controls
address
loaded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES458311A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of ES458311A1 publication Critical patent/ES458311A1/es
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0292—User address space allocation, e.g. contiguous or non contiguous base addressing using tables or multilevel address translation means

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Memory System (AREA)
  • Storage Device Security (AREA)

Abstract

Unos controles de anticipación de traductor para uso con una memoria principal dotada de una pluralidad de distintas unidades de almacenaje o memoria, comprendiendo dichos controles d e anticipación lo siguiente: una pluralidad de registros de segmentación, para traducir una parte de una dirección lógica de acceso, dada como entrada, poniéndola en unas direcciones físicas de bloque contenidas en los registros de segmentación.
ES458311A 1976-04-30 1977-04-29 Unos controles de anticipacion de traductor para uso con unamemoria principal dotada de una pluralidad de distintas uni-dades de almacenaje o memoria. Expired ES458311A1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/682,227 US4050094A (en) 1976-04-30 1976-04-30 Translator lookahead controls

Publications (1)

Publication Number Publication Date
ES458311A1 true ES458311A1 (es) 1978-02-16

Family

ID=24738761

Family Applications (1)

Application Number Title Priority Date Filing Date
ES458311A Expired ES458311A1 (es) 1976-04-30 1977-04-29 Unos controles de anticipacion de traductor para uso con unamemoria principal dotada de una pluralidad de distintas uni-dades de almacenaje o memoria.

Country Status (9)

Country Link
US (1) US4050094A (es)
JP (1) JPS5821308B2 (es)
AU (1) AU506130B2 (es)
BR (1) BR7702777A (es)
CA (1) CA1078069A (es)
ES (1) ES458311A1 (es)
FR (1) FR2349878A1 (es)
GB (1) GB1557114A (es)
SE (1) SE417651B (es)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4170039A (en) * 1978-07-17 1979-10-02 International Business Machines Corporation Virtual address translation speed up technique
US4236205A (en) * 1978-10-23 1980-11-25 International Business Machines Corporation Access-time reduction control circuit and process for digital storage devices
JPH0658646B2 (ja) * 1982-12-30 1994-08-03 インタ−ナショナル・ビジネス・マシ−ンズ・コ−ポレ−ション デ−タ持続性が制御される仮想記憶アドレス変換機構
JPS60156151A (ja) * 1983-12-23 1985-08-16 Nec Corp メモリアクセス制御装置
IT1216085B (it) * 1988-03-15 1990-02-22 Honeywell Bull Spa Apparato di selezione veloce di memoria locale.
US4969085A (en) * 1988-08-03 1990-11-06 Intellignet Computer Engineering Memory module for a memory-managed computer system
US5099415A (en) * 1989-02-15 1992-03-24 International Business Machines Guess mechanism for virtual address translation
JPH0679296B2 (ja) * 1989-09-22 1994-10-05 株式会社日立製作所 多重仮想アドレス空間アクセス方法およびデータ処理装置
US5590297A (en) * 1994-01-04 1996-12-31 Intel Corporation Address generation unit with segmented addresses in a mircroprocessor
US5680578A (en) * 1995-06-07 1997-10-21 Advanced Micro Devices, Inc. Microprocessor using an instruction field to specify expanded functionality and a computer system employing same
US5768574A (en) * 1995-06-07 1998-06-16 Advanced Micro Devices, Inc. Microprocessor using an instruction field to expand the condition flags and a computer system employing the microprocessor
US5822778A (en) * 1995-06-07 1998-10-13 Advanced Micro Devices, Inc. Microprocessor and method of using a segment override prefix instruction field to expand the register file
KR0176637B1 (ko) * 1995-12-30 1999-04-15 김광호 디스크 콘트롤러의 프로그래머블 콘트롤 시퀀서와 그의 맵 할당방법
KR0159435B1 (ko) * 1995-12-30 1998-12-15 김광호 디스크 콘트롤러의 프로그래머블 콘트롤 시퀀서와 그의 맵 할당방법
US5819080A (en) * 1996-01-02 1998-10-06 Advanced Micro Devices, Inc. Microprocessor using an instruction field to specify condition flags for use with branch instructions and a computer system employing the microprocessor
US6230259B1 (en) 1997-10-31 2001-05-08 Advanced Micro Devices, Inc. Transparent extended state save
US6157996A (en) * 1997-11-13 2000-12-05 Advanced Micro Devices, Inc. Processor programably configurable to execute enhanced variable byte length instructions including predicated execution, three operand addressing, and increased register space
US6981132B2 (en) 2000-08-09 2005-12-27 Advanced Micro Devices, Inc. Uniform register addressing using prefix byte
US6877084B1 (en) 2000-08-09 2005-04-05 Advanced Micro Devices, Inc. Central processing unit (CPU) accessing an extended register set in an extended register mode

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3533075A (en) * 1967-10-19 1970-10-06 Ibm Dynamic address translation unit with look-ahead
US3699533A (en) * 1970-10-29 1972-10-17 Rca Corp Memory system including buffer memories
FR130806A (es) * 1973-11-21

Also Published As

Publication number Publication date
JPS5821308B2 (ja) 1983-04-28
SE417651B (sv) 1981-03-30
FR2349878B1 (es) 1978-12-29
US4050094A (en) 1977-09-20
BR7702777A (pt) 1978-02-28
GB1557114A (en) 1979-12-05
JPS52133728A (en) 1977-11-09
FR2349878A1 (fr) 1977-11-25
CA1078069A (en) 1980-05-20
AU2474177A (en) 1978-11-09
SE7704967L (sv) 1977-10-31
AU506130B2 (en) 1979-12-13

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