JPS57100677A - Data processor - Google Patents

Data processor

Info

Publication number
JPS57100677A
JPS57100677A JP55174674A JP17467480A JPS57100677A JP S57100677 A JPS57100677 A JP S57100677A JP 55174674 A JP55174674 A JP 55174674A JP 17467480 A JP17467480 A JP 17467480A JP S57100677 A JPS57100677 A JP S57100677A
Authority
JP
Japan
Prior art keywords
address
register
actual
rewriting operation
address conversion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55174674A
Other languages
Japanese (ja)
Inventor
Akira Sakauchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP55174674A priority Critical patent/JPS57100677A/en
Publication of JPS57100677A publication Critical patent/JPS57100677A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To shorten address conversion time by holding an actual address converted from a virtual address and by using it for rewriting operation. CONSTITUTION:A virtual address set in a virtual address register 11 under the control of an address conversion control part 12 is converted into an actual address through an address conversion block 13, etc., and it is stored in an actual address register 14. The address stored in this register 14 is used to access a main memory and even after the access, the actual address is held in the register 14. Then, the control part 12 advances the held address of the register 14 and it is used for rewriting operation. Therefore, the rewriting operation is performed without address conversion, etc., to shorten address conversion time, thus speeding data processing.
JP55174674A 1980-12-12 1980-12-12 Data processor Pending JPS57100677A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55174674A JPS57100677A (en) 1980-12-12 1980-12-12 Data processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55174674A JPS57100677A (en) 1980-12-12 1980-12-12 Data processor

Publications (1)

Publication Number Publication Date
JPS57100677A true JPS57100677A (en) 1982-06-22

Family

ID=15982704

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55174674A Pending JPS57100677A (en) 1980-12-12 1980-12-12 Data processor

Country Status (1)

Country Link
JP (1) JPS57100677A (en)

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