ES2170272T3 - Carcasa de matriz de protuberancias polimeras para sistemas de conexiones de microondas. - Google Patents

Carcasa de matriz de protuberancias polimeras para sistemas de conexiones de microondas.

Info

Publication number
ES2170272T3
ES2170272T3 ES96934617T ES96934617T ES2170272T3 ES 2170272 T3 ES2170272 T3 ES 2170272T3 ES 96934617 T ES96934617 T ES 96934617T ES 96934617 T ES96934617 T ES 96934617T ES 2170272 T3 ES2170272 T3 ES 2170272T3
Authority
ES
Spain
Prior art keywords
metal layer
substrate
structured metal
connections
tacos
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES96934617T
Other languages
English (en)
Inventor
Ann Dumoulin
Marcel Heerman
Jean Roggen
Eric Beyne
Hoof Rita Van
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens NV SA
Interuniversitair Microelektronica Centrum vzw IMEC
Original Assignee
Siemens NV SA
Interuniversitair Microelektronica Centrum vzw IMEC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens NV SA, Interuniversitair Microelektronica Centrum vzw IMEC filed Critical Siemens NV SA
Application granted granted Critical
Publication of ES2170272T3 publication Critical patent/ES2170272T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/20—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Structure Of Printed Boards (AREA)
  • Injection Moulding Of Plastics Or The Like (AREA)
  • Combinations Of Printed Boards (AREA)
  • Fittings On The Vehicle Exterior For Carrying Loads, And Devices For Holding Or Mounting Articles (AREA)
  • Casings For Electric Apparatus (AREA)
  • Radar Systems Or Details Thereof (AREA)
  • Waveguides (AREA)

Abstract

SE PROPONE UN DISPOSITIVO EN REJILLA DE TACOS POLIMERICOS PARA DISPOSICIONES DE CIRCUITOS DE MICROONDAS, CON UN SUSTRATO TRIDIMENSIONAL (S) DE FUNDICION INYECTADA A PARTIR DE UN POLIMERO ELECTRICAMENTE AISLANTE, TACOS POLIMERICOS (PS) DISPUESTOS SUPERFICIALMENTE SOBRE LA CARA INFERIOR DEL SUSTRATO (S) Y MOLDEADOS TAMBIEN DURANTE LA FUNDICION INYECTADA, CONEXIONES DE SEÑAL (SA) FORMADAS SOBRE VARIOS TACOS POLIMERICOS (PS) MEDIANTE UNA SUPERFICIE EXTREMA SOLDABLE, UNA CONEXION DE POTENCIA (PA) FORMADA SOBRE AL MENOS UN TACO POLIMERICO (PS) MEDIANTE UNA SUPERFICIE EXTREMA SOLDABLE, CONDUCTORES DE TIRA (SL) CONFORMADOS SOBRE LA CARA INFERIOR DEL SUSTRATO (S), QUE ESTAN FORMADOS POR UNA PRIMERA CAPA METALICA ESTRUCTURADA (MS1), UNA CAPA DIELECTRICA (DE1) Y UNA SEGUNDA CAPA METALICA ESTRUCTURADA (MS2), ESTANDO UNIDA DE FORMA ELECTRICAMENTE CONDUCTORA LA PRIMERA CAPA METALICA ESTRUCTURADA (MS1) A LA CONEXION DE POTENCIA (PA), Y UNIENDO LA SEGUNDA CAPA METALICA ESTRUCTURADA (MS2) DE LOS CONDUCTOS DE TIRA (SL) LAS CONEXIONES DE SEÑAL (SA) A UNAS CONEXIONES INTERIORES SUBORDINADAS (IA), Y CON AL MENOS UN CIRCUITO DE CONMUTACION DE MICROONDAS INTEGRADO (MIC) DISPUESTO SOBRE EL SUSTRATO (S), CUYAS CONEXIONES ESTAN UNIDAS DE FORMA ELECTRICAMENTE CONDUCTORA A LAS CONEXIONES INTERIORES (IA).
ES96934617T 1995-10-16 1996-10-10 Carcasa de matriz de protuberancias polimeras para sistemas de conexiones de microondas. Expired - Lifetime ES2170272T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19538465 1995-10-16

Publications (1)

Publication Number Publication Date
ES2170272T3 true ES2170272T3 (es) 2002-08-01

Family

ID=7774970

Family Applications (1)

Application Number Title Priority Date Filing Date
ES96934617T Expired - Lifetime ES2170272T3 (es) 1995-10-16 1996-10-10 Carcasa de matriz de protuberancias polimeras para sistemas de conexiones de microondas.

Country Status (8)

Country Link
US (1) US6130478A (es)
EP (1) EP0856198B1 (es)
JP (1) JP3011772B2 (es)
KR (1) KR100421301B1 (es)
AT (1) ATE211586T1 (es)
DE (1) DE59608615D1 (es)
ES (1) ES2170272T3 (es)
WO (1) WO1997015077A1 (es)

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US6250192B1 (en) 1996-11-12 2001-06-26 Micron Technology, Inc. Method for sawing wafers employing multiple indexing techniques for multiple die dimensions
US6493934B2 (en) 1996-11-12 2002-12-17 Salman Akram Method for sawing wafers employing multiple indexing techniques for multiple die dimensions
JP3543189B2 (ja) * 1997-12-10 2004-07-14 日本オプネクスト株式会社 半導体素子パッケージおよび半導体装置
WO1999064195A2 (en) 1998-06-05 1999-12-16 Dsm N.V. Curved ceramic moulded part
DE19921867C2 (de) * 1999-05-11 2001-08-30 Infineon Technologies Ag Verfahren zur Herstellung eines Halbleiterbauelements mit mindestens einem verkapselten Chip auf einem Substrat
US20020140096A1 (en) * 2001-03-30 2002-10-03 Siemens Dematic Electronics Assembly Systems, Inc. Method and structure for ex-situ polymer stud grid array contact formation
US6888240B2 (en) * 2001-04-30 2005-05-03 Intel Corporation High performance, low cost microelectronic circuit package with interposer
US6894399B2 (en) 2001-04-30 2005-05-17 Intel Corporation Microelectronic device having signal distribution functionality on an interfacial layer thereof
US20020167804A1 (en) * 2001-05-14 2002-11-14 Intel Corporation Polymeric encapsulation material with fibrous filler for use in microelectronic circuit packaging
US7071024B2 (en) * 2001-05-21 2006-07-04 Intel Corporation Method for packaging a microelectronic device using on-die bond pad expansion
US7183658B2 (en) * 2001-09-05 2007-02-27 Intel Corporation Low cost microelectronic circuit package
US20030057544A1 (en) * 2001-09-13 2003-03-27 Nathan Richard J. Integrated assembly protocol
US20030059976A1 (en) * 2001-09-24 2003-03-27 Nathan Richard J. Integrated package and methods for making same
US6638082B2 (en) 2001-11-20 2003-10-28 Fci Americas Technology, Inc. Pin-grid-array electrical connector
US6666693B2 (en) 2001-11-20 2003-12-23 Fci Americas Technology, Inc. Surface-mounted right-angle electrical connector
US20030153119A1 (en) * 2002-02-14 2003-08-14 Nathan Richard J. Integrated circuit package and method for fabrication
US6903458B1 (en) 2002-06-20 2005-06-07 Richard J. Nathan Embedded carrier for an integrated circuit chip
US6731189B2 (en) * 2002-06-27 2004-05-04 Raytheon Company Multilayer stripline radio frequency circuits and interconnection methods
US20050031840A1 (en) * 2003-08-05 2005-02-10 Xerox Corporation RF connector
US7052763B2 (en) * 2003-08-05 2006-05-30 Xerox Corporation Multi-element connector
JP2005353740A (ja) 2004-06-09 2005-12-22 Toshiba Corp 半導体素子及び半導体装置
US20170356640A1 (en) * 2016-06-10 2017-12-14 Innotec, Corp. Illumination assembly including thermal energy management

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3271507A (en) * 1965-11-02 1966-09-06 Alloys Unltd Inc Flat package for semiconductors
US3483308A (en) * 1968-10-24 1969-12-09 Texas Instruments Inc Modular packages for semiconductor devices
AU2073088A (en) * 1987-07-01 1989-01-30 Western Digital Corporation Plated plastic castellated interconnect for electrical components
DE3732249A1 (de) * 1987-09-24 1989-04-13 Siemens Ag Verfahren zur herstellung von dreidimensionalen leiterplatten
US5072283A (en) * 1988-04-12 1991-12-10 Bolger Justin C Pre-formed chip carrier cavity package
US4943346A (en) * 1988-09-29 1990-07-24 Siemens Aktiengesellschaft Method for manufacturing printed circuit boards
US5280194A (en) * 1988-11-21 1994-01-18 Micro Technology Partners Electrical apparatus with a metallic layer coupled to a lower region of a substrate and metallic layer coupled to a lower region of a semiconductor device
US5081520A (en) * 1989-05-16 1992-01-14 Minolta Camera Kabushiki Kaisha Chip mounting substrate having an integral molded projection and conductive pattern
US5206712A (en) * 1990-04-05 1993-04-27 General Electric Company Building block approach to microwave modules
WO1992002040A1 (en) * 1990-07-25 1992-02-06 Dsm N.V. Package for incorporating an integrated circuit and a process for the production of the package
DE69318879T2 (de) * 1992-04-03 1998-10-08 Matsushita Electric Ind Co Ltd Keramisches Mehrschicht-Substrat für hohe Frequenzen
US5338970A (en) * 1993-03-24 1994-08-16 Intergraph Corporation Multi-layered integrated circuit package with improved high frequency performance
DE59403626D1 (de) * 1993-09-29 1997-09-11 Siemens Nv Verfahren zur Herstellung einer zwei- oder mehrlagigen Verdrahtung und danach hergestellte zwei- oder mehrlagige Verdrahtung
US5629835A (en) * 1994-07-19 1997-05-13 Olin Corporation Metal ball grid array package with improved thermal conductivity
JP3112949B2 (ja) * 1994-09-23 2000-11-27 シーメンス エヌ フェー ポリマースタッドグリッドアレイ

Also Published As

Publication number Publication date
JP3011772B2 (ja) 2000-02-21
ATE211586T1 (de) 2002-01-15
US6130478A (en) 2000-10-10
WO1997015077A1 (de) 1997-04-24
EP0856198B1 (de) 2002-01-02
EP0856198A1 (de) 1998-08-05
DE59608615D1 (de) 2002-02-28
KR100421301B1 (ko) 2004-09-18
KR19990064243A (ko) 1999-07-26
JPH10512402A (ja) 1998-11-24

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