ES2143932A1 - Mejoras introducidas en el procedimiento de fabricacion de circuitos impresos objeto de la patente principal n. 9700184 (8) por un procedimiento de fabricacion de circuitos impresos. - Google Patents

Mejoras introducidas en el procedimiento de fabricacion de circuitos impresos objeto de la patente principal n. 9700184 (8) por un procedimiento de fabricacion de circuitos impresos.

Info

Publication number
ES2143932A1
ES2143932A1 ES009702533A ES9702533A ES2143932A1 ES 2143932 A1 ES2143932 A1 ES 2143932A1 ES 009702533 A ES009702533 A ES 009702533A ES 9702533 A ES9702533 A ES 9702533A ES 2143932 A1 ES2143932 A1 ES 2143932A1
Authority
ES
Spain
Prior art keywords
same
manufacturing process
produce
printed circuits
double
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
ES009702533A
Other languages
English (en)
Other versions
ES2143932B1 (es
Inventor
Nieto Rodolfo Kroebel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lear Automotive EEDS Spain SL
Original Assignee
Lear Automotive EEDS Spain SL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lear Automotive EEDS Spain SL filed Critical Lear Automotive EEDS Spain SL
Priority to JP2000524962A priority Critical patent/JP2002503878A/ja
Priority to KR1020007005566A priority patent/KR20010015829A/ko
Priority to PCT/US1998/025395 priority patent/WO1999030541A1/en
Priority to EP98500259A priority patent/EP0923278A1/fr
Publication of ES2143932A1 publication Critical patent/ES2143932A1/es
Application granted granted Critical
Publication of ES2143932B1 publication Critical patent/ES2143932B1/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • H05K3/202—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using self-supporting metal foil pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09118—Moulded substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0369—Etching selective parts of a metal substrate through part of its thickness, e.g. using etch resist
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14—Related to the order of processing steps
    • H05K2203/1476—Same or similar kind of process performed in phases, e.g. coarse patterning followed by fine patterning

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Injection Moulding Of Plastics Or The Like (AREA)
  • Structure Of Printed Boards (AREA)
  • Laminated Bodies (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)

Abstract

Mejoras introducidas en el procedimiento de fabricación de circuitos impresos objeto de la patente principal nº 9700184(8) por un procedimiento de fabricación de circuitos impresos. El procedimiento se iniciará tal y como se describe en la patente principal con el mecanizado de una lámina de cobre por su base superior de manera que con los procedimientos de corte o fresado químico se producirán en la misma unos surcos o entrepistas, ello se efectuará por partida doble, es decir, utilizándose dos láminas de cobre, las que una vez mecanizadas por las formas descritas y mediante los medios adecuados se inmovilizarán para producir el dieléctrico entre las mismas a base de un moldeo o inyección o método similar, con lo cual se evitará la doble producción de sustrato dieléctrico y posterior enganchado del mismo.
ES9702533A 1997-01-31 1997-12-05 Mejoras introducidas en el procedimiento de fabricacion de circuitos impresos objeto de la patente principal n. 9700184 (8) por un procedimiento de fabricacion de circuitos impresos. Expired - Lifetime ES2143932B1 (es)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2000524962A JP2002503878A (ja) 1997-12-05 1998-11-30 プリント回路及び製造方法
KR1020007005566A KR20010015829A (ko) 1997-12-05 1998-11-30 인쇄회로와 제조방법
PCT/US1998/025395 WO1999030541A1 (en) 1997-12-05 1998-11-30 Printed circuits and method for making
EP98500259A EP0923278A1 (fr) 1997-12-05 1998-12-01 Procédé de fabrication de circuits imprimés

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
ES9700184A ES2125821B1 (es) 1997-01-31 1997-01-31 Un procedimiento de fabricacion de circuitos impresos.

Publications (2)

Publication Number Publication Date
ES2143932A1 true ES2143932A1 (es) 2000-05-16
ES2143932B1 ES2143932B1 (es) 2000-12-01

Family

ID=8298051

Family Applications (2)

Application Number Title Priority Date Filing Date
ES9700184A Expired - Lifetime ES2125821B1 (es) 1997-01-31 1997-01-31 Un procedimiento de fabricacion de circuitos impresos.
ES9702533A Expired - Lifetime ES2143932B1 (es) 1997-01-31 1997-12-05 Mejoras introducidas en el procedimiento de fabricacion de circuitos impresos objeto de la patente principal n. 9700184 (8) por un procedimiento de fabricacion de circuitos impresos.

Family Applications Before (1)

Application Number Title Priority Date Filing Date
ES9700184A Expired - Lifetime ES2125821B1 (es) 1997-01-31 1997-01-31 Un procedimiento de fabricacion de circuitos impresos.

Country Status (6)

Country Link
EP (1) EP0857010B1 (es)
JP (1) JPH10224011A (es)
CA (1) CA2279340A1 (es)
DE (1) DE69735750T2 (es)
ES (2) ES2125821B1 (es)
WO (1) WO1998034444A1 (es)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010015829A (ko) * 1997-12-05 2001-02-26 리어 오토모티브 디어본 , 인코포레이티드. 인쇄회로와 제조방법
EP1257157B1 (en) 1999-12-31 2004-11-24 Lear Automotive (EEDS) Spain, S.L. Method for manufacturing printed circuit boards
ES2188381B1 (es) * 2001-06-05 2004-12-16 Lear Automotive (Eeds) Spain, S.L. Procedimiento de fabricacion de placas de circuito impreso a partir de un polimero extrusionado.
CN105282974B (zh) * 2015-10-14 2018-05-11 深圳崇达多层线路板有限公司 一种阶梯式印制电路板的制作方法
CN109195340A (zh) * 2018-09-18 2019-01-11 桑尼维尔新材料科技(南京)有限公司 一种制作金属化陶瓷基板超窄线宽、线距图形的方法
CN110098302A (zh) * 2019-05-06 2019-08-06 华南理工大学 一种用于微型led器件的柔性聚酰亚胺衬底及其制备方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3085295A (en) * 1957-04-30 1963-04-16 Michael A Pizzino Method of making inlaid circuits
DE1521770A1 (de) * 1963-03-26 1969-09-18 Haydon Switch & Instr Inc Verfahren zur Herstellung von elektrischen Schaltungsanordnungen

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1260804A (fr) * 1960-03-31 1961-05-12 Electronique & Automatisme Sa Procédé de réalisation de circuits imprimés
GB971775A (en) * 1961-07-17 1964-10-07 Borg Warner Electrical terminal board
US3177103A (en) * 1961-09-18 1965-04-06 Sauders Associates Inc Two pass etching for fabricating printed circuitry
DE1665944A1 (de) * 1967-05-13 1971-04-08 Siemens Ag Verfahren zum Herstellen elektrischer Schaltkreise
JPH02138793A (ja) * 1988-11-18 1990-05-28 Shinko Electric Ind Co Ltd 回路基板の製造方法
ES2071540B1 (es) * 1992-01-29 1996-02-01 Mecanismos Aux Ind Perfeccionamientos en los procesos de fabricacion de cajas de servicios y de sus partes.

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3085295A (en) * 1957-04-30 1963-04-16 Michael A Pizzino Method of making inlaid circuits
DE1521770A1 (de) * 1963-03-26 1969-09-18 Haydon Switch & Instr Inc Verfahren zur Herstellung von elektrischen Schaltungsanordnungen

Also Published As

Publication number Publication date
EP0857010B1 (fr) 2006-04-26
DE69735750D1 (de) 2006-06-01
ES2143932B1 (es) 2000-12-01
CA2279340A1 (en) 1998-08-06
DE69735750T2 (de) 2007-05-10
WO1998034444A1 (en) 1998-08-06
JPH10224011A (ja) 1998-08-21
ES2125821A1 (es) 1999-03-01
ES2125821B1 (es) 1999-12-01
EP0857010A1 (fr) 1998-08-05

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