ES2139583T3 - Sistema multiprocesador con memorias cache. - Google Patents

Sistema multiprocesador con memorias cache.

Info

Publication number
ES2139583T3
ES2139583T3 ES92114159T ES92114159T ES2139583T3 ES 2139583 T3 ES2139583 T3 ES 2139583T3 ES 92114159 T ES92114159 T ES 92114159T ES 92114159 T ES92114159 T ES 92114159T ES 2139583 T3 ES2139583 T3 ES 2139583T3
Authority
ES
Spain
Prior art keywords
spkm
spk1
system components
ssk
serial
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES92114159T
Other languages
English (en)
Inventor
Harald Dipl-Ing Sachs
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wincor Nixdorf International GmbH
Original Assignee
Wincor Nixdorf International GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wincor Nixdorf International GmbH filed Critical Wincor Nixdorf International GmbH
Application granted granted Critical
Publication of ES2139583T3 publication Critical patent/ES2139583T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06Q—INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
    • G06Q10/00—Administration; Management
    • G06Q10/02—Reservations, e.g. for tickets, services or events
    • G06Q10/025—Coordination of plural reservations, e.g. plural trip segments, transportation combined with accommodation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Business, Economics & Management (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tourism & Hospitality (AREA)
  • General Engineering & Computer Science (AREA)
  • Economics (AREA)
  • Development Economics (AREA)
  • Entrepreneurship & Innovation (AREA)
  • Human Resources & Organizations (AREA)
  • Marketing (AREA)
  • Operations Research (AREA)
  • Quality & Reliability (AREA)
  • Strategic Management (AREA)
  • General Business, Economics & Management (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)

Abstract

SE PROPONE UN SISTEMA MULTIPROCESADOR CON UNA MULTIPLICIDAD DE SISTEMAS BUS EN SERIE DISPUESTOS DE FORMA PARALELA, A LOS QUE PUEDEN SER CONECTADOS UNA ALTA CANTIDAD DE COMPONENTES (SPK1, SPKM, SSK) DE SISTEMA. EN LOS COMPONENTES (SPK1, SPKM, SSK) DE SISTEMA, SE TRATA DE COMPONENTES DE (SPK1, SPKM) DE SISTEMA PROCESADOR QUE MUESTRA UNA MEMORIA CACHE Y ALREDEDOR DE COMPONENTES DE SISTEMA-MEMORIA. CADA COMPONENTE (SPK1, SPKM, SSK) DE SISTEMA ESTA UNIDO CON CADA SISTEMA BUS EN SERIE. LOS COMPONENTES (SPK1, SPKM) DE SISTEMA-PROCESADOR DISPONEN PARA CADA BUS (SB1, SBN-1, SBN) DE ALTA VELOCIDAD EN SERIE, MEDIOS PARA EL MANTENIMIENTO DE LOS DERECHOS DE CONSISTENCIA DEL CONTENIDO DE LA MEMORIA CACHE.
ES92114159T 1992-08-19 1992-08-19 Sistema multiprocesador con memorias cache. Expired - Lifetime ES2139583T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP92114159A EP0587918B1 (de) 1992-08-19 1992-08-19 Multiprozessorsystem mit Cache-Speichern

Publications (1)

Publication Number Publication Date
ES2139583T3 true ES2139583T3 (es) 2000-02-16

Family

ID=8209926

Family Applications (1)

Application Number Title Priority Date Filing Date
ES92114159T Expired - Lifetime ES2139583T3 (es) 1992-08-19 1992-08-19 Sistema multiprocesador con memorias cache.

Country Status (5)

Country Link
US (1) US5829037A (es)
EP (1) EP0587918B1 (es)
AT (1) ATE186411T1 (es)
DE (1) DE59209766D1 (es)
ES (1) ES2139583T3 (es)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19524023B4 (de) * 1995-06-30 2004-02-05 Fujitsu Siemens Computers Gmbh Multiprozessorsystem mit einer sehr großen Anzahl von Mikroprozessoren
US6064497A (en) * 1996-03-08 2000-05-16 Intel Corporation Low cost digital scanners
US6330591B1 (en) * 1998-03-09 2001-12-11 Lsi Logic Corporation High speed serial line transceivers integrated into a cache controller to support coherent memory transactions in a loosely coupled network
US7213168B2 (en) * 2003-09-16 2007-05-01 Rockwell Automation Technologies, Inc. Safety controller providing for execution of standard and safety control programs
US11360906B2 (en) * 2020-08-14 2022-06-14 Alibaba Group Holding Limited Inter-device processing system with cache coherency

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4656620A (en) * 1984-09-19 1987-04-07 Itt Corporation Apparatus for obtaining reduced pin count packaging and methods
US5067071A (en) * 1985-02-27 1991-11-19 Encore Computer Corporation Multiprocessor computer system employing a plurality of tightly coupled processors with interrupt vector bus
US4794521A (en) * 1985-07-22 1988-12-27 Alliant Computer Systems Corporation Digital computer with cache capable of concurrently handling multiple accesses from parallel processors
US4785396A (en) * 1986-01-28 1988-11-15 Intel Corporation Push-pull serial bus coupled to a plurality of devices each having collision detection circuit and arbitration circuit
US4837682A (en) * 1987-04-07 1989-06-06 Glen Culler & Associates Bus arbitration system and method
JPH01253059A (ja) * 1988-04-01 1989-10-09 Kokusai Denshin Denwa Co Ltd <Kdd> 並列信号処理方式
GB8814077D0 (en) * 1988-06-14 1988-07-20 Int Computers Ltd Data memory system
DE3917715A1 (de) * 1989-05-31 1990-12-06 Teldix Gmbh Rechnersystem
US5345578A (en) * 1989-06-30 1994-09-06 Digital Equipment Corporation Competitive snoopy caching for large-scale multiprocessors
US5113514A (en) * 1989-08-22 1992-05-12 Prime Computer, Inc. System bus for multiprocessor computer system
US5191652A (en) * 1989-11-10 1993-03-02 International Business Machines Corporation Method and apparatus for exploiting communications bandwidth as for providing shared memory
JPH03223957A (ja) * 1989-12-26 1991-10-02 Hitachi Ltd 計算機
US5265235A (en) * 1990-11-30 1993-11-23 Xerox Corporation Consistency protocols for shared memory multiprocessors
US5249283A (en) * 1990-12-24 1993-09-28 Ncr Corporation Cache coherency method and apparatus for a multiple path interconnection network
US5410654A (en) * 1991-07-22 1995-04-25 International Business Machines Corporation Interface with address decoder for selectively generating first and second address and control signals respectively in response to received address and control signals
DE69227996T2 (de) * 1991-07-26 1999-08-26 Tandem Computers Inc. Vorrichtung und verfahren zur vermittlung von datenblöcken
US5388224A (en) * 1992-04-24 1995-02-07 Digital Equipment Corporation Processor identification mechanism for a multiprocessor system
WO1994002973A1 (en) * 1992-07-24 1994-02-03 Berg Technology, Inc. Apparatus for connecting computer devices
US5434993A (en) * 1992-11-09 1995-07-18 Sun Microsystems, Inc. Methods and apparatus for creating a pending write-back controller for a cache controller on a packet switched memory bus employing dual directories
US5519832A (en) * 1992-11-13 1996-05-21 Digital Equipment Corporation Method and apparatus for displaying module diagnostic results
US5349579A (en) * 1993-01-05 1994-09-20 Excel, Inc. Telecommunication switch with programmable communications services
JPH06324977A (ja) * 1993-05-14 1994-11-25 Matsushita Electric Ind Co Ltd データ転送方法
US5475854A (en) * 1994-01-28 1995-12-12 Vlsi Technology, Inc. Serial bus I/O system and method for serializing interrupt requests and DMA requests in a computer system
US5404460A (en) * 1994-01-28 1995-04-04 Vlsi Technology, Inc. Method for configuring multiple identical serial I/O devices to unique addresses through a serial bus

Also Published As

Publication number Publication date
US5829037A (en) 1998-10-27
DE59209766D1 (de) 1999-12-09
ATE186411T1 (de) 1999-11-15
EP0587918B1 (de) 1999-11-03
EP0587918A1 (de) 1994-03-23

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