ES2102938B1 - Sistema de reduccion de fluctuaciones de fase en demultiplexores digitales. - Google Patents

Sistema de reduccion de fluctuaciones de fase en demultiplexores digitales.

Info

Publication number
ES2102938B1
ES2102938B1 ES09400667A ES9400667A ES2102938B1 ES 2102938 B1 ES2102938 B1 ES 2102938B1 ES 09400667 A ES09400667 A ES 09400667A ES 9400667 A ES9400667 A ES 9400667A ES 2102938 B1 ES2102938 B1 ES 2102938B1
Authority
ES
Spain
Prior art keywords
write
read
rck
phc
frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
ES09400667A
Other languages
English (en)
Other versions
ES2102938A1 (es
Inventor
Pinto Francisco Jose Castano
Beato Jose Vicente Rodriguez
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nokia Spain SA
Original Assignee
Alcatel Standard Electrics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel Standard Electrics SA filed Critical Alcatel Standard Electrics SA
Priority to ES09400667A priority Critical patent/ES2102938B1/es
Priority to AU14718/95A priority patent/AU697719B2/en
Priority to DE69531320T priority patent/DE69531320T2/de
Priority to AT95104189T priority patent/ATE245872T1/de
Priority to EP95104189A priority patent/EP0675613B1/en
Priority to CA002145595A priority patent/CA2145595A1/en
Priority to US08/412,129 priority patent/US5598445A/en
Publication of ES2102938A1 publication Critical patent/ES2102938A1/es
Application granted granted Critical
Publication of ES2102938B1 publication Critical patent/ES2102938B1/es
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/07—Synchronising arrangements using pulse stuffing for systems with different or fluctuating information rates or bit rates
    • H04J3/076—Bit and byte stuffing, e.g. SDH/PDH desynchronisers, bit-leaking

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Optical Communication System (AREA)
  • Manipulation Of Pulses (AREA)
  • Dc Digital Transmission (AREA)

Abstract

SISTEMA DE REDUCCION DE FLUCTUACIONES DE FASE EN DEMULTIPLEXORES DIGITALES. COMPUESTO POR UN SUBCONJUNTO DE ESCRITURA-LECTURA ELASTICA DE MEMORIA (EM, WP, WA, RP, RA), CUYO RELOJ DE LECTURA (RCK) VARIA SU FRECUENCIA CON LA SEÑAL OBTENIDO POR UN DETECTOR DE FASE (PHC) EN FUNCION DE LA DIFERENCIA TEMPORAL EN QUE DOS PUNTEROS, DE LECTURA (RP) Y ESCRITURA (WP) TOMAN RESPECTIVAMENTE UNOS VALORES DE REFERENCIA. CUANDO EL INSTANTE EN QUE EL PUNTERO DE ESCRITURA (WP) TOMA EL VALOR DE REFERENCIA DE ESCRITURA SE ADELANTA O ATRASA UN CICLO DE RELOJ DE ESCRITURA (WCK), CON RESPECTO A PERIODOS ANTERIORES, DICHA REFERENCIA SE INCREMENTA O DECREMENTO EL MISMO NUMERO DE UNIDADES, DE FORMA QUE NO SE MODIFICA LA COMPONENTE CONTINUA DE LA SEÑAL DE SALIDA DEL DETECTOR DE FASE (PHC) DE FORMA BRUSCA; SINO QUE GRADUALMENTE Y MEDIANTE FRACCIONES DE LA REFERENCIA DE LECTURA, ESTA SE INCREMENTA O SE DECREMENTO PARA PRODUCIR UNA VARIACION SUAVE DE LA FRECUENCIA DEL RELOJ DE LECTURA (RCK) QUE COMPENSA LAS DIFERENCIASDE FLUJOS NETOS DE ENTRADA Y SALIDA DE DATOS DE LA MEMORIA ELASTICA (EM).
ES09400667A 1994-03-28 1994-03-28 Sistema de reduccion de fluctuaciones de fase en demultiplexores digitales. Expired - Fee Related ES2102938B1 (es)

Priority Applications (7)

Application Number Priority Date Filing Date Title
ES09400667A ES2102938B1 (es) 1994-03-28 1994-03-28 Sistema de reduccion de fluctuaciones de fase en demultiplexores digitales.
AU14718/95A AU697719B2 (en) 1994-03-28 1995-03-08 Jitter reduction
AT95104189T ATE245872T1 (de) 1994-03-28 1995-03-22 System zur verminderung von jitter in einem digitalen demultiplexer
EP95104189A EP0675613B1 (en) 1994-03-28 1995-03-22 Jitter reduction system in digital demultiplexers
DE69531320T DE69531320T2 (de) 1994-03-28 1995-03-22 System zur Verminderung von Jitter in einem digitalen Demultiplexer
CA002145595A CA2145595A1 (en) 1994-03-28 1995-03-27 Jitter reduction system in digital demultiplexers
US08/412,129 US5598445A (en) 1994-03-28 1995-03-28 Jitter reduction system in digital demultiplexers

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
ES09400667A ES2102938B1 (es) 1994-03-28 1994-03-28 Sistema de reduccion de fluctuaciones de fase en demultiplexores digitales.

Publications (2)

Publication Number Publication Date
ES2102938A1 ES2102938A1 (es) 1997-08-01
ES2102938B1 true ES2102938B1 (es) 1998-04-16

Family

ID=8285730

Family Applications (1)

Application Number Title Priority Date Filing Date
ES09400667A Expired - Fee Related ES2102938B1 (es) 1994-03-28 1994-03-28 Sistema de reduccion de fluctuaciones de fase en demultiplexores digitales.

Country Status (7)

Country Link
US (1) US5598445A (es)
EP (1) EP0675613B1 (es)
AT (1) ATE245872T1 (es)
AU (1) AU697719B2 (es)
CA (1) CA2145595A1 (es)
DE (1) DE69531320T2 (es)
ES (1) ES2102938B1 (es)

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US5784377A (en) 1993-03-09 1998-07-21 Hubbell Incorporated Integrated digital loop carrier system with virtual tributary mapper circuit
US5883900A (en) * 1994-03-23 1999-03-16 Gpt Limited Telecommunications transmission
US5901149A (en) * 1994-11-09 1999-05-04 Sony Corporation Decode and encode system
GB9509216D0 (en) * 1995-05-05 1995-06-28 Plessey Telecomm Retiming arrangement for SDH data transmission system
US6061411A (en) * 1995-12-22 2000-05-09 Compaq Computer Corporation Method and apparatus for synchronizing a serial bus clock to a serial bus function clock
US5761203A (en) * 1996-04-04 1998-06-02 Lucent Technologies Inc. Synchronous and asynchronous recovery of signals in an ATM network
JP3442228B2 (ja) * 1996-08-29 2003-09-02 松下電器産業株式会社 同期保持装置
US6389553B1 (en) * 1998-05-26 2002-05-14 Nortel Networks Limited Redundant link delay maintenance circuit and method
US6816934B2 (en) * 2000-12-22 2004-11-09 Hewlett-Packard Development Company, L.P. Computer system with registered peripheral component interconnect device for processing extended commands and attributes according to a registered peripheral component interconnect protocol
US6512804B1 (en) 1999-04-07 2003-01-28 Applied Micro Circuits Corporation Apparatus and method for multiple serial data synchronization using channel-lock FIFO buffers optimized for jitter
US6937621B2 (en) * 2001-02-21 2005-08-30 Integrated Device Technology, Inc. Apparatus and method for determining byte gain and loss adjustments in a SONET/SDH network element
KR100770906B1 (ko) * 2006-02-10 2007-10-26 삼성전자주식회사 비디오 패킷의 출력 비트레이트 조절 방법 및 장치
US10013375B2 (en) 2014-08-04 2018-07-03 Samsung Electronics Co., Ltd. System-on-chip including asynchronous interface and driving method thereof
JP6929995B1 (ja) * 2020-06-15 2021-09-01 Ｎｔｔエレクトロニクス株式会社 データ転送回路及び通信装置

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IT1074199B (it) * 1976-12-23 1985-04-17 Italiana Telecomunicazioni Ora Memoria elastica per la soppressione del disturbo di fase (jitter)nei sistemi di trasmissione per segnali digitali
JPS6214546A (ja) * 1985-07-12 1987-01-23 Nec Corp 準同期バツフア制御方式
US5033064A (en) * 1988-12-09 1991-07-16 Transwitch Corporation Clock dejitter circuit for regenerating DS1 signal
US5359605A (en) * 1989-06-22 1994-10-25 U.S. Philips Corporation Circuit arrangement for adjusting the bit rates of two signals
DE4014815A1 (de) * 1990-05-09 1991-11-14 Ant Nachrichtentech Anordnung und verfahren zum abbilden eines ersten nutzsignals aus dem rahmen eines ersten digitalsignals mittels impulsstopftechnik in den rahmen eines zweiten digitalsignals
US5313502A (en) * 1990-05-09 1994-05-17 Ant Nachrichtentechnik Gmbh Arrangement for imaging a useful signal from the frame of a first digital signal at a first bite rate into the frame of a second digital signal at a second bite rate
DE4014814A1 (de) * 1990-05-09 1991-11-21 Ant Nachrichtentech Verfahren und anordnung zur reduktion von wartezeitjitter
DE4016189A1 (de) * 1990-05-19 1991-11-28 Philips Patentverwaltung Einrichtung zur phasenjitterreduzierung
JP2777929B2 (ja) * 1990-07-04 1998-07-23 富士通株式会社 非同期信号抽出回路
SE466474B (sv) * 1990-07-10 1992-02-17 Ericsson Telefon Ab L M Faslaasningskrets foer jitterreducering i digitalt multiplexsystem
US5052025A (en) * 1990-08-24 1991-09-24 At&T Bell Laboratories Synchronous digital signal to asynchronous digital signal desynchronizer
FR2668323B1 (fr) * 1990-10-17 1993-01-15 Telecommunications Sa Dispositif de reduction de la gigue due aux sauts de pointeurs dans un reseau de telecommunications numeriques.
IT1244350B (it) * 1990-12-21 1994-07-08 Telettra Spa Metodo per la riduzione del rumore di fase introdotto nella resincronizzazione di segnali digitali mediante giustificazione, e circuiti integrati per l'implementazione del metodo
DE69228775T2 (de) * 1991-02-08 1999-09-02 Nec Corp Verteilte Bit für Bit Entstopfungsschaltung für bytegestopfte Mehrfachrahmendaten
US5126693A (en) * 1991-09-09 1992-06-30 Motorola, Inc. Circuit and method of reducing phase jitter in a phase lock loop
US5200982A (en) * 1991-10-02 1993-04-06 Alcatel Network Systems, Inc. In-line piece-wise linear desynchronizer
US5267236A (en) * 1991-12-16 1993-11-30 Alcatel Network Systems, Inc. Asynchronous parallel data formatter
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FI90709C (fi) * 1992-02-14 1994-03-10 Nokia Telecommunications Oy Järjestely osoitinvärinän vaimentamiseksi desynkronisaattorissa
FI95636C (fi) * 1992-02-14 1996-02-26 Nokia Telecommunications Oy Desynkronisaattori ja menetelmä osoitinvärinän vaimentamiseksi desynkronisaattorissa
US5404380A (en) * 1992-08-25 1995-04-04 Alcatel Network Systems, Inc. Desynchronizer for adjusting the read data rate of payload data received over a digital communication network transmitting payload data within frames
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Also Published As

Publication number Publication date
AU1471895A (en) 1995-10-05
EP0675613A3 (en) 1998-07-08
AU697719B2 (en) 1998-10-15
EP0675613A2 (en) 1995-10-04
DE69531320T2 (de) 2004-03-04
ES2102938A1 (es) 1997-08-01
CA2145595A1 (en) 1995-09-29
US5598445A (en) 1997-01-28
ATE245872T1 (de) 2003-08-15
DE69531320D1 (de) 2003-08-28
EP0675613B1 (en) 2003-07-23

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