ES2087127T3 - Interfaz de datos asincrona de alta velocidad. - Google Patents
Interfaz de datos asincrona de alta velocidad.Info
- Publication number
- ES2087127T3 ES2087127T3 ES90302024T ES90302024T ES2087127T3 ES 2087127 T3 ES2087127 T3 ES 2087127T3 ES 90302024 T ES90302024 T ES 90302024T ES 90302024 T ES90302024 T ES 90302024T ES 2087127 T3 ES2087127 T3 ES 2087127T3
- Authority
- ES
- Spain
- Prior art keywords
- data
- clock
- transitions
- extraction
- speed asynchronous
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
- H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
- H04L25/4904—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using self-synchronising codes, e.g. split-phase codes
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/04—Speed or phase control by synchronisation signals
- H04L7/06—Speed or phase control by synchronisation signals the synchronisation signals differing from the information signals in amplitude, polarity or frequency or length
Landscapes
- Physics & Mathematics (AREA)
- Spectroscopy & Molecular Physics (AREA)
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Dc Digital Transmission (AREA)
- Communication Control (AREA)
Abstract
SE DESCRIBE UN INTERFAZ DE DATOS DIGITAL PARA TRANSFERIR DATOS ASINCRONOS DE ALTA VELOCIDAD. EL DISEÑO ESTA PENSADO NOMINALMENTE PARA INTEGRARSE EN LOS MICROCIRCUITOS COMPONENTES DE SISTEMAS DE COMUNICACIONES. EL SISTEMA SE DESCRIBE RESPECTO A SU REALIZACION EN TECNOLOGIA DE CI CMOS. LAS TECNICAS IMPLICADAS, SIN EMBARGO, PUEDEN APLICARSE FACILMENTE A OTRAS TECNOLOGIAS. EL INTERFAZ UTILIZA LA CODIFICACION MANCHESTER BI-PHASE MARK DEL RELOJ Y LOS DATOS PARA PERMITIR LA EXTRACCION DE LAS SEÑALES DEL RELOJ Y LOS DATOS EN EL RECEPTOR (7). ADEMAS, EL USO DE ESTE CODIGO MANCHESTER PERMITE QUE LAS VIOLACIONES DE CODIGO SE UTILICEN FACILMENTE COMO MARCADORES DE CUADRO PARA LOS SISTEMAS DE SINCRONIZACION. LA ESENCIA DEL CIRCUITO DE EXTRACCION DEL RELOJ Y DE DETECCION DE DATOS (9,11) ES EL USO DE ELEMENTOS DE LINEA DE RETARDO CALIBRADOS PARA SUPRIMIR LAS TRANSICIONES DE DATOS DENTRO DE LA SEÑAL DE ENTRADA CODIFICADA, PERMITIENDO ASI QUE SE DETECTE LAS TRANSICIONES DE RELOJ DESDE LAS QUE SE GENERA EL RELOJ DESPUES.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB8907152A GB2230165B (en) | 1989-03-30 | 1989-03-30 | High speed asynchronous data interface |
Publications (1)
Publication Number | Publication Date |
---|---|
ES2087127T3 true ES2087127T3 (es) | 1996-07-16 |
Family
ID=10654166
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ES90302024T Expired - Lifetime ES2087127T3 (es) | 1989-03-30 | 1990-02-26 | Interfaz de datos asincrona de alta velocidad. |
Country Status (11)
Country | Link |
---|---|
US (1) | US5050194A (es) |
EP (1) | EP0392653B1 (es) |
JP (1) | JPH0327638A (es) |
CN (1) | CN1046057A (es) |
AU (1) | AU618887B2 (es) |
CA (1) | CA2012256A1 (es) |
DE (1) | DE69026644T2 (es) |
ES (1) | ES2087127T3 (es) |
FI (1) | FI901588A0 (es) |
GB (1) | GB2230165B (es) |
PT (1) | PT93579A (es) |
Families Citing this family (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0589217A1 (en) * | 1992-09-24 | 1994-03-30 | Siemens Stromberg-Carlson | Serial line synchronization method and apparatus |
US5345186A (en) * | 1993-01-19 | 1994-09-06 | Credence Systems Corporation | Retriggered oscillator for jitter-free phase locked loop frequency synthesis |
FR2723805B1 (fr) * | 1994-08-18 | 1996-10-25 | Matra Mhs | Detecteur de transition d'un signal logique engendrant une impulsion de duree calibree. |
JPH08139577A (ja) * | 1994-11-07 | 1996-05-31 | Mitsubishi Electric Corp | 可変遅延回路 |
JP3080007B2 (ja) * | 1996-08-28 | 2000-08-21 | 日本電気株式会社 | Pll回路 |
WO1998043386A1 (en) * | 1997-03-25 | 1998-10-01 | Telefonaktiebolaget Lm Ericsson | Method and device for aligning synchronous digital signals |
US6658239B1 (en) * | 1997-05-09 | 2003-12-02 | Micrel Incorporated | Fully integrated ALL-CMOS AM transmitter with automatic antenna tuning |
US6253068B1 (en) * | 1997-05-09 | 2001-06-26 | Micrel, Incorporated | Fully integrated all-CMOS AM transmitter with automatic antenna tuning |
FR2768575B1 (fr) * | 1997-09-12 | 2004-04-09 | Sgs Thomson Microelectronics | Procede de mesure de delai temporel et circuit mettant en oeuvre le procede |
US6970435B1 (en) | 1998-06-15 | 2005-11-29 | International Business Machines Corporation | Data alignment compensator |
US7119839B1 (en) * | 1998-07-22 | 2006-10-10 | Micron Technology, Inc. | High resolution CMOS circuit using a matched impedance output transmission line |
US6363086B1 (en) * | 1998-12-03 | 2002-03-26 | Telefonaktiebolaget L M Ericsson (Publ) | Method for combining signals on a digital interface |
JP3278621B2 (ja) * | 1998-12-24 | 2002-04-30 | 松下電器産業株式会社 | データ伝送装置 |
US6597752B1 (en) * | 1999-02-24 | 2003-07-22 | Agere Systems Inc. | Method for detecting a dotting sequence for manchester encoded data in a deep fading environment |
US7158593B2 (en) * | 2001-03-16 | 2007-01-02 | Silicon Image, Inc. | Combining a clock signal and a data signal |
US7664214B2 (en) * | 2002-09-24 | 2010-02-16 | Standard Microsystems Corporation | System and method for transferring data among transceivers substantially void of data dependent jitter |
EP1404050B1 (en) * | 2002-09-25 | 2011-11-09 | Samsung Electronics Co., Ltd. | Input/output circuit for simultaneously bidirectional transmission |
US7577756B2 (en) | 2003-07-15 | 2009-08-18 | Special Devices, Inc. | Dynamically-and continuously-variable rate, asynchronous data transfer |
JP2006217171A (ja) * | 2005-02-02 | 2006-08-17 | Sanyo Electric Co Ltd | クロック抽出回路 |
JP4786262B2 (ja) * | 2005-09-06 | 2011-10-05 | ルネサスエレクトロニクス株式会社 | インターフェイス回路 |
US7487331B2 (en) * | 2005-09-15 | 2009-02-03 | Microchip Technology Incorprated | Programming a digital processor with a single connection |
CN101364960B (zh) * | 2008-07-08 | 2011-11-23 | 华亚微电子(上海)有限公司 | 高速差分接口 |
TWI489770B (zh) * | 2012-06-18 | 2015-06-21 | Via Tech Inc | 去除差分信號雜訊的電路和方法以及接收差分信號的晶片 |
US9118308B1 (en) * | 2014-02-07 | 2015-08-25 | Via Technologies, Inc. | Duty cycle corrector |
US9651572B2 (en) * | 2014-03-19 | 2017-05-16 | Infineon Technologies Ag | Speed sensor device, speed sensor method, electronic control unit and control method |
DE102014219512A1 (de) * | 2014-09-26 | 2016-03-31 | Dr. Johannes Heidenhain Gmbh | Verfahren und Vorrichtung zur seriellen Datenübertragung über einen bidirektionalen Datenübertragungskanal |
US9490964B2 (en) | 2014-11-26 | 2016-11-08 | Qualcomm Incorporated | Symbol transition clocking clock and data recovery to suppress excess clock caused by symbol glitch during stable symbol period |
CN113886300B (zh) * | 2021-09-23 | 2024-05-03 | 珠海一微半导体股份有限公司 | 一种总线接口的时钟数据自适应恢复系统及芯片 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4611335A (en) * | 1981-09-30 | 1986-09-09 | Hitachi, Ltd. | Digital data synchronizing circuit |
US4592072B1 (en) * | 1982-05-07 | 1994-02-15 | Digital Equipment Corporation | Decoder for self-clocking serial data communications |
US4513427A (en) * | 1982-08-30 | 1985-04-23 | Xerox Corporation | Data and clock recovery system for data communication controller |
JPS60145745A (ja) * | 1984-01-09 | 1985-08-01 | Nec Corp | バイフェーズ符号クロック抽出回路 |
US4675612A (en) * | 1985-06-21 | 1987-06-23 | Advanced Micro Devices, Inc. | Apparatus for synchronization of a first signal with a second signal |
US4805197A (en) * | 1986-12-18 | 1989-02-14 | Lecroy Corporation | Method and apparatus for recovering clock information from a received digital signal and for synchronizing that signal |
-
1989
- 1989-03-30 GB GB8907152A patent/GB2230165B/en not_active Expired - Fee Related
-
1990
- 1990-02-26 DE DE69026644T patent/DE69026644T2/de not_active Expired - Fee Related
- 1990-02-26 EP EP90302024A patent/EP0392653B1/en not_active Expired - Lifetime
- 1990-02-26 ES ES90302024T patent/ES2087127T3/es not_active Expired - Lifetime
- 1990-03-14 US US07/493,730 patent/US5050194A/en not_active Expired - Fee Related
- 1990-03-15 CA CA002012256A patent/CA2012256A1/en not_active Abandoned
- 1990-03-27 PT PT93579A patent/PT93579A/pt not_active Application Discontinuation
- 1990-03-28 AU AU52312/90A patent/AU618887B2/en not_active Ceased
- 1990-03-29 FI FI901588A patent/FI901588A0/fi not_active IP Right Cessation
- 1990-03-29 JP JP2082904A patent/JPH0327638A/ja active Pending
- 1990-03-30 CN CN90101835.XA patent/CN1046057A/zh active Pending
Also Published As
Publication number | Publication date |
---|---|
EP0392653A2 (en) | 1990-10-17 |
GB2230165B (en) | 1993-09-15 |
FI901588A0 (fi) | 1990-03-29 |
CA2012256A1 (en) | 1990-09-30 |
PT93579A (pt) | 1991-10-31 |
AU618887B2 (en) | 1992-01-09 |
GB8907152D0 (en) | 1989-05-10 |
EP0392653A3 (en) | 1993-06-09 |
DE69026644D1 (de) | 1996-05-30 |
AU5231290A (en) | 1990-10-04 |
EP0392653B1 (en) | 1996-04-24 |
GB2230165A (en) | 1990-10-10 |
JPH0327638A (ja) | 1991-02-06 |
CN1046057A (zh) | 1990-10-10 |
DE69026644T2 (de) | 1996-09-19 |
US5050194A (en) | 1991-09-17 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
FG2A | Definitive protection |
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