ES2085591T3 - Dispositivo de detencion de enganche de un bucle de enclavamiento de fase numerica. - Google Patents

Dispositivo de detencion de enganche de un bucle de enclavamiento de fase numerica.

Info

Publication number
ES2085591T3
ES2085591T3 ES92402670T ES92402670T ES2085591T3 ES 2085591 T3 ES2085591 T3 ES 2085591T3 ES 92402670 T ES92402670 T ES 92402670T ES 92402670 T ES92402670 T ES 92402670T ES 2085591 T3 ES2085591 T3 ES 2085591T3
Authority
ES
Spain
Prior art keywords
phase
transitions
type
signal
detection device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES92402670T
Other languages
English (en)
Inventor
Jean-Luc Lafon
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alcatel CIT SA
Original Assignee
Alcatel CIT SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel CIT SA filed Critical Alcatel CIT SA
Application granted granted Critical
Publication of ES2085591T3 publication Critical patent/ES2085591T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/095—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/50—All digital phase-locked loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S331/00—Oscillators
    • Y10S331/02—Phase locked loop having lock indicating or detecting means

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Measuring Phase Differences (AREA)

Abstract

ESTE DISPOSITIVO DE DETECCION DE ENGANCHE DE UN BUCLE DE CIERRE DE FASE NUMERICA ES TAL QUE DICHO BUCLE DE CIERRE DE FASE (1) QUE COMPRENDE UN DETECTOR DE DESVIO DE FASE ENTRE DICHA SEÑAL ENTRANTE Y DICHA SEÑAL SALIENTE, Y PRESENTANDO LA SEÑAL DE SALIDA DE ESTE DETECTOR DE DESVIO DE FASE TRANSICIONES DE UN PRIMER TIPO COINCIDENTE CON LAS TRANSICIONES DE UN TIPO DADO DE LA SEÑAL SALIENTE, Y TRANSICIONES DE UN SEGUNDO TIPO COINCIDENTE CON LAS TRANSICIONES DE UN TIPO DADO DE LA SEÑAL ENTRANTE, ESTE DISPOSITIVO COMPRENDE, PARA REALIZAR DICHA DETECCION DE ENGANCHE, MEDIOS (5) DE DETECCION DE ENGANCHE QUE COMPRENDEN ELLOS MISMOS MEDIOS PARA REALIZAR UN MUESTRO DE LA SEÑAL DE SALIDA DEL DETECTOR DE FASE, POR AQUELLAS TRANSICIONES DE LA SEÑAL SALIENTE QUE SON DEL TIPO OPUESTO A DICHO TIPO DADO DE LOS MEDIOS (50) PARA MEMORIZAR, EN NUMERO AL MENOS IGUAL A 3, Y MEDIOS (54) DE DETECCION DEL INSTANTE EN QUE, POR PRIMERA VEZ, DOS O MENOS DE DICHAS MUESTRAS NO TIENEN EL MISMO NIVEL LOGICO.
ES92402670T 1991-10-04 1992-09-29 Dispositivo de detencion de enganche de un bucle de enclavamiento de fase numerica. Expired - Lifetime ES2085591T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9112267A FR2682237B1 (fr) 1991-10-04 1991-10-04 Dispositif de detection d'accrochage d'une boucle a verrouillage de phase.

Publications (1)

Publication Number Publication Date
ES2085591T3 true ES2085591T3 (es) 1996-06-01

Family

ID=9417619

Family Applications (1)

Application Number Title Priority Date Filing Date
ES92402670T Expired - Lifetime ES2085591T3 (es) 1991-10-04 1992-09-29 Dispositivo de detencion de enganche de un bucle de enclavamiento de fase numerica.

Country Status (10)

Country Link
US (1) US5268652A (es)
EP (1) EP0536042B1 (es)
JP (1) JP2769267B2 (es)
AT (1) ATE137368T1 (es)
AU (1) AU659875B2 (es)
CA (1) CA2079761C (es)
DE (1) DE69210158T2 (es)
ES (1) ES2085591T3 (es)
FR (1) FR2682237B1 (es)
NZ (1) NZ244539A (es)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5339049A (en) * 1993-04-22 1994-08-16 Wiltron Company Ultra low noise frequency divider/multiplier
US5781544A (en) * 1996-01-17 1998-07-14 Lsi Logic Corporation Method for interleaving network traffic over serial lines
US5956370A (en) * 1996-01-17 1999-09-21 Lsi Logic Corporation Wrap-back test system and method
US5787114A (en) * 1996-01-17 1998-07-28 Lsi Logic Corporation Loop-back test system and method
US5781038A (en) * 1996-02-05 1998-07-14 Lsi Logic Corporation High speed phase locked loop test method and means
US5896426A (en) * 1996-02-05 1999-04-20 Lsi Logic Corporation Programmable synchronization character
US6208621B1 (en) 1997-12-16 2001-03-27 Lsi Logic Corporation Apparatus and method for testing the ability of a pair of serial data transceivers to transmit serial data at one frequency and to receive serial data at another frequency
US6341142B2 (en) 1997-12-16 2002-01-22 Lsi Logic Corporation Serial data transceiver including elements which facilitate functional testing requiring access to only the serial data ports, and an associated test method
US6331999B1 (en) 1998-01-15 2001-12-18 Lsi Logic Corporation Serial data transceiver architecture and test method for measuring the amount of jitter within a serial data stream
EP2136472A1 (en) * 2008-06-17 2009-12-23 Nxp B.V. Fast-locking bang-bang PLL with low output jitter

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4330758A (en) * 1980-02-20 1982-05-18 Motorola, Inc. Synchronized frequency synthesizer with high speed lock
JPS5717236A (en) * 1980-07-04 1982-01-28 Mitsubishi Electric Corp Detector for synchronism
JPH0693628B2 (ja) * 1981-05-27 1994-11-16 株式会社日立製作所 Ｐｌｌロツク検出回路
GB8522998D0 (en) * 1985-09-18 1985-10-23 Plessey Co Plc Phase comparator lock detect circuit
JPH0752839B2 (ja) * 1986-11-06 1995-06-05 富士通株式会社 Ｄｐｌｌ回路の収束判定器
JPS6468127A (en) * 1987-09-09 1989-03-14 Nec Corp Oscillation circuit
EP0349966A3 (de) * 1988-07-08 1990-03-21 Siemens Aktiengesellschaft Verfahren zur Synchronisation eines Taktgenerators, insbesondere Taktgenerators einer digitalen Fernmeldevermittlungsstelle
JP2531269B2 (ja) * 1989-07-17 1996-09-04 日本電気株式会社 同期検出方式
JP2828286B2 (ja) * 1989-11-16 1998-11-25 富士通株式会社 Ｐｌｌのロック検出回路

Also Published As

Publication number Publication date
DE69210158T2 (de) 1996-09-19
AU2603592A (en) 1993-04-08
EP0536042A1 (fr) 1993-04-07
ATE137368T1 (de) 1996-05-15
JP2769267B2 (ja) 1998-06-25
FR2682237A1 (fr) 1993-04-09
AU659875B2 (en) 1995-06-01
EP0536042B1 (fr) 1996-04-24
FR2682237B1 (fr) 1993-11-19
CA2079761A1 (fr) 1993-04-05
CA2079761C (fr) 1999-04-20
DE69210158D1 (de) 1996-05-30
NZ244539A (en) 1995-12-21
JPH05243988A (ja) 1993-09-21
US5268652A (en) 1993-12-07

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