ES2068819T3 - Dispositivo de almacenamiento de propagacion del tipo fifo. - Google Patents

Dispositivo de almacenamiento de propagacion del tipo fifo.

Info

Publication number
ES2068819T3
ES2068819T3 ES88117025T ES88117025T ES2068819T3 ES 2068819 T3 ES2068819 T3 ES 2068819T3 ES 88117025 T ES88117025 T ES 88117025T ES 88117025 T ES88117025 T ES 88117025T ES 2068819 T3 ES2068819 T3 ES 2068819T3
Authority
ES
Spain
Prior art keywords
pass gate
gate transistors
storage device
inverters
fifo type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES88117025T
Other languages
English (en)
Inventor
David Norris
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of ES2068819T3 publication Critical patent/ES2068819T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/08—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations, the intermediate ones not being accessible for either enqueue or dequeue operations, e.g. using a shift register
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Communication Control (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Shift Register Type Memory (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Advance Control (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Small-Scale Networks (AREA)
  • Apparatus For Radiation Diagnosis (AREA)
  • Static Random-Access Memory (AREA)

Abstract

UNA PRIMERA ENTRADA DE PROPAGACION, Y UN DISPOSITIVO DE ALMACENAJE DE PRIMERA SALIDA (FIFO) SE CONDUCEN MEDIANTE UN RELOJ DE DOS FASES NO SUPERPUESTAS Y QUE INCLUYE UNA DIVERSIDAD DE CELULAS DE ALMACENAMIENTO (C1....C4) Y UNA DIVERSIDAD DE CIRCUITOS DE CELULA BIT DE RASTREO (T1...T4). CADA UNO DE LAS CELULAS DE ALMACENAJE INCLUYEN TIRISTORES PUERTA DE PRIMER PASO (G1...G8), INVERSORES PRIMEROS (INV1.....INV8), TRANSISTORES PUERTA DE SEGUNDO PASO (G9...G16), E INVERSORES SEGUNDOS (INV9...INV16). LOS TRANSISTORES PUERTA DE PRIMER PASO SON SENSIBLES A UNA SEÑAL DE CONTROL DESDE UN CIRCUITO DE RASTREO PARA ALMACENAR LAS SEÑALES DE LOS DATOS DE ENTRADA DENTRO DE LOS PRIMEROS INVERSORES. LOS TRANSISTORES PUERTA DE SEGUNDO PASO SON SENSIBLES A UNA PRIMERA FASE DEL RELOJ PARA CAMBIAR LAS SEÑALES DE LOS DATOS DE ENTRADA DENTRO DE LOS INVERSORES SEGUNDOS
ES88117025T 1987-10-22 1988-10-13 Dispositivo de almacenamiento de propagacion del tipo fifo. Expired - Lifetime ES2068819T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/111,476 US4805139A (en) 1987-10-22 1987-10-22 Propagating FIFO storage device

Publications (1)

Publication Number Publication Date
ES2068819T3 true ES2068819T3 (es) 1995-05-01

Family

ID=22338768

Family Applications (1)

Application Number Title Priority Date Filing Date
ES88117025T Expired - Lifetime ES2068819T3 (es) 1987-10-22 1988-10-13 Dispositivo de almacenamiento de propagacion del tipo fifo.

Country Status (7)

Country Link
US (1) US4805139A (es)
EP (1) EP0312914B1 (es)
JP (1) JP2863808B2 (es)
AT (1) ATE118904T1 (es)
DE (1) DE3853123T2 (es)
ES (1) ES2068819T3 (es)
GR (1) GR3015593T3 (es)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5532958A (en) * 1990-06-25 1996-07-02 Dallas Semiconductor Corp. Dual storage cell memory
US4873665A (en) * 1988-06-07 1989-10-10 Dallas Semiconductor Corporation Dual storage cell memory including data transfer circuits
US5544078A (en) * 1988-06-17 1996-08-06 Dallas Semiconductor Corporation Timekeeping comparison circuitry and dual storage memory cells to detect alarms
JP2721931B2 (ja) * 1990-09-28 1998-03-04 三菱電機株式会社 半導体メモリのためのシリアル選択回路
US5305319A (en) * 1991-01-31 1994-04-19 Chips And Technologies, Inc. FIFO for coupling asynchronous channels
US5237219A (en) * 1992-05-08 1993-08-17 Altera Corporation Methods and apparatus for programming cellular programmable logic integrated circuits
US5528463A (en) * 1993-07-16 1996-06-18 Dallas Semiconductor Corp. Low profile sockets and modules for surface mountable applications
US5579206A (en) * 1993-07-16 1996-11-26 Dallas Semiconductor Corporation Enhanced low profile sockets and module systems
FR2709359B1 (fr) * 1993-08-24 1995-11-10 Thomson Consumer Electronics Procédé de commande d'un circuit du type premier entré - premier sorti.
SE515201C2 (sv) * 1993-11-26 2001-06-25 Ericsson Telefon Ab L M Förfarande och anordning för klocksignalgenerering
US5937177A (en) * 1996-10-01 1999-08-10 Sun Microsystems, Inc. Control structure for a high-speed asynchronous pipeline

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4151609A (en) * 1977-10-11 1979-04-24 Monolithic Memories, Inc. First in first out (FIFO) memory
US4390970A (en) * 1980-12-15 1983-06-28 Texas Instruments Incorporated Rotating register utilizing field effect transistors
US4409680A (en) * 1981-08-27 1983-10-11 Ncr Corporation High speed write control for synchronous registers
DE3586523T2 (de) * 1984-10-17 1993-01-07 Fujitsu Ltd Halbleiterspeicheranordnung mit einer seriellen dateneingangs- und ausgangsschaltung.
US4651333A (en) * 1984-10-29 1987-03-17 Raytheon Company Shift register memory cell having a transmission gate disposed between an inverter and a level shifter
JPS61264596A (ja) * 1985-05-16 1986-11-22 Mitsubishi Electric Corp 読み出し専用メモリ
JPS62175991A (ja) * 1986-01-28 1987-08-01 Sharp Corp 先入れ先出し記憶装置

Also Published As

Publication number Publication date
DE3853123D1 (de) 1995-03-30
JPH01191392A (ja) 1989-08-01
EP0312914B1 (en) 1995-02-22
JP2863808B2 (ja) 1999-03-03
GR3015593T3 (en) 1995-06-30
EP0312914A2 (en) 1989-04-26
EP0312914A3 (en) 1991-03-06
DE3853123T2 (de) 1995-06-14
ATE118904T1 (de) 1995-03-15
US4805139A (en) 1989-02-14

Similar Documents

Publication Publication Date Title
ES2068819T3 (es) Dispositivo de almacenamiento de propagacion del tipo fifo.
ATE125385T1 (de) Elektronischer speicher.
JPS54139344A (en) Clock-system static memory
US4156288A (en) Asynchronous shift register with turnpike feature
EP1026692A3 (en) Data output buffers in semiconductor memory devices
US5901110A (en) Synchronous memory with dual sensing output path each of which is connected to latch circuit
US4825098A (en) Bidirectional semiconductor device having only one one-directional device
DE3785043D1 (de) Digitaler fifo-speicher.
JPS56114196A (en) Ram circuit
GB1422819A (en) Matrix data manipulator
JPS5835783A (ja) 半導体メモリ
KR970002679A (ko) 피씨아이(pci) 버스에서 플러그/플레이를 위한 배치회로
US4152777A (en) On chip buffering for optimizing performance of a bubble memory
ATE129592T1 (de) Differentielle verriegelungsumkehrschaltung und direktzugriffspeicher unter verwendung derselben vorrichtung.
US5113418A (en) Elastic buffer for local area network
US4142248A (en) Asynchronous storage loop type bubble chip architecture
SU819947A1 (ru) Накопительное устройство
GB1436345A (en) Semiconductor switching circuit
KR100461970B1 (ko) 면적 감소를 위한 래치 회로_
SU1444894A1 (ru) Регистр сдвига
SU1196950A1 (ru) Устройство для управления динамическим накопителем
KR840001406A (ko) 디지탈 휠터 회로
SU1058069A1 (ru) Цифровой накопитель
JPH01243296A (ja) シフト・レジスタ回路
KR0169400B1 (ko) 래치로 구성한 데이터 저장 회로

Legal Events

Date Code Title Description
FG2A Definitive protection

Ref document number: 312914

Country of ref document: ES