ES2005837A6 - Un procesador celular con control interno de las celulas de procesamiento. - Google Patents

Un procesador celular con control interno de las celulas de procesamiento.

Info

Publication number
ES2005837A6
ES2005837A6 ES8603011A ES8603011A ES2005837A6 ES 2005837 A6 ES2005837 A6 ES 2005837A6 ES 8603011 A ES8603011 A ES 8603011A ES 8603011 A ES8603011 A ES 8603011A ES 2005837 A6 ES2005837 A6 ES 2005837A6
Authority
ES
Spain
Prior art keywords
array
instruction
obey
control cell
processing state
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES8603011A
Other languages
English (en)
Inventor
Steven Gregory Morton
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nokia Spain SA
Original Assignee
Alcatel Standard Electrics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel Standard Electrics SA filed Critical Alcatel Standard Electrics SA
Publication of ES2005837A6 publication Critical patent/ES2005837A6/es
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G06F15/8023—Two dimensional arrays, e.g. mesh, torus
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/006—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation at wafer scale level, i.e. wafer scale integration [WSI]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Microcomputers (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

UN PROCESADOR CELULAR CON CONTROL INTERNO DE LAS CELULAS DE PROCESAMIENTO. SE MUESTRA UNA MATRIZ DE ELEMENTOS DE PROCESAMIENTO QUE ESTAN DISPUESTOS COMO UN PROCESADOR DE INSTRUCCION UNICA Y DATOS MULTIPLES. CADA CELULA DE PROCESAMIENTO DE LA MATRIZ CONTIENE LA LOGICA QUE PERMITE A LA CELULA DETERMINAR SI HA SIDO O NO SELECCIONADA PARA REALIZAR UNA OPERACION ARITMETICA O LOGICA. DE ESTE MODO CADA CELULA DE LA MATRIZ PUEDE OBEDECER UNA INSTRUCCION MIENTRAS QUE LAS OTRAS CELULAS DE LA MATRIZ PERMANECERAN INACTIVAS PARA LA MISMA INSTRUCCION. EL APARATO MEDIANTE EL CUAL LOS PROCESADORES PUEDEN OBEDECER O NO UNA INSTRUCCION ESTA INTEGRADO DENTRO DE LA MATRIZ DE ELEMENTOS DE PROCESAMIENTO Y PROPORCIONA MEMORIAS TIPO LIFO Y MECANISMOS COMPLEMENTARIOS PARA OCUPARSE DE COMPLEJAS SECUENCIAS DE PRUEBAS.
ES8603011A 1985-11-13 1986-11-13 Un procesador celular con control interno de las celulas de procesamiento. Expired ES2005837A6 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US79771885A 1985-11-13 1985-11-13

Publications (1)

Publication Number Publication Date
ES2005837A6 true ES2005837A6 (es) 1989-04-01

Family

ID=25171618

Family Applications (1)

Application Number Title Priority Date Filing Date
ES8603011A Expired ES2005837A6 (es) 1985-11-13 1986-11-13 Un procesador celular con control interno de las celulas de procesamiento.

Country Status (6)

Country Link
EP (1) EP0223690B1 (es)
JP (1) JPS62119675A (es)
CN (1) CN1012297B (es)
AU (1) AU588394B2 (es)
DE (1) DE3677330D1 (es)
ES (1) ES2005837A6 (es)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0231686A3 (en) * 1985-12-12 1989-06-14 Itt Industries, Inc. Cellular array processing apparatus with variable nesting depth vector processor control structure
GB2211638A (en) * 1987-10-27 1989-07-05 Ibm Simd array processor
US4933895A (en) * 1987-07-10 1990-06-12 Hughes Aircraft Company Cellular array having data dependent processing capabilities
EP0308660B1 (de) * 1987-09-22 1995-05-24 Siemens Aktiengesellschaft Vorrichtung zur Herstellung einer testkompatiblen, weitgehend fehlertoleranten Konfiguration von redundant implementierten systolischen VLSI-Systemen
DE68926783T2 (de) * 1988-10-07 1996-11-28 Martin Marietta Corp Paralleler datenprozessor
CA2021192A1 (en) * 1989-07-28 1991-01-29 Malcolm A. Mumme Simplified synchronous mesh processor
US6073185A (en) * 1993-08-27 2000-06-06 Teranex, Inc. Parallel data processor
CN1045220C (zh) * 1996-06-26 1999-09-22 杨风桐 用硼元素和中子寿命测井仪寻求剩余油残余油的方法
US6185667B1 (en) 1998-04-09 2001-02-06 Teranex, Inc. Input/output support for processing in a mesh connected computer
US6173388B1 (en) 1998-04-09 2001-01-09 Teranex Inc. Directly accessing local memories of array processors for improved real-time corner turning processing
US6212628B1 (en) 1998-04-09 2001-04-03 Teranex, Inc. Mesh connected computer
US6067609A (en) * 1998-04-09 2000-05-23 Teranex, Inc. Pattern generation and shift plane operations for a mesh connected computer
CN100419668C (zh) * 2003-05-23 2008-09-17 日本电信电话株式会社 并行处理设备和并行处理方法
JP4562759B2 (ja) * 2007-09-03 2010-10-13 京楽産業．株式会社 アクセス制御装置、アクセス制御方法およびアクセス制御プログラム
KR101510694B1 (ko) * 2007-12-12 2015-04-10 엘지전자 주식회사 데이터 처리 장치 및 방법

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56127266A (en) * 1980-03-10 1981-10-05 Ibm Method of executing and controlling command stream
US4580215A (en) * 1983-03-08 1986-04-01 Itt Corporation Associative array with five arithmetic paths
NZ207326A (en) * 1983-03-08 1988-03-30 Stc Plc Associative data processing array
JPH0654505B2 (ja) * 1983-12-23 1994-07-20 株式会社日立製作所 並列型演算処理装置

Also Published As

Publication number Publication date
JPS62119675A (ja) 1987-05-30
EP0223690A2 (en) 1987-05-27
CN86106713A (zh) 1987-05-20
EP0223690B1 (en) 1991-01-30
AU6483486A (en) 1987-05-21
AU588394B2 (en) 1989-09-14
CN1012297B (zh) 1991-04-03
EP0223690A3 (en) 1988-07-27
DE3677330D1 (de) 1991-03-07

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Legal Events

Date Code Title Description
SA6 Expiration date (snapshot 920101)

Free format text: 2006-11-13