Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/76—Making of isolation regions between components
  • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
  • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
  • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
  • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02002—Preparing wafers
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02436—Intermediate layers between substrates and deposited layers
  • H01L21/02439—Materials
  • H01L21/02441—Group 14 semiconducting materials
  • H01L21/02444—Carbon, e.g. diamond-like carbon
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  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02436—Intermediate layers between substrates and deposited layers
  • H01L21/02439—Materials
  • H01L21/02441—Group 14 semiconducting materials
  • H01L21/02447—Silicon carbide
• • H—ELECTRICITY
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  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02436—Intermediate layers between substrates and deposited layers
  • H01L21/02494—Structure
  • H01L21/02496—Layer structure
  • H01L21/02505—Layer structure consisting of more than two layers
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02436—Intermediate layers between substrates and deposited layers
  • H01L21/02494—Structure
  • H01L21/02513—Microstructure
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02518—Deposited layers
  • H01L21/02521—Materials
  • H01L21/02524—Group 14 semiconducting materials
  • H01L21/02529—Silicon carbide
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02518—Deposited layers
  • H01L21/0257—Doping during depositing
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02518—Deposited layers
  • H01L21/02587—Structure
  • H01L21/0259—Microstructure
  • H01L21/02598—Microstructure monocrystalline
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02612—Formation types
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

Definitions

• TITLE METHOD FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE BASED ON SILICON CARBIDE AND STRUCTURE
• the present invention relates to the field of semiconductor materials for microelectronic components. It relates in particular to a process for manufacturing a semiconductor structure comprising an active layer of high-quality monocrystalline silicon carbide comprising or intended to accommodate electronic components, said active layer being placed on a support layer of polysilicon carbide. -crystalline.
• the invention also relates to an intermediate composite structure obtained during said process.
• SiC silicon carbide
• Power devices and integrated power systems based on monocrystalline silicon carbide can handle much higher power density compared to their traditional silicon counterparts, and this with smaller active area dimensions.
• To further limit the dimensions of power devices on SiC it is advantageous to manufacture vertical rather than lateral components. For this, vertical electrical conduction, between an electrode arranged on the front face of the assembly of components and an electrode arranged on the rear face, must be authorized by said assembly.
• a well-known thin film transfer solution is the Smart CutTM process, based on light ion implantation and direct bonding assembly.
• Such a method makes it possible, for example, to manufacture a composite structure comprising a thin layer of monocrystalline SiC (c-SiC), taken from a donor substrate of c-SiC, in direct contact with a support substrate of polycrystalline SiC (p- SiC), and allowing vertical electrical conduction.
• the support substrate which must have a sufficient thickness to be compatible with the formation of the components, is finally thinned to obtain the set of electronic components ready to be integrated.
• Document US8436363 is also known, which describes a process for manufacturing a composite structure comprising a thin layer of c-SiC placed on a metal support substrate whose coefficient of thermal expansion is matched with that of the thin layer. This manufacturing process includes the following steps:
• the composite structure comprising the metal support substrate and the thin layer in c-SiC, and on the other hand, the rest of the donor substrate in c-SiC.
• the present invention relates to an alternative solution to those of the state of the art, and aims to remedy all or part of the aforementioned drawbacks. It relates in particular to a method for manufacturing a semiconductor structure for electronic components, advantageously vertical, produced on and/or in an active layer of high quality monocrystalline silicon carbide, which is placed on a carbide support layer. of polycrystalline silicon. The invention also relates to a composite structure obtained at an intermediate step of said manufacturing process.
• the invention relates to a method for manufacturing a semiconductor structure, comprising: a) a step of supplying a temporary substrate made of a material whose coefficient of thermal expansion is between 3.5.10 6 /°C and 5.10 6 /°C; b) a step of forming an intermediate layer of graphite, on a front face of the temporary substrate; c) a step of depositing, on the intermediate layer, a support layer of polycrystalline silicon carbide having a thickness of between 10 microns and 200 microns, d) a step of transferring a useful layer of silicon carbide monocrystalline on the support layer, directly or via an additional layer, to form a composite structure, said transfer implementing bonding by molecular adhesion, e) a step of forming an active layer on the useful layer, f) a step dismantling at an interface of the intermediate layer or in the intermediate layer, to obtain, on the one hand the semiconductor structure including the active layer, the useful layer and the support layer, and on the other hand the temporary substrate.
• the intermediate layer has a thickness of between 1 micron and 100 microns; • the graphite of the intermediate layer has an average grain size of between 1 micron and 50 microns;
• the graphite of the intermediate layer has a porosity of between 6 and 17%
• the graphite of the intermediate layer has a thermal expansion coefficient of between 4.10 6 /°C and 5.10 6 /°C;
• the intermediate layer is also formed on a peripheral edge of the temporary substrate, and/or a second intermediate layer is formed on a rear face of the temporary substrate;
• the support layer is also deposited on the intermediate layer present on the peripheral edge of the temporary substrate and/or directly on the peripheral edge of the temporary substrate;
• transfer step d) comprises: o the introduction of light species into a monocrystalline silicon carbide donor substrate, to form a buried fragile plane defining with the front face of the donor substrate, the useful layer, o the assembly of the front face of the donor substrate on the support layer, directly or via an additional layer, by bonding by molecular adhesion, o separation along the buried fragile plane to transfer the useful layer onto the support layer;
• step e) comprises epitaxial growth of at least one additional layer of doped monocrystalline silicon carbide, on the useful layer, said additional layer forming all or part of the active layer;
• step e) comprises a heat treatment at a temperature greater than or equal to 1600° C., aimed at effecting an activation of dopants in the active layer;
• the method comprises a step e′) of producing all or part of the electronic components on and/or in the active layer, step e′) being inserted between step e) and step f);
• a removable handle is assembled on the free face of the active layer or of all or part of the electronic components if they are present, prior to step f) of disassembly;
• step f • the dismantling of step f) takes place by the propagation of a crack at an interface of the intermediate layer or in the intermediate layer, following the application of a mechanical stress;
• step f • the dismantling of step f) comprises a lateral chemical etching of all or part of the intermediate layer
• step f • the dismantling of step f) includes thermal damage to the graphite of the intermediate layer
• step f • the dismantling of step f) takes place by cutting the graphite of the intermediate layer using a diamond wire saw;
• the method comprises a step of recycling the temporary substrate resulting from step f);
• step c) comprises the deposition, on the second intermediate layer present on the rear face of the temporary substrate, of a second polycrystalline silicon carbide support layer having a thickness of between 10 microns and 200 microns,
• step d) comprises the transfer of a second useful layer of monocrystalline silicon carbide onto the second support layer, directly or via a layer additional, said transfer implementing bonding by molecular adhesion,
• step e) comprises the formation of a second active layer on the second useful layer
• step f) comprises dismantling at an interface of the second intermediate layer or in the second intermediate layer, to obtain another semiconductor structure including the second active layer, the second useful layer and the second support layer.
• the invention also relates to a composite structure comprising:
• the temporary substrate is made of monocrystalline or polycrystalline silicon carbide
• the useful layer has a thickness of between 100 nm and 1500 nm.
• Figure 1 shows a set of electronic components developed according to a manufacturing method according to the invention
• FIG. 2f Figures 2a, 2b, 2c, 2d, 2e, 2e' and 2f show steps of a manufacturing method according to the invention
• FIG. 3d Figures 3a to 3d show steps of a particular embodiment of the manufacturing method according to the invention.
• FIGS. 4a to 4c present a step d) of transfer of the manufacturing method according to the invention.
• the same references in the figures may be used for elements of the same type.
• the figures are schematic representations which, for the purpose of readability, are not to scale.
• the thicknesses of the layers along the z axis are not to scale by relation to the lateral dimensions along the x and y axes; and the relative thicknesses of the layers between them are not necessarily observed in the figures.
• the present invention relates to a method of manufacturing a semiconductor structure 100 (FIG. 1).
• semiconductor structure 100 is meant at least a stack of layers 4,3,2 intended to accommodate a plurality of microelectronic components; also means the stack of layers 4,3,2 with said electronic components 40, resulting from a collective manufacture on and/or in the active layer 4 maintained in the form of a wafer by a support layer 2, and ready to undergo the singulation stages prior to packaging.
• the manufacturing method advantageously applies to vertical microelectronic components, which require vertical electrical conduction through support layer 2, which forms the mechanical support for said components 40.
• the manufacturing process firstly comprises a step a) of supplying a temporary substrate 1 made of a material whose coefficient of thermal expansion is close to that of silicon carbide (SiC), namely between 3.5.10 6 / °C and 5.10 6 /°C (between ambient temperature and 1000°C), having a front face 1a, a rear face 1b and a peripheral edge 1c (FIG. 2a).
• the temporary substrate 1 is therefore made of polycrystalline or monocrystalline SiC of low crystalline quality, the role of the temporary substrate 1 being essentially mechanical.
• the manufacturing process then comprises a step b) of forming an intermediate layer 12 of graphite.
• the intermediate layer 12 could be produced, for example, by deposition from a plasma, ion sputtering, cathodic arc deposition, evaporation of graphite by laser, carbonization and/or pyrolysis of a resin, etc.
• graphite of polycrystalline structure
• p-SiC polycrystalline silicon carbide
• support layer 2 a layer of polycrystalline silicon carbide
• certain physical properties of graphite are chosen to provide an excellent seed for the deposition of a layer of polycrystalline silicon carbide (p-SiC), called support layer 2 below, and which will be described with reference to step c) of the method.
• graphite, of polycrystalline structure has a grain size, in particular an average grain size, of between 1 micron and 50 microns, that is to say falling in the same order of magnitude as the size grain average expected for the support layer 2, in the plane of the faces la, lb.
• the mean size of the grains corresponds in particular to the arithmetic mean of the sizes of the grains of dimension greater than or equal to 100 nm. These grain sizes can be measured for example by scanning microscopy (SEM), by X-ray diffraction (in particular from the width at mid-height of an X-ray diffraction signal) or by backscattered electron diffraction (EBSD).
• SEM scanning microscopy
• X-ray diffraction in particular from the width at mid-height of an X-ray diffraction signal
• EBSD backscattered electron diffraction
• the thermal conductivity of the support layer 2 is thus ensured, because the grains of said layer will not be too small; moreover, even if the size of the grains is made to grow during the deposition of the support layer 2, we remain within a range of controlled sizes, due to the defined range of grain sizes of the graphite, which limits the roughness at the level of the free surface of the support layer 2 deposited.
• the porosity of the graphite is between 6 and 17%, a restricted range which makes it possible to control the surface roughness of the support layer 2 after its deposition. Typically, it will thus be possible to limit the surface roughness to less than 1 micron RMS, or even to less than lOnm RMS, so as to reduce the smoothing treatments after the deposition of the support layer 2.
• the coefficient of thermal expansion of the intermediate layer 12 is between 4.10 6 /°C and 5.10 6 /°C (between ambient temperature and 1000°C) so as to be matched with the coefficient of thermal expansion of silicon carbide, for limit the mechanical stresses during treatments (described later in the process) involving high temperatures.
• the temporary substrate 1 provided with the intermediate layer 12 is compatible with temperatures which can go up to 1450° C., when the atmosphere is controlled, that is to say without oxygen. Indeed, if exposed to air, the graphite of the intermediate layer 12 begins to burn in a range of low temperatures, typically 400°C - 600°C. Protected by a protective layer completely encapsulating it, the intermediate layer 12 of graphite is compatible with very high temperatures, even above 1450° C.
• step b) also comprises the formation of the intermediate layer 12 on the peripheral edges 1e of the temporary substrate 1 (FIG. 3b).
• Step b) can also comprise a second intermediate layer 12' of graphite, on a rear face lb of the temporary substrate 1 (FIG. 3a, FIG. 3b), with or without intermediate layer 12 on the peripheral edges 1e.
• a step c) of depositing, on the intermediate layer 12, a support layer 2 in polycrystalline silicon carbide (p-SiC) is then operated on (figure 2c).
• the support layer 2 is, in particular, deposited directly on the intermediate layer 12, that is to say that no additional layer is interposed between the layers 2 and 12, which are in contact with each other.
• the deposition of the support layer 2 is also carried out on the peripheral edges of the temporary substrate 1, so as to encapsulate and protect the intermediate layer 12 for the subsequent steps of the method.
• the deposition can be carried out by any known technique, in particular by chemical vapor deposition (CVD), at a temperature of the order of 1100° C. to 1400° C. Mention may be made, for example, of a thermal CVD technique such as deposition at atmospheric pressure (APCVD for "atmospheric pressure CVD) or at low pressure (LPCVD for "low pressure CVD”), the precursors possibly being chosen from methylsilane, dimethyldichlorosilane or alternatively dichlorosilane+i-butane.
• CVD chemical vapor deposition
• PECVD plasma-assisted CVD
• plasma enhanced CVD can also be used, with, for example, silicon tetrachloride and methane as precursors; preferentially, the frequency of the source used to generate the electric discharge creating the plasma is of the order of 3.3 MHz, and more generally comprised between 10 kHz and 100 GHz.
• conventional cleaning sequences may be applied to the temporary substrate 1 provided with the intermediate layer 12, to eliminate all or part of the particulate, metallic or organic contaminants potentially present on its free faces 1a, 1b.
• the p-SiC support layer 2 has a thickness of between 10 microns and 200 microns. This thickness is chosen according to the thickness specifications expected for the semiconductor structure 100.
• the support layer 2 will have, in this structure 100, the role of mechanical substrate and will potentially ensure vertical electrical conduction. To guarantee this last property of electrical conduction (low resistivity), the support layer 2 is advantageously n- or p-type doped according to need.
• step c) can also be carried out on the second intermediate layer 12', to form a second support layer 2', and/or on the peripheral edge the of the temporary substrate 1 , as shown in Figure 3c.
• the role of the second support layer 2 ', deposited on the rear face lb of the temporary substrate 1 is to allow the following steps of the method to be carried out at the level of the two faces la, lb of the said substrate 1.
• a surface treatment is carried out to improve the surface roughness of the support layer 2 and/or the quality of the edges of the structure, with a view to the next step of thin layer transfer.
• the manufacturing method according to the invention comprises a step d) of transferring a useful layer 3 of monocrystalline silicon carbide (c-SiC) directly onto the support layer 2 or via an additional layer, to form a composite structure 10 (FIG. 2d).
• the transfer implements bonding by molecular adhesion, and consequently a bonding interface 5.
• the additional layer can be formed on the side of the useful layer 3 and/or on the side of the support layer 2, to promote said bonding.
• transfer step d) comprises:
• the light species are preferably hydrogen, helium or a co-implantation of these two species, and are implanted at a determined depth in the donor substrate 30, consistent with the thickness of the targeted useful layer 3 (figure 4a). These light species will form, around the determined depth, microcavities distributed in a thin layer parallel to the free surface 30a of the donor substrate 30, ie parallel to the plane (x,y) in the figures. This thin layer is called the buried fragile plane 31, for simplicity.
• the implantation energy of the light species is chosen so as to reach the determined depth.
• hydrogen ions will be implanted at an energy between 10 keV and 250 keV, and at a dose of between 5 E 16/cm2 and 1 E 17/cm2, to delimit a useful layer 3 having a thickness of the order of 100 to 1500 nm.
• a protective layer may be deposited on the front face 30a of the donor substrate 30, prior to the ion implantation step. This protective layer can be composed of a material such as silicon oxide or silicon nitride for example. It can be kept for the next step, or removed.
• bonding by molecular adhesion does not require an adhesive material, bonds being established on the atomic scale between the assembled surfaces.
• the assembly step may include, prior to bringing the faces to be assembled into contact, conventional sequences of cleaning, surface activation or other surface preparations, likely to promote the quality of the bonding interface 5 ( low defectivity, high adhesion energy).
• the front face 30a of the donor substrate 30 and/or the free face of the support layer 2 may (have) optionally comprise an additional layer, for example metallic (tungsten, etc.) or doped semiconductor (silicon, etc. ) to promote vertical electrical conduction, or insulating (oxide silicon, silicon nitride, etc. for applications that do not require vertical electrical conduction.
• the additional layer is capable of promoting bonding by molecular adhesion, in particular by erasing residual roughness or surface defects present on the faces to be assembled. It may undergo planarization or smoothing treatments to achieve a roughness of less than 1 nm RMS, or even less than 0.5 nm RMS, favorable to bonding.
• the separation along the buried fragile plane 31 usually takes place by applying a heat treatment at a temperature between 800° C. and 1200° C. (FIG. 4c).
• a heat treatment induces the development of cavities and microcracks in the buried fragile plane 31, and their pressurization by the light species present in gaseous form, until the propagation of a fracture along said fragile plane 31.
• a mechanical stress can be applied to the bonded assembly and in particular at the level of the buried fragile plane 31, so as to propagate or help to mechanically propagate the fracture leading to the separation.
• the composite structure 10 comprising the temporary substrate 1, the intermediate layer 12 in graphite, the support layer 2 in p-SiC and the useful layer 3 transferred in c-SiC, and on the other hand, the remainder 30' of the donor substrate.
• the useful layer 3 typically has a thickness of between 100 nm and 1500 nm.
• the level and the type of doping of the useful layer 3 is defined by the choice of the properties of the donor substrate 30 or can be adjusted later via known techniques for doping semiconductor layers.
• the free surface of the useful layer 3 is usually rough after separation: for example, it has a roughness of between 5 nm and 100 nm RMS (AFM, scan 20 microns ⁇ 20 microns). Cleaning and/or smoothing steps can be applied to restore a good surface condition (typically, a roughness of less than a few Angstroms RMS on a 20 micron x 20 micron AFM scan).
• the free surface of the useful layer 3 can remain rough, as separated, when the next step of the process tolerates this roughness.
• step d) can also comprise the transfer of a second useful layer 3 'in c-SiC on the second support layer 2', via a second bonding interface 5' (FIG. 3d).
• the manufacturing method according to the invention then comprises a step e) of forming an active layer 4 on the useful layer 3 (FIG. 2e).
• the active layer 4 is produced by epitaxial growth of an additional layer of doped monocrystalline silicon carbide, on the useful layer 3.
• This epitaxial growth is carried out in the conventional temperature range, namely between 1500° C. and 1900° C. C and forms an additional layer with a thickness of the order of 1 micron to a few tens of microns, depending on the electronic components targeted.
• a protective layer on the edges of the intermediate layer 12 of graphite, in the composite structure 10, is required so that the aforementioned very high temperature treatments do not damage the graphite.
• this protective layer may for example consist of a layer of polycrystalline silicon carbide (deposited, for example, at the same time as the support layer 2) or amorphous.
• the manufacturing method according to the invention can also comprise a step e′) of producing all or part of the electronic components 40 on and/or in the active layer 4 (FIG. 2e′).
• the electronic components 40 can for example consist of transistors or other high voltage and/or high frequency components.
• step e) can also comprise the formation of a second active layer on the second useful layer 3'; and step e′) can comprise the production of all or part of second electronic components on and/or in said second active layer.
• the manufacturing method according to the invention comprises a step f) of dismantling at an interface of the intermediate layer 12 and/or in the intermediate layer 12 to form on the one hand the semiconductor structure 100 including the active layer 4 , the useful layer 3 and the support layer 2, and on the other hand the temporary substrate 1 (FIG. 2f (i)), and potentially the electronic components 40 (FIG. 2f (ii)), if a step e' has been carried out .
• Several variants of dismantling, at the level of the intermediate layer 12 can be implemented for this step.
• step f) comprises mechanical dismantling by propagation of a crack in the intermediate layer 12, and/or at the interface between the intermediate layer 12 and the support layer 2, and/or even between the intermediate layer 12 and the temporary substrate 1.
• the crack propagates substantially parallel to the plane of the intermediate layer 12, following the application of a mechanical stress.
• the insertion of a bevelled tool opposite the intermediate layer 12 makes it possible to initiate and propagate an opening at a fragile interface: the graphite having a lower cohesive energy along the axis z, the cracking will preferentially take place in the intermediate layer 12 or at interfaces, until the complete separation between the semiconductor structure 100 and the temporary substrate 1.
• the protective layer present on the edges le of the substrate temporary 1 is removed, by dry or wet etching for example, to promote crack initiation in the graphite.
• step f) comprises a chemical dismantling between the semiconductor structure 100 and the temporary substrate 1, by lateral chemical etching.
• the protective layer (p-SiC) located on the peripheral edges of the temporary substrate 1 (and in particular on the edges of the intermediate layer 12) in the composite structure 10 must be removed chemically or mechanically, to allow access in graphite.
• the lateral chemical etching of the intermediate layer 12 can implement a solution based on nitric acid and/or sulfuric acid, for example a solution of concentrated sulfuric acid and potassium dichromate or a solution of sulfuric acid, nitric acid and potassium chlorate.
• Chemical etching using an alkaline solution can also be applied.
• an alkaline solution of the potassium hydroxide (KOH) or sodium hydroxide (NaOH) type
• KOH potassium hydroxide
• NaOH sodium hydroxide
• step f) comprises mechanical dismantling by thermal damage of the graphite making up the intermediate layer 12.
• step f) comprises mechanical dismantling by thermal damage of the graphite making up the intermediate layer 12.
• it is required to remove the protective layer present at least on the edges of the temporary substrate 1 to give access to the intermediate layer 12.
• Dismantling by thermal damage can take place at a temperature between 600° C. and 1000° C., in the presence of oxygen: the graphite of the intermediate layer 12 is then burned and crumbles, thus separating the semi-conducting structure 100 of temporary substrate 1.
• this dismantling variant can only be applied if said components 40 are compatible with the temperature applied.
• step f) is carried out by cutting the graphite of the intermediate layer 12, by means of a wire saw.
• the wire contains diamond particles.
• the aforementioned variants may possibly be combined with each other, according to all the technically feasible combinations.
• the dismantling of the temporary substrate 1 can leave residues 12r of the intermediate layer 12, on the rear face 2b of the support layer 2 and/or on the front face of the temporary substrate 1. These residues can be eliminated by mechanical rectification, by mechanical-chemical polishing, by chemical etching and/or by thermal damage.
• Mechanical-chemical polishing or chemical etching techniques can also be implemented to reduce the roughness of the rear face 2b of the support layer 2, if necessary, after elimination of the residues 12r.
• step f) of dismantling the temporary substrate 1 also makes it possible to form a second semiconductor structure including the second active layer, the second useful layer 3' and the second support layer 2'.
• the semiconductor structure 100 must be manipulated during and after the removal of the temporary substrate 1, and its total thickness is insufficient for its mechanical maintenance during this manipulation, it is possible to use a removable handle: the latter is arranged on the active layer 4 or on the components 40, and temporarily attached to them, to perform the manipulation up to the singulation step, for example.
• the semiconductor structure 100 obtained at the end of the manufacturing process according to the invention comprises an active layer 4 advantageously finalized with electronic components 40 and placed on a support layer 2 having the thickness targeted for the application. No mechanical thinning involving significant loss of material is required.
• the support layer 2 is made of p-SiC of good quality (because it is deposited at relatively high temperatures) but at low cost compared to a solid monocrystalline or polycrystalline SiC substrate which should have been thinned significantly before singulation of the components 40.
• the substrate temporary 1, after dismantling, is recovered for recycling, which also constitutes an economic advantage.
• the intermediate layer 12 of graphite allows simple dismantling of the composite structure 10 after the active layer 4 (and preferably all or part of the components) has been formed, while ensuring mechanical stability to the composite structure 10 during the heat treatments at very high temperatures applied for the development of the active layer 4.
• the choice of the physical characteristics of the intermediate layer 12 of graphite ensures the formation of a support layer 2 allowing the obtaining a composite structure 10 that is robust and of high quality, and making it possible to obtain a semiconductor structure 100 that is reliable and efficient.
• the performance of the components 40 comes in particular from the fact that the composite structure 10 allows treatment at very high temperatures for the formation of the active layer 4.
• the invention also relates to a composite structure 10, described above with reference to the manufacturing process, and corresponding to an intermediate structure obtained during said process (FIGS. 2d, 3d).
• the composite structure 10 comprises:
• a temporary substrate 1 made of a material whose coefficient of thermal expansion is close to that of silicon carbide, - an intermediate layer 12 of graphite, at least arranged on the front face 1a of the temporary substrate 1,
• the graphite of the intermediate layer 12 has a grain size of between 1 micron and 50 microns, a porosity of between 6 and 17%, and/or a thermal expansion coefficient of between 4.10 6 /°C and 5.10 6 / °C.
• a grain size of between 1 micron and 50 microns a porosity of between 6 and 17%
• a thermal expansion coefficient of between 4.10 6 /°C and 5.10 6 / °C The advantages associated with these characteristics have been previously stated.
• the useful layer 3 has a thickness of between 100 nm and 1500 nm.
• the intermediate layer 12 has a thickness of between 1 micron and 100 microns, or between 10 microns and 100 microns;
• the temporary substrate 1 has a thickness of between 300 microns and 800 microns.
• support layer 2 advantageously has good electrical conductivity, i.e. between 0.015 and 0.03 ohm.cm, high thermal conductivity, i.e. greater than or equal to 200 Wm _1 .K _1 and a coefficient of thermal expansion similar to that of the useful layer 3, ie typically between 3.8 ⁇ 10 6 /°C and 4.2 ⁇ 10 6 /°C at ambient temperature.
• the intermediate layer 12 and/or the temporary substrate 1 can advantageously have a thermal conductivity of between 5 Wm _1 .K _1 and 500 Wm _1 .K _1 , so as to ensure a uniform temperature on the temporary substrate 1 during the steps of heat treatments at very high temperatures in the manufacturing process. This notably improves the uniformity of layers deposited and the reproducibility of the physical properties of the layers and components produced.
• the composite structure 10 can be “double-sided”, that is to say comprise:
• Such a composite structure 10 allows the formation of two active layers 40, on the first 3 and the second 3 'useful layer, and at the end of the manufacturing method according to the invention, the obtaining of two semiconductor structures 100 , from a single temporary substrate 1.

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• 2021
  • 2021-03-09 FR FR2102307A patent/FR3120737A1/fr active Pending
• 2022
  • 2022-03-03 KR KR1020237034300A patent/KR20230153476A/ko unknown
  • 2022-03-03 CN CN202280015305.2A patent/CN116868312A/zh active Pending
  • 2022-03-03 US US18/548,616 patent/US20240145294A1/en active Pending
  • 2022-03-03 WO PCT/FR2022/050380 patent/WO2022189733A1/fr active Application Filing
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  • 2022-03-03 TW TW111107793A patent/TW202301555A/zh unknown
  • 2022-03-03 EP EP22712959.0A patent/EP4305660A1/de active Pending

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