EP4261604A2 - Dispositif électronique - Google Patents

Dispositif électronique Download PDF

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Publication number
EP4261604A2
EP4261604A2 EP23164218.2A EP23164218A EP4261604A2 EP 4261604 A2 EP4261604 A2 EP 4261604A2 EP 23164218 A EP23164218 A EP 23164218A EP 4261604 A2 EP4261604 A2 EP 4261604A2
Authority
EP
European Patent Office
Prior art keywords
spacer
pattern
disposed
electronic device
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP23164218.2A
Other languages
German (de)
English (en)
Other versions
EP4261604A3 (fr
Inventor
Ming-Jou Tai
Chia-Hao Tsai
Yi-Shiuan Cherng
You-cheng LU
Wei-Yen Chiu
Yung-Hsun Wu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Innolux Corp
Original Assignee
Innolux Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CN202310011886.9A external-priority patent/CN116909060A/zh
Application filed by Innolux Corp filed Critical Innolux Corp
Publication of EP4261604A2 publication Critical patent/EP4261604A2/fr
Publication of EP4261604A3 publication Critical patent/EP4261604A3/fr
Pending legal-status Critical Current

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • G02F1/13394—Gaskets; Spacers; Sealing of cells spacers regularly patterned on the cell subtrate, e.g. walls, pillars
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133514—Colour filters
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • G02F1/13396—Spacers having different sizes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136222—Colour filters incorporated in the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/011—Arrangements for interaction with the human body, e.g. for user immersion in virtual reality
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/40—Arrangements for improving the aperture ratio

Definitions

  • the present disclosure relates to an electronic device, and more particularly, to an electronic device with high resolution.
  • the present disclosure aims at providing an electronic device which is capable of maintaining the opening rate and the applications of high-resolution display devices.
  • the claimed electronic device has a plurality of sub-pixels.
  • the electronic device includes a substrate, a gate line and a spacer.
  • the gate line is disposed on the substrate and extends along a first direction.
  • the spacer is disposed on the gate line and overlaps with the gate line.
  • the spacer has a first width W1 along the first direction.
  • One of the plurality of sub-pixels has a sub-pixel pitch P along the first direction.
  • the first width W1 and the sub-pixel pitch P satisfy the following relationship: P ⁇ W1.
  • the claimed electronic device includes a substrate, a data line, an opposite substrate, a spacer and a first pattern.
  • the data line is disposed on the substrate and has an extending direction.
  • the opposite substrate is disposed corresponding to the substrate.
  • the spacer is disposed between the substrate and the opposite substrate.
  • the first pattern is disposed between the data line and the spacer and extends along the extending direction. The first pattern overlaps with the data line.
  • the directional terms such as “on/up/above”, “down/below”, “front”, “rear/back”, “left”, “right”, etc., are only directions referring to the drawings. Therefore, the directional terms are used for explaining and not used for limiting the present disclosure.
  • the drawings show the general characteristics of methods, structures, and/or materials used in specific embodiments. However, the drawings should not be construed as defining or limiting the scope or properties encompassed by these embodiments. For example, for clarity, the relative size, thickness, and position of each layer, each area, and/or each structure may be reduced or enlarged.
  • a structure or layer, or component, or substrate
  • the two structures are adjacent and directly connected with each other, or the two structures are adjacent and indirectly connected with each other.
  • the two structures being indirectly connected with each other may refer that at least one intervening structure (or intervening layer, or intervening component, or intervening substrate, or intervening interval) exists between the two structures, a lower surface of one of the two structure is adjacent or directly connected with an upper surface of the intervening structure, and an upper surface of the other of the two structures is adjacent or directly connected with a lower surface of the intervening structure.
  • the intervening structure may be a single-layer or multi-layer physical structure or a non-physical structure, and the present disclosure is not limited thereto.
  • a certain structure when a certain structure is disposed "on/above” other structures, it may refer that the certain structure is “directly” disposed on/above the other structures, or the certain structure is “indirectly” disposed on/above the other structures, i.e., at least one structure is disposed between the certain structure and the other structures.
  • any two values or directions used for comparison may have a certain error. If a first value is equal to a second value, it implies that there may be an error of about 10% between the first value and the second value; if a first direction is perpendicular or "substantially” perpendicular to a second direction, then an angle between the first direction and the second direction may be between 80 degrees to 100 degrees; if the first direction is parallel or “substantially” parallel to the second direction, an angle between the first direction and the second direction may be between 0 degree to 10 degrees.
  • ordinal numbers such as “first”, “second”, etc., may be used to describe elements in the description and the claims, it does not imply and represent that there have other previous ordinal number.
  • the ordinal numbers do not represent the order of the elements or the manufacturing order of the elements.
  • the ordinal numbers are only used for discriminate an element with a certain designation from another element with the same designation.
  • the claims and the description may not use the same terms. Accordingly, a first element in the description may be a second element in the claims.
  • a given range is from a first value to the second value or "a given range falls within a range from a first value to a second value” refers that the given range includes the first value, the second value and other values therebetween.
  • the electronic device of the present disclosure may include a display device, a backlight device, an antenna device, a sensing device, a tiled device, a touch display device, a curved display device or a free shape display device, but not limited thereto.
  • the electronic device may exemplarily include liquid crystal, light emitting diode, fluorescence, phosphor, other suitable display media or a combination thereof, but not limited thereto.
  • the display device may be a non-self-luminous type display device or a self-luminous type display device.
  • the antenna device may be a liquid-crystal-type antenna device or a non-liquid-crystal-type antenna device.
  • the sensing device may be a device for sensing capacitance, light, thermal or ultrasonic, but not limited thereto.
  • the electronic components of the electronic device may include passive components and active components, such as capacitors, resistors, inductors, diodes, transistors, etc., but not limited thereto.
  • the diode may include a light emitting diode (LED) or a photodiode.
  • the light emitting diode may include organic light emitting diode (OLED), mini LED, micro LED or quantum dot LED, but not limited thereto.
  • the tiled device may exemplarily be a tiled display device or a tiled antenna device, but not limited thereto.
  • the electronic device may be any combination of aforementioned devices, but not limited thereto.
  • the electronic devices may be foldable or flexible electronic devices.
  • the electronic device may be any combination of aforementioned devices, but not limited thereto.
  • a shape of the electronic device may be a rectangle, a circle, a polygon, a shape with curved edge or other suitable shape.
  • the electronic device may have peripheral systems, such as a driving system, a control system, a light system, etc., for supporting the display device, the antenna device or the tiled device.
  • a depth, a thickness, a width or a height of each element, or a space or a distance between elements may be measured by an optical microscopy (OM), a scanning electron microscope (SEM), a film thickness profiler ( ⁇ -step), an ellipsometer or other suitable methods.
  • OM optical microscopy
  • SEM scanning electron microscope
  • ⁇ -step film thickness profiler
  • ellipsometer ellipsometer
  • a cross-sectional image including elements to be measured can be obtained by the SEM, and the depth, the thickness, the width or the height of each element, or the space or the distance between elements can be measured thereby.
  • one element "overlap" with another element refers that at least of a portion of the element overlap with at least a portion of the another element along a direction.
  • FIG. 1 is a schematic diagram showing a top view of an electronic device 10 according to an embodiment of the present disclosure.
  • FIG. 2A is a schematic diagram showing a partial cross-sectional view taken along line A-A' of the electronic device 10 shown in FIG. 1 .
  • FIG. 2B is a schematic diagram showing a partial cross-sectional view taken along line B-B' of the electronic device 10 shown in FIG. 1 .
  • the electronic device 10 is applied as a display device, but not limited thereto.
  • the electronic device 10 may also include other functions, such as touch and detection, but not limited thereto.
  • the electronic device 10 may include a virtual reality electronic device.
  • the electronic device 10 has a plurality of sub-pixels 11, and the plurality of sub-pixels 11 are arranged along a first direction (such as direction X) and a second direction (such as direction Y) to form a sub-pixel matrix.
  • first sub-pixel 11a, the second sub-pixel 11b and the third sub-pixel 11c are labeled exemplarily.
  • the shape of the sub-pixel 11 can be adjusted according to product requirements.
  • the electronic device 10 is exemplary a flat electronic device. In other embodiments of the present disclosure, the electronic device 10 may be a non-flat electronic device such as a curved electronic device.
  • the electronic device 10 may include a substrate 100 and an opposite substrate 200, and the opposite substrate 200 is disposed corresponding to the substrate 100.
  • the electronic device 10 may further include a display medium layer 300 disposed between the substrate 100 and the opposite substrate 200.
  • the display medium layer 300 is a liquid crystal layer, but not limited thereto.
  • the electronic device 10 may further include a sealant layer (not shown) disposed between the substrate 100 and the opposite substrate 200. The sealant layer may be used to bond the substrate 100 and the opposite substrate 200, so as to encapsulate the display medium layer 300 between the substrate 100 and the opposite substrate 200.
  • the substrate 100 may be exemplary an array substrate or a driving substrate.
  • the driving substrate refers to a substrate formed with a thin-film transistor (TFT) and/or an indium tin oxide (ITO) electrode.
  • the substrate 100 is exemplarily formed with the thin-film transistor.
  • a patterned light shielding layer 112, an insulating layer 110, a patterned semiconductor layer 122, an insulating layer 120 (such as a gate dielectric layer), a patterned first metal layer ML1 (shown in FIG. 1 ), an insulating layer 130, a patterned second metal layer ML2, an insulating layer 140 and an insulating layer 150 may be sequentially formed on an upper surface M3 of the substrate 100 from bottom to top.
  • the insulating layer 110 covers the light shielding layer 112.
  • the insulating layer 120 is located between the semiconductor layer 122 and the first metal layer ML1.
  • the insulating layer 140 covers the second metal layer ML2.
  • a plurality of the gate lines 124 extending along the direction X may be formed in the first metal layer ML1.
  • a plurality of data lines 142 and a plurality of drains 144 may be formed in the second metal layer ML2.
  • the data lines 142 may extend along the direction Y and intersect with the gate lines 124. In some embodiments, the extending direction of the gate lines 124 may not be perpendicular to the extending direction of the data lines 142.
  • the semiconductor layer 122, a portion of the gate line 124 corresponding to the semiconductor layer 122, a portion of the data line 142 (as the source) and the drain 144 form a thin film transistor as the driving element 12.
  • the pixel electrodes 160 and the common electrode 180 are disposed on the insulating layer 150.
  • the insulating layer 170 is disposed between the pixel electrodes 160 and the common electrode 180 to electrically separate the pixel electrodes 160 and the common electrode 180.
  • the insulating layer 150 has a plurality of vias 151. Each of the via 151 is configured to expose at least a portion of the drain 144.
  • the pixel electrode 160 is electrically connected to the drain 144 through the via 151.
  • the insulating layer 120 and the insulating layer 130 are formed with holes HH (see FIG. 1 , the position of the holes HH are shown by dotted lines in FIG. 1 ).
  • the extending direction of the hole HH is substantially parallel to the extending direction of the gate line 124, both of which are parallel to the first direction.
  • the portion of the data line 142 as the source can be electrically connected with the corresponding semiconductor layer 122 through the hole HH, and the drain 144 can also be electrically connected with the corresponding semiconductor layer 122 through the hole HH.
  • the driving element 12 is disposed on the substrate 100, the insulating layer 150 is disposed on the driving element 12, the insulating layer 150 has the vias 151, the pixel electrodes 160 are disposed on the insulating layer 150, and the pixel electrodes 160 are electrically connected with the driving element 12 through the vias 151.
  • a light shielding layer 210, a color filter layer 220 and an insulating layer 230 may be sequentially formed on the inner surface M6 of the opposite substrate 200 from top to bottom.
  • the light shielding layer 210 such as a black matrix layer, may include a plurality of openings 211.
  • the color filter layer 220 may include a green photoresist layer 221, a blue photoresist layer 222 and/or a red photoresist layer 223. At least a portion of the color filter layer 220 overlaps with the openings 211 of the light shielding layer 210, so as to adjust the color of light passing through each of the openings 211.
  • the first sub-pixel 11a, the second sub-pixel 11b and the third sub-pixel 11c may be respectively corresponding to the green photoresist layer 221, the blue photoresist layer 222 and the red photoresist layer 223 of the color filter layer 220, but not limited thereto.
  • the materials of the insulating layer 230 may include but are not limited to transparent organic materials such as photoresist materials.
  • at least parts of the layers and/or elements on the opposite substrate 200 may be disposed on the substrate 100, but not limited thereto.
  • one side of the electronic device 10 may also be disposed with a backlight element (not shown).
  • the backlight element can be disposed below the substrate 100.
  • the backlight element may include light emitting diodes (LEDs), submillimeter light emitting diodes (mini LEDs), micro light emitting diodes (micro LEDs), quantum dots (QDs), quantum dot light emitting diodes (QLEDs, QD-LEDs), fluorescence, phosphor, other suitable materials, or a combination thereof, but not limited thereto.
  • LEDs light emitting diodes
  • mini LEDs submillimeter light emitting diodes
  • micro LEDs micro light emitting diodes
  • QDs quantum dots
  • QLEDs, QD-LEDs quantum dot light emitting diodes
  • fluorescence phosphor, other suitable materials, or a combination thereof, but not limited thereto.
  • the substrate 100 and the opposite substrate 200 may exemplary be flexible or inflexible substrates.
  • the substrate 100 and the opposite substrate 200 may be transparent substrates, and the materials thereof may exemplarily include glass, quartz, sapphire, polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), other suitable materials or a combination thereof, but not limited thereto.
  • the insulating layer 110, the insulating layer 120, the insulating layer 130, the insulating layer 140 and the insulating layer 170 may include inorganic materials (such as silicon oxide, silicon nitride, silicon oxynitride, or stacking layers including at least two of the aforementioned materials).
  • the insulating layer 150 may exemplarily include organic materials (such as polyimide resin, epoxy resin or acrylic resin), but not limited thereto.
  • Materials of the semiconductor layer 122 may exemplarily include amorphous silicon, low temperature polysilicon (LTPS), metal oxides (such as indium gallium zinc oxide (IGZO)), other suitable materials or a combination thereof.
  • some components disposed on the substrate 100 and the opposite substrate 200 are omitted for the sake of simplification, such as the insulating layer 110, the insulating layer 120, the insulating layer 130, the insulating layer 140, the insulating layer 150, the light shielding layer 112, the pixel electrodes 160, the common electrode 180, the insulating layer 170 on the substrate 100, and the color filter layer 220 and the insulating layer 230 on the opposite substrate 200.
  • the display medium layer 300 is also omitted in FIG. 1 .
  • sub-pixel may refer to all film layers (at least including the pixel electrode 160, a portion of the common electrode 180 and the corresponding driving element 12) along the normal direction (i.e., the direction Z) in the area surrounded by two adjacent data lines 142 and two adjacent gate lines 124.
  • the electronic device 10 may further include the spacer 310.
  • the gate lines 124 are disposed on the substrate 100 and extend along the first direction (such as the direction X).
  • the spacer 310 is disposed on the gate line 124 and overlaps with the gate line 124.
  • the spacer 310 has a first width W1 along the first direction, one of the plurality of sub-pixels 11 has a sub-pixel pitch P along the first direction, and the first width W1 and the sub-pixel pitch P satisfy the following relationship: P ⁇ W1 (Formula (1)).
  • P ⁇ W1 (Formula (1)).
  • the first width W1 and the sub-pixel pitch P may satisfy the following relationship: P ⁇ W1 ⁇ 3 ⁇ P (Formula (2)).
  • the aforementioned "the spacer 310 overlaps with the gate line 124" may refer that at least a portion of the spacer 310 overlaps with at least a portion of the gate line 124 in the top view (for example, the view angle parallel to the direction Z).
  • the aforementioned "sub-pixel pitch P", taking the direction X as an example, may refer to the distance between the same edges (left edge or right edge) of two adjacent data lines 142 or the distance between two center lines (not shown) of two adjacent data lines 142.
  • the sub-pixel pitch P are exemplary the distance between two right edges of two adjacent data lines 142 and the distance between two left edges of two adjacent data lines 142.
  • the spacer 310 exemplarily includes a main spacer 311 and a sub-spacer 312.
  • the main spacer 311 is disposed on the gate line 124 (the gate line 124 at the lower position of FIG. 1 ), and at least a portion of the main spacer 311 overlaps with at least a portion of the gate line 124 (the gate line 124 at the lower position of FIG. 1 ).
  • the main spacer 311 has a width W11 along the first direction, which satisfies the following relationship: P ⁇ W11 ⁇ 3 ⁇ P.
  • the sub-spacer 312 is disposed on the gate line 124 (the gate line 124 at the upper position of FIG.
  • the sub-spacer 312 has a width W 12 along the first direction, which satisfies the following relationship: P ⁇ W12 ⁇ 3 ⁇ P.
  • the aforementioned "first width W1" of the spacer 310 may be the width W11 of the main spacer 311 or the width W12 of the sub-spacer 312. In other words, at least one of the width W11 of the main spacer 311 and the width W12 of the sub-spacer 312 satisfying Formula (1) or Formula (2) is within the scope of the present disclosure.
  • widths of the main spacer 311 and the sub-spacer 312 may change gradually along the direction Z.
  • Atop surface M1 of the main spacer 311 and a top surface M2 of the sub-spacer 312 may be flat surfaces.
  • the present disclosure is not limited thereto.
  • the top surface M1 of the main spacer 311 and the top surface M2 of the sub-spacer 312 may be non-flat surfaces, such as curved surfaces which protrude upwardly.
  • the width W11 of the main spacer 311 may be the maximum width of the main spacer 311 along the first direction
  • the width W12 of the sub-spacer 312 may be the maximum width of the sub-spacer 312 along the first direction.
  • the width W11 of the main spacer 311 may be the maximum width of the projection of the main spacer 311 on the XY plane along the first direction
  • the width W12 of the sub-spacer 312 may be the maximum width of the sub-spacer 312 on the XY plane along the first direction.
  • two opposite ends of "the main spacer 311" (such as the two opposite ends along the direction Z) may respectively contact the film layer on the substrate 100 and the film layer on the opposite substrate 200.
  • one of the two opposite ends of "the sub-spacer 312" may be disposed on one of the substrate 100 and the opposite substrate 200, and the other end of the sub-spacer 312 does not contact with the other one of the substrate 100 and the opposite substrate 200 when the electronic device 10 is not pressed.
  • the materials of the spacer 310 may include photoresist materials, but the present disclosure is not limited thereto.
  • the main spacer 311 and the sub-spacer 312 are disposed on the substrate 100 and are located between the substrate 100 and the opposite substrate 200.
  • the main spacer 311 has a first height H1, the sub-spacer 312 has a second height H2, and the first height H1 is greater than the second height H2.
  • the electronic device 10 may further include a first pattern 410 and a second pattern 420.
  • the first pattern 410 is disposed between the opposite substrate 200 and the main spacer 311.
  • the second pattern 420 is disposed between the opposite substrate 200 and the sub-spacer 312.
  • the first pattern 410 has a first thickness T1, the second pattern 420 has a second thickness T2, and the first thickness T1 may be equal to the second thickness T2.
  • the first height H1 may be the maximum distance between the top surface M1 of the main spacer 311 and the upper surface M3 of the substrate 100 along the normal direction.
  • the second height H2 may be the maximum distance between the top surface M2 of the sub-spacer 312 and the upper surface M3 of the substrate 100 along the normal direction.
  • the aforementioned first thickness T1 may be the protruding length or protruding height of the first pattern 410 along the normal direction.
  • the first thickness T1 may be the maximum protruding height of the first pattern 410 relative to the inner surface M4 of the insulating layer 230 along the normal direction.
  • the aforementioned second thickness T2 may be the protruding length or protruding height of the second pattern 420 along the normal direction.
  • the second thickness T2 may be the maximum protruding height of the second pattern 420 relative to the inner surface M4 of the insulating layer 230 along the normal direction.
  • the first pattern 410 abuts against the main spacer 311 to form a cell gap between the substrate 100 and the opposite substrate 200.
  • the cell gap can be used to accommodate other components of the electronic device 10, such as the display medium layer 300.
  • the first pattern 410 and the second pattern 420 With the first pattern 410 and the second pattern 420, the first height H1 and the second height H2 can be reduced while maintaining the same cell gap.
  • alignment films (not shown) will be coated on the inner sides of the substrate 100 and the opposite substrate 200 after desired film layers are formed on the substrate 100 and the opposite substrate 200.
  • the materials of the alignment film may include but are not limited to polyimide (PI).
  • the probability of scratching the alignment films due to the shift of the spacer 310 when assembling the substrate 100 and the opposite substrate 200 may be reduced, and the alignment film halo and the range of poor alignment (such as poor alignment of liquid crystals) can be reduced.
  • the first thickness T1 being equal to the second thickness T2, it is beneficial to simplify the manufacturing process of the first pattern 410 and the second pattern 420.
  • the first pattern 410 and the second pattern 420 may be made of transparent or opaque materials.
  • the materials of the first pattern 410 and the second pattern 420 may be independently identical to the materials or the paints of the light shielding layer 210, the insulating layer 230 or the spacer 310.
  • the materials of the first pattern 410 and the second pattern 420 may be the same or similar to that of the spacer 310.
  • the materials of the first pattern 410 and the second pattern 420 may include conductive materials (such as metal or ITO) or insulating materials, but the present disclosure is not limited thereto.
  • a first distance S1 is between the main spacer 311 and the first pattern 410
  • a second distance S2 is between the sub-spacer 312 and the second pattern 420
  • the first distance S1 is smaller than the second distance S2.
  • the main spacer 311 abuts against the first pattern 410
  • the first distance S1 is 0.
  • the sub-spacer 312 does not abut against the second pattern 420
  • the second distance S2 is greater than 0.
  • the first height H1 of the main spacer 311 may be equal to the second height H2 of the sub-spacer 312.
  • the electronic device 10 may only include the first pattern 410 but does not include the second pattern 420.
  • the first pattern 410 may be disposed between the opposite substrate 200 and the main spacer 311, and the first pattern 410 abuts against the main spacer 311. Thereby, it is beneficial to simplify the manufacturing process of the main spacer 311 and the sub-spacer 312.
  • one mask process can be omitted, or a complicated half-grayscale mask to fabricate the main spacer 311 and the sub-spacer 312 with different heights is not required, and the cost can be reduced.
  • the color filter layer 220 is disposed between the first pattern 410 and the opposite substrate 200.
  • both the first pattern 410 and the second pattern 420 are disposed corresponding to the blue photoresist layer 222, but not limited thereto.
  • the first pattern 410 and the second pattern 420 may be independently disposed corresponding to the green photoresist layer 221, the blue photoresist layer 222 or the red photoresist layer 223.
  • the color filter layer 220 may also be disposed between the substrate 100 and the spacer 310, but the present disclosure is not limited thereto.
  • the main spacer 311 has a long axis direction (such as the direction X) parallel to the first direction, and the main spacer 311 overlaps with the gate line 124 (the gate line 124 at the lower position of FIG. 1 ).
  • the main spacer 311 has a rectangular shape in the top view, wherein the long axis direction is corresponding to the long side direction of the rectangular shape and is parallel to the extending direction of the gate line 124.
  • FIG. 2B at least a portion of the main spacer 311 is disposed in the via 151.
  • at least a portion of the sub-spacer 312 is disposed in the via 151.
  • the four corners of the "rectangle" may be non-right angles, such as rounded angles or arc-shaped angles.
  • FIG. 3A is a schematic diagram showing an enlarged top view of a main spacer 311 and a first pattern 410 according to an embodiment of the present disclosure.
  • the main spacer 311 has a second width W2 along the second direction perpendicular to the first direction (i.e., the length along the short axis direction of the main spacer 311).
  • the first pattern 410 has a protruding distance PD relative to the main spacer 311 along the second direction, and the second width W2 and the protruding distance PD may satisfy the following relationship: PD > 0.05 ⁇ W2 (Formula (3)).
  • the long axis is defined as a straight line extending lengthwise through a center of an object.
  • the long axis is closest to its maximal longitudinal dimension.
  • the long axis may refer to a long side of a smallest rectangle that can enclose the object.
  • the first pattern 410 has a first protruding distance PD1 relative to the main spacer 311 along the second direction, which satisfies the following relationship: PD1 > 0.05 ⁇ W2.
  • the first pattern 410 has a second protruding distance PD2 relative to the main spacer 311 along the second direction, which satisfies the following relationship: PD2 > 0.05 ⁇ W2.
  • the first protruding distance PD1 may be equal to or unequal to the second protruding distance PD2.
  • the protruding distance PD may be the first protruding distance PD1 or the second protruding distance PD2.
  • first protruding distance PD1 and the second protruding distance PD2 satisfying Formula (3) is within the scope of the present disclosure.
  • both sides of the first pattern 410 protrude relative to the main spacer 311 along the second direction, but the present disclosure is not limited thereto.
  • the first pattern 410 may unilaterally protrude relative to the main spacer 311.
  • the first pattern 410 has a first area A1
  • the first pattern 410 and the main spacer 311 have an overlapping area AA
  • the first area A1 and the overlapping area AA satisfy the following relationship: AA > 0.05 ⁇ A1.
  • the first area A1 and the overlapping area AA may satisfy the following relationship: AA > 0.3 ⁇ A1.
  • the abutting area is smaller, and the influence on the opening rate of the pixel caused by the offset can be reduced.
  • the present disclosure is not limited thereto.
  • the first pattern 410 and the main spacer 311 may be independently arranged as other shapes according to actual needs, such as square, rhombus, ellipse, etc.
  • FIG. 3B is a schematic diagram showing an enlarged top view of a main spacer 311 and a first pattern 410' according to another embodiment of the present disclosure.
  • the difference between FIG. 3A and FIG. 3B is that the first pattern 410' is arranged as an ellipse, so that the overlapping area AA is larger. That is, the abutting area is larger, which can improve the stability of the cell gap between the substrate 100 and the opposite substrate 200.
  • FIG. 3A is a schematic diagram showing an enlarged top view of a main spacer 311 and a first pattern 410' according to another embodiment of the present disclosure.
  • the first pattern 410' is arranged as an ellipse, so that the overlapping area AA is larger. That is, the abutting area is larger, which can improve the stability of the cell gap between the substrate 100 and the opposite substrate 200.
  • FIG. 3A is a schematic diagram showing an enlarged top view of a main spacer 311 and a first pattern 410' according to another
  • FIG. 4 is a schematic diagram showing a top view of an electronic device 10a according to another embodiment of the present disclosure
  • FIG. 6 is a schematic diagram showing a partial cross-sectional view taken along line A-A' of the electronic device 10a shown in FIG. 4 .
  • FIG. 4 shows a first pattern 410a and a second pattern 420a extending along the first direction.
  • the main difference between the electronic device 10a and the electronic device 10 is the arrangement of the first pattern 410a and the second pattern 420a.
  • the first pattern 410a includes a first blocking portion 411a and a second blocking portion 412a
  • the second pattern 420a includes a third blocking portion 421a and a fourth blocking portion 422a.
  • the first blocking portion 411a, the second blocking portion 412a, the third blocking portion 421a and the fourth blocking portion 422a may be integrally formed on the inner surface M4 of the insulating layer 230 and extend outwardly and parallel to the normal direction (such as the direction Z), but not limited thereto.
  • the first pattern 410a and the second pattern 420a may also include other material layers formed on the inner surface M4 of the insulating layer 230.
  • a first inserting space CS1 is formed between the first blocking portion 411a and the second blocking portion 412a
  • a second inserting space CS2 is formed between the third blocking portion 421a and the fourth blocking portion 422a.
  • Each of the first inserting space CS1 and the second inserting space CS2 has a rectangular shape or a strip shape in the top view.
  • each of the first blocking portion 411a, the second blocking portion 412a, the third blocking portion 421a, and the fourth blocking portion 422a has a rectangular shape or a strip shape in the top view.
  • the rectangle shape or the strip shape has a long axis direction parallel to the first direction (such as the direction X).
  • the first pattern 410a and the second pattern 420a do not overlap with the main spacer 311 and the sub-spacer 312, and the first pattern 410a and the second pattern 420a partially overlap with the via 151.
  • the sub-spacer 312 is disposed corresponding to the via 151. That is, at least a portion of the sub-spacer 312 is located in the via 151.
  • the third blocking portion 421a and the sub-spacer 312 have a third overlapping thickness TT3 along the normal direction (such as the direction Z), the fourth blocking portion 422a and the sub-spacer 312 have a fourth overlapping thickness TT4 along the normal direction (such as the direction Z), and the third overlapping thickness TT3 is equal to the fourth overlapping thickness TT4.
  • the first blocking portion 411a and the main spacer 311 have a first overlapping thickness (not shown) along the normal direction (such as the direction Z)
  • the second blocking portion 412a and the main spacer 311 have a second overlapping thickness (not shown) along the normal direction (such as the direction Z)
  • the first overlapping thickness is equal to the second overlapping thickness.
  • the main spacer 311 is inserted in the first inserting space CS1 between the first blocking portion 411a and the second blocking portion 412a, and the sub-spacer 312 is inserted in the second inserting space CS2 between the third blocking portion 421a and the fourth blocking portion 422a, which is beneficial to limit the displacement degree of the main spacer 311 and the sub-spacer 312 along the second direction.
  • the second height H2 of the sub-spacer 312 is smaller than the first height H1 of the main spacer 311 (refer to FIG. 2B ).
  • the sub-spacer 312 does not abut against the inner surface M4 of the insulating layer 230, and the main spacer 311 abuts against the inner surface M4 of the insulating layer 230(not shown).
  • the materials of the first pattern 410a and the second pattern 420a may include transparent materials or opaque materials.
  • the transparent materials may exemplarily include oxides, nitrides, indium tin oxides, organic materials, inorganic materials or a combination thereof
  • the opaque materials may exemplarily include, photoresist materials, resins, metals, etc., but the present disclosure is not limited thereto.
  • FIG. 5 is a schematic diagram showing a top view of an electronic device 10b according to yet another embodiment of the present disclosure. Since the partial cross-sectional view taken along line A-A' of the electronic device 10b shown in FIG. 5 is identical to that of the electronic device 10a shown in FIG. 4 , please refer to FIG. 6 simultaneously.
  • the main difference between the electronic device 10b and the electronic device 10a is the arrangement of the first pattern 410b and the second pattern 420b.
  • the first pattern 410b includes a first blocking portion 411a, a second blocking portion 412a and a first connecting portion 413a.
  • the first connecting portion 413a is connected between the first blocking portion 411a and the second blocking portion 412a.
  • the second pattern 420a includes a third blocking portion 421a, a fourth blocking portion 422a and a second connecting portion 423a.
  • the second connecting portion 423a is connected between the third blocking portion 421a and the fourth blocking portion 422a.
  • the first blocking portion 411a, the second blocking portion 412a and the first connecting portion 413a may be integrally formed on the inner surface M4 of the insulating layer 230 and extend outwardly and parallel to the normal direction, so as to form a first inserting space CS1 between the first blocking portion 411a, the second blocking portion 412a and the first connecting portion 413a.
  • the third blocking portion 421a, the fourth blocking portion 422a and the second connecting portion 423a may be integrally formed on the inner surface M4 of the insulating layer 230 and extend outwardly and parallel to the normal direction, so as to form a second inserting space CS2 between the third blocking portion 421a, the fourth blocking portion 422a and the second connecting portion 423a.
  • Each of the first inserting space CS1 and the second inserting space CS2 has a rectangular shape, an elliptical shape or other suitable shape in the top view, but the present disclosure is not limited thereto.
  • the main spacer 311 is inserted in the first inserting space CS1, and the sub-spacer 312 is inserted in the second inserting space CS2.
  • the second height H2 of the sub-spacer 312 is smaller than the first height H1 of the main spacer 311 (refer to FIG. 2B ).
  • the sub-spacer 312 does not abut against the inner surface M4 of the insulating layer 230, and the main spacer 311 abuts against the inner surface M4 of the insulating layer 230 (not shown).
  • the materials of the first pattern 410b and the second pattern 420b may include transparent materials or opaque materials. For other details of the electronic device 10b, references may be made to that of the electronic device 10a.
  • FIG. 7 is a schematic diagram showing a top view of an electronic device 10c according to yet another embodiment of the present disclosure
  • FIG. 9 is a schematic diagram showing a partial cross-sectional view taken along line A-A' of the electronic device 10c shown in FIG. 7 .
  • the difference between the electronic device 10c and the electronic device 10a is the arrangement of the first pattern 410c and the second pattern 420c.
  • FIG. 7 is a schematic diagram showing a top view of an electronic device 10c according to yet another embodiment of the present disclosure
  • FIG. 9 is a schematic diagram showing a partial cross-sectional view taken along line A-A' of the electronic device 10c shown in FIG. 7 .
  • the difference between the electronic device 10c and the electronic device 10a is the arrangement of the first pattern 410c and the second pattern 420c.
  • a first blocking portion 411c, a second blocking portion 412c, a third blocking portion 421c, and a fourth blocking portion 422c have longer lengths in the second direction, and the first blocking portion 411c is integrally connected with the fourth blocking portion 422c, so as to form a first inserting space CS1 between the first blocking portion 411c and the second blocking portion 412c and formed a second inserting space CS2 between the third blocking portion 421c and the fourth blocking portion 422c.
  • Each of the first inserting space CS1 and the second inserting space CS2 has a rectangular shape or a strip shape in the top view.
  • each of the first blocking portion 411c, the second blocking portion 412c, the third blocking portion 421c and the fourth blocking portion 422c has a rectangular shape or a strip shape in the top view.
  • the rectangular shape or the strip shape has a long axis direction parallel to the first direction.
  • the first pattern 410c and the second pattern 420c do not overlap with the main spacer 311 and the sub-spacer 312, and at least portions of the first pattern 410c and the second pattern 420c may partially overlap with the via 151, but the present disclosure is not limited thereto.
  • the main spacer 311 is inserted in the first inserting space CS1, and the sub-spacer 312 is inserted in the second inserting space CS2.
  • the materials of the first pattern 410c and the second pattern 420c may include transparent materials.
  • references may be made to that of the electronic device 10a.
  • FIG. 8 is a schematic diagram showing a top view of an electronic device 10d according to yet another embodiment of the present disclosure. Since the partial cross-sectional view taken along line A-A' of the electronic device 10d shown in FIG. 8 is identical to that of the electronic device 10c shown in FIG. 7 , please refer to FIG. 9 simultaneously.
  • the main difference between the electronic device 10d and the electronic device 10c is the arrangement of the first pattern 410d and the second pattern 420d.
  • the first pattern 410d includes a first blocking portion 421c, a second blocking portion 412c and a first connecting portion 413c, and the first connecting portion 413c is connected between the first blocking portion 411c and the second blocking portion 412c.
  • the second pattern 420c includes a third blocking portion 421c, a fourth blocking portion 422c and a second connecting portion 423c, and the second connecting portion 423c is connected between the third blocking portion 421c and the fourth blocking portion 422c.
  • the first blocking portion 411c, the second blocking portion 412c, and the first connecting portion 413c may be integrally formed on the inner surface M4 of the insulating layer 230 and extend outwardly and parallel to the normal direction, so as to form the first inserting space CS1 between the first blocking portion 411c, the second blocking portion 412c and the first connecting portion 413c.
  • the third blocking portion 421c, the fourth blocking portion 422c and the second connecting portion 423c may be integrally formed on the inner surface M4 of the insulating layer 230 and extend outwardly and parallel to the normal direction, so as to form the second inserting space CS2 between the third blocking portion 421c, the fourth blocking portion 422c and the second connecting portion 423c.
  • Each of the first inserting space CS1 and the second inserting space CS2 has a rectangular shape, an elliptical shape or other suitable shape in the top view, but the present disclosure is not limited thereto.
  • the main spacer 311 is inserted in the first inserting space CS1, and the sub-spacer 312 is inserted in the second inserting space CS2.
  • the materials of the first pattern 410d and the second pattern 420d may include transparent materials.
  • FIG. 10 is a schematic diagram showing a partial cross-sectional view of an electronic device 10e according to yet another embodiment of the present disclosure.
  • the view angle of FIG. 10 is identical to that of FIG. 6 .
  • the differences between the electronic device 10e and the electronic device 10a are explained below.
  • the spacer 310 includes a main spacer (not shown) and a sub-spacer 312, the main spacer (not shown) and the sub-spacer 312 are disposed on the inner surface M6 of the opposite substrate 200. Specifically, the main spacer (not shown) and the sub-spacer 312 are disposed on the inner surface M4 of the insulating layer 230.
  • the electronic device 10e further includes an insulating layer 190.
  • the insulating layer 190 is disposed on the insulating layer 150. Specifically, the insulating layer 190 may be disposed on the common electrode 180. In other embodiments, the insulating layer 190 may be disposed under the common electrode 180, such as disposed between the drain 144 and the common electrode 180.
  • a third blocking portion 421e and a fourth blocking portion 422e of the second pattern 420e are integrally formed on the top surface M5 of the insulating layer 190 and extend outwardly and parallel to the normal direction, so as to form a second inserting space CS2 between the third blocking portion 421e and the fourth blocking portion 422e.
  • first blocking portion and the second blocking portion of the first pattern are integrally formed on the top surface M5 of the insulating layer 190 and extend outwardly and parallel to the normal direction, so as to form a first inserting space (not shown) between the first blocking portion and the second blocking portion.
  • the main spacer is inserted in the first inserting space
  • the sub-spacer 312 is inserted in the second inserting space CS2.
  • the second height H2 of the sub-spacer 312 is smaller than the first height of the main spacer (not shown).
  • the first height may be the maximum distance between the top surface of the main spacer (not shown) and the inner surface M6 of the opposite substrate 200 along the normal direction.
  • the second height H2 may be the maximum distance between the top surface M2 of the sub-spacer 312 and the inner surface M6 of the opposite substrate 200 along the normal direction.
  • the electronic device 10b of FIG. 5 may further include an insulating layer 190 (refer to FIG.
  • the insulating layer 190 is disposed on the insulating layer 150.
  • the insulating layer 190 may be disposed on the common electrode 180.
  • the spacer 310 may be changed to be disposed on the inner surface M4 of the insulating layer 230, and the first pattern 410b and the second pattern 420b may be changed to be integrally formed on the top surface M5 of the insulating layer 190 and extend outwardly and parallel to the normal direction.
  • the effect of limiting the displacement degree of the main spacer 311 and the sub-spacer 312 along the first direction and the second direction can be achieved, too.
  • the electronic device 10c shown in FIG. 7 may further include an insulating layer 190 (refer to FIG. 10 ).
  • the insulating layer 190 is disposed on the insulating layer 150.
  • the insulating layer 190 may be disposed on the common electrode 180
  • the spacer 310 may be changed to be disposed on the inner surface M4 of the insulating layer 230
  • the first pattern 410c and the second pattern 420c shown in FIG. 7 may be changed to integrally formed on the top surface M5 of the insulating layer 190 and extend outwardly and parallel to the normal direction.
  • the effect of limiting the displacement degree of the main spacer 311 and the sub-spacer 312 along the second direction can be achieved, too.
  • the electronic device 10d shown in FIG. 8 may further include an insulating layer 190 (refer to FIG. 10 ).
  • the insulating layer 190 is disposed on the insulating layer 150.
  • the insulating layer 190 may be disposed on the common electrode 180, the spacer 310 can be changed to be disposed on the inner surface M4 of the insulating layer 230, and the first pattern 410d and the second pattern 420d may be changed to integrally formed on the top surface M5 of the insulating layer 190 and extend outwardly and parallel to the normal direction.
  • the effect of limiting the displacement degree of the main spacer 311 and the sub-spacer 312 along the first direction and the second direction can be achieved, too.
  • the electronic devices 10a, 10b, 10c, 10d and 10e when the electronic devices 10a, 10b, 10c, 10d and 10 are applied as liquid crystal display devices, the probability of the spacer 310 scratching the alignment film can be reduced, and the loss of the opening rate caused by the offset when assembling the substrate 100 and the opposite substrate 200 can also be reduced. With the arrangement of the electronic devices 10b and 10d, the assembling accuracy along the first direction and the second direction can be further controlled.
  • the first patterns 410a, 410b, 410c and 410d and the second patterns 420a, 420b, 420c, 420d and 420e may be formed on the existing layers (such as the insulating layer 230 and the insulating layer 190).
  • the existing layers such as the insulating layer 230 and the insulating layer 190.
  • FIG. 11 is a schematic diagram showing a top view of an electronic device 10f according to yet another embodiment of the present disclosure
  • FIG. 12 is a schematic diagram showing partial cross-sectional views taken along line A-A' and line B-B' of the electronic device 10f shown in FIG. 11
  • the data line 142 is disposed on the substrate 100 and has an extending direction (such as the direction parallel to the direction Y).
  • the spacer 310 is disposed between the substrate 100 and the opposite substrate 200
  • the first pattern 410f is disposed between the data line 142 and the spacer 310 and extends along the extending direction, wherein the first pattern 410f overlaps with the data line 142.
  • the spacer 310 is disposed on the inner surface M6 of the opposite substrate 200. Specifically, the spacer 310 is disposed on the inner surface M4 of the insulating layer 230.
  • the spacer 310 includes a main spacer 311 and a sub-spacer 312.
  • the main spacer 311 has a first height H1
  • the sub-spacer 312 has a second height H2
  • the first height H1 is greater than the second height H2.
  • Each of the data lines 142 is correspondingly disposed with the first pattern 410f, wherein the main spacer 311 abuts against the first pattern 410f, and the sub-spacer 312 does not abut against the first pattern 410f.
  • the present disclosure is not limited thereto.
  • the first height H1 of the main spacer 311 may be equal to the second height H2 of the sub-spacer 312, the data line 142 corresponding to the main spacer 311 may be disposed with the first pattern 410f, so that the main spacer 311 abuts against the first pattern 410f, while the data line 142 corresponding to the sub-spacer 312 is not disposed with the first pattern 410f, so that the sub-spacer 312 does not abut against the first pattern 410f. That is, there may be a spaced distance between the sub-spacer 312 and the common electrode 180. With the first height H1 being equal to the second height H2, it is beneficial to simplify the manufacturing process of the spacer 310.
  • the first pattern 410f has a rectangular shape or a strip shape in the top view and extends along the extending direction of the data line 142, but not limited thereto.
  • the first pattern 410f is staggered with the opening 211 and does not overlap with the opening 211.
  • the electronic device 10f is applied as a liquid crystal display device, with the first pattern 410f, it is beneficial to reduce the probability of scratching the alignment film corresponding to the opening 211 caused by the shift of the spacer 310. Accordingly, the light shielding range corresponding to the spacer 310 can be reduced, which is beneficial to maintain the opening rate.
  • the first pattern 410f has a width W3 along the first direction.
  • the width W3 may be less than 10 ⁇ m, and no alignment film is formed on the first pattern 410f, which can prevent the spacer 310 from scratching the alignment film, but not limited thereto.
  • the materials of the first pattern 410f may include conductive materials with low reflectivity, such as molybdenum (Mo), titanium (Ti), chromium (Cr) or oxides thereof.
  • the materials of the first pattern 410f may include transparent conductive materials (such as ITO). When the materials of the first pattern 410f include the conductive materials, the electrical properties of the common electrode 180 can be improved by the electrical connection between the first pattern 410f and the common electrode 180.
  • the materials of the first pattern 410f may also include non-conductive materials, such as a silicon nitride (SiNx), a silicon oxide (SiOx) or a photoresist material, which can reduce the influence on the electric field of the pixel.
  • non-conductive materials such as a silicon nitride (SiNx), a silicon oxide (SiOx) or a photoresist material, which can reduce the influence on the electric field of the pixel.
  • the materials of the first pattern 410f include transparent materials, it is beneficial to reduce the loss of the opening rate caused by the process variation.
  • the materials of the first pattern 410f include non-transparent materials, it is beneficial to shield the reflection of the metals (such as the data line 142).
  • the data line 142 has a width W4 along the first direction, and the width W3 is greater than the width W4, meanwhile the material of the first pattern 410 includes the non-transparent materials.
  • the width W3 may be smaller than the width W4, which is beneficial to reduce the influence on the alignment of the liquid crystal in the display area.
  • the aforementioned width W3 may be the distance between the left edge and the right edge of the first pattern 410f along the first direction, and the aforementioned width W4 may be the distance between the left edge and the right edge of the data line 142 along the first direction.
  • FIG. 13 is a schematic diagram showing a top view of an electronic device 10g according to yet another embodiment of the present disclosure.
  • FIG. 14 is a schematic diagram showing partial cross-sectional views taken along line A-A' and line B-B' of the electronic device 10g shown in FIG. 13 .
  • the main difference between the electronic device 10g and the electronic device 10f is the arrangement of the first pattern 410g of the electronic device 10g.
  • the data line 142 is disposed on the substrate 100 and has an extending direction (such as a direction parallel to the direction Y).
  • the spacer 310 is disposed between the substrate 100 and the opposite substrate 200.
  • the first pattern 410g is disposed between the data line 142 and the spacer 310 and extending along the extending direction.
  • the first pattern 410g overlaps with the data line 142.
  • the electronic device 10g may further include gate lines 124 disposed on the substrate 100, wherein the gate lines 124 intersects with the data lines 142, and the gate lines 124 overlap with the first pattern 410g.
  • the data line 142 has an extending direction (such as a direction parallel to the direction Y)
  • the gate line 124 has an extending direction (such as a direction parallel to the direction X) perpendicular to the extending direction of the data line 142.
  • the first pattern 410g extends along the extending direction of the data line 142 and the extending direction of the gate line 124, and the first pattern 410g overlaps with the data line 142 and the gate line 124 at the same time.
  • the first pattern 410g and the opening 211 are staggered and do not overlap with each other.
  • the spacer 310 is disposed on the inner surface M4 of the insulating layer 230.
  • the spacer 310 includes a main spacer 311 and a sub-spacer 312.
  • the main spacer 311 has a first height H1, the sub-spacer 312 has a second height H2, and the first height H1 is greater than the second height H2.
  • the first height H1 of the main spacer 311 may be equal to the second height H2 of the sub-spacer 312, the first pattern 410g is disposed between the data line 142 and the main spacer 311, and the first pattern 410g is not disposed between the data line 142 and the sub-spacer 312, so that the main spacer 311 abuts against the first pattern 410g, and the sub-spacer 312 does not abut against the first pattern 410g. That is, there may be a spaced distance between the sub-spacer 312 and the common electrode 180. With the first height H1 being equal to the second height H2, it is beneficial to simplify the manufacturing process of the spacer 310.
  • FIG. 15 is a schematic diagram showing a top view of an electronic device 10i according to yet another embodiment of the present disclosure
  • FIG. 16 is a schematic diagram showing a partial cross-sectional view taken along line A-A' of the electronic device 10i shown in FIG. 15
  • FIG. 17 is a schematic diagram showing a partial cross-sectional view taken along line B-B' of the electronic device 10i shown in FIG. 15 .
  • the light shielding layer 210 on the opposite substrate 200 is further omitted in FIG. 15 for the sake of simplification.
  • the electronic device 10i includes a first pattern 410i and a second pattern 420i. As shown in FIG.
  • the first pattern 410i has a long axis direction parallel to the second direction (such as the direction Y), and the first pattern 410i overlaps with the gate line 124 (the gate line 124 at the lower position of FIG. 15 ).
  • the first pattern 410i has a rectangular shape in the top view, wherein the long axis direction is corresponding to the long side direction of the rectangular shape and is perpendicular to the extending direction of the gate line 124.
  • the second pattern 420i has a long axis direction parallel to the second direction, and the second pattern 420i overlaps with the gate line 124 (the gate line 124 at the upper position of FIG. 15 ).
  • the second pattern 420i has a rectangular shape in the top view, wherein the long axis direction is corresponding to the long side direction of the rectangular shape and is perpendicular to the extending direction of the gate line 124.
  • the spacer 310 includes a main spacer 311 and a sub-spacer 312.
  • the main spacer 311 has a long axis direction parallel to the first direction (such as the direction X), and the main spacer 311 overlaps with the gate line 124 (the gate line 124 at the lower position in FIG. 15 ).
  • the sub-spacer 312 has a long axis direction parallel to the first direction, and the sub-spacer 312 overlaps with the gate line 124 (the gate line 124 at the upper position of FIG.
  • each of the main spacer 311 and the sub-spacer 312 have a strip shape in the top view, and a long axis direction of the strip shape is parallel to the first direction.
  • the length of each of the main spacer 311 and the sub-spacer 312 along the second direction may vary.
  • the portion of the main spacer 311 corresponding to the first pattern 410i may have a longer length
  • the portion of the sub-spacer 312 corresponding to the second pattern 420i may have a longer length, but the present disclosure is not limited thereto.
  • the main spacer 311 and the sub-spacer 312 may overlap with a plurality of vias 151.
  • each of the main spacer 311 and the sub-spacer 312 is exemplarily filled in at least one via 151, which can reduce light leakage and improve display contrast.
  • the main spacer 311 and the sub-spacer 312 are disposed on the top surface M7 of the common electrode 180.
  • the main spacer 311 has a first height H1
  • the sub-spacer 312 has a second height H2
  • the first height H1 is greater than the second height H2.
  • the first pattern 410i overlaps with the main spacer 311, and the second pattern 420i overlaps with the sub-spacer 312.
  • the first pattern 410i abuts against the main spacer 311, and the second pattern 420i does not abut against the sub-spacer 312.
  • FIG. 18 is a schematic diagram showing a top view of an electronic device 10j according to yet another embodiment of the present disclosure
  • FIG. 19 is a schematic diagram showing a partial cross-sectional view taken along line A-A' of the electronic device 10j shown in FIG. 18
  • FIG. 20 is a schematic diagram showing a partial cross-sectional view taken along line B-B' of the electronic device 10j shown in FIG. 18
  • the electronic device 10j includes an insulating layer 190.
  • the insulating layer 190 is disposed on the insulating layer 150, wherein the spacer 310 overlaps with the insulating layer 190.
  • the insulating layer 190 may be disposed between the spacer 310 and the insulating layer 150.
  • an extending direction of the insulating layer 190 is parallel to an extending direction of the gate line 124, both of which are parallel to the first direction (such as the direction X).
  • the insulating layer 190 has a rectangular shape or a strip shape in the top view, and a long axis direction of the rectangular shape or the strip shape is parallel to the first direction, but the present disclosure is not limited thereto.
  • a length of the insulating layer 190 along the second direction may vary.
  • the portion of the insulating layer 190 corresponding to the spacer 310, the first pattern 410j or the second pattern 420j may have a longer length.
  • the shape of the insulating layer 190 may be similar to the shapes of the main spacer 311 and the sub-spacer 312 in FIG. 15 .
  • the insulating layer 190 overlaps with a plurality of vias 151. In other words, at least a portion of the insulating layer 190 may be disposed in the vias 151.
  • the insulating layer 190 is entirely filled in the via 151, which is exemplary. Thereby, light leakage can be reduced and the display contrast can be improved.
  • the electronic device 10j may further include a first pattern 410j.
  • the spacer 310 is disposed between the first pattern 410j and the insulating layer 190.
  • the electronic device 10j may further include a second pattern 420j.
  • the spacer 310 is disposed between the second pattern 420j and the insulating layer 190.
  • the first pattern 410j has a width W51 along the first direction.
  • the width W51 and the sub-pixel pitch P may satisfy the following relationship: P ⁇ W51 ⁇ 3 ⁇ P.
  • the second pattern 420j has a width W52 along the first direction.
  • the width W52 and the sub-pixel pitch P may satisfy the following relationship: P ⁇ W52 ⁇ 3 ⁇ P.
  • the spacer 310 is disposed on the top surface M5 of the insulating layer 190.
  • the spacer 310 includes a main spacer 311 and a sub-spacer 312.
  • the width W11 of the main spacer 311 and the sub-pixel pitch P may satisfy the following relationship: P ⁇ W11 ⁇ 3 ⁇ P.
  • the width W12 of the sub-spacer 312 and the sub-pixel pitch P may satisfy the following relationship: P ⁇ W12 ⁇ 3 ⁇ P.
  • the main spacer 311 has a first height H1, the sub-spacer 312 has a second height H2, and the first height H1 is greater than the second height H2.
  • the main spacer 311 is disposed between the first pattern 410j and the insulating layer 190, and the sub-spacer 312 is disposed between the second pattern 420j and the insulating layer 190.
  • the first pattern 410j has a first thickness T1
  • the second pattern 420j has a second thickness T2
  • the first thickness T1 is equal to the second thickness T2.
  • the first pattern 410j abuts against the main spacer 311, and the second pattern 420j does not abut against the sub-spacer 312.
  • the first thickness T1 may be the protruding length or protruding height of the first pattern 410j along the normal direction.
  • the first thickness T1 may be the maximum protruding height of the first pattern 410j relative to the inner surface M4 of the insulating layer 230 along the normal direction.
  • the second thickness T2 may be the protruding length or protruding height of the second pattern 420j along the normal direction.
  • the second thickness T2 may be the maximum protruding height of the second pattern 420j relative to the inner surface M4 of the insulating layer 230 along the normal direction.
  • the present disclosure is not limited thereto.
  • the first height H1 may be equal to the second height H2, and the first thickness T1 may be greater than the second thickness T2, so that the first pattern 410j abuts against the main spacer 311, and the second pattern 420j does not abut against the sub-spacer 312.
  • the spacer may be an island or a portion with a larger thickness or height in a layer.
  • the materials of the spacer may include organic materials (such as photoresist materials) or metal materials.
  • the electronic device when the electronic device is applied as a liquid crystal display device, it can reduce the probability of scratching the alignment film, the alignment film halo and the range of poor alignment, which is beneficial to maintain the opening rate and the applications of high-resolution display devices.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Mathematical Physics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Human Computer Interaction (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)
EP23164218.2A 2022-04-12 2023-03-27 Dispositif électronique Pending EP4261604A3 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US202263329896P 2022-04-12 2022-04-12
CN202310011886.9A CN116909060A (zh) 2022-04-12 2023-01-05 电子装置

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EP4261604A2 true EP4261604A2 (fr) 2023-10-18
EP4261604A3 EP4261604A3 (fr) 2023-11-29

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KR101224582B1 (ko) * 2006-01-16 2013-01-22 삼성디스플레이 주식회사 액정 표시 패널 및 그 제조 방법
JP7091067B2 (ja) * 2017-12-26 2022-06-27 株式会社ジャパンディスプレイ 表示装置
KR20200103231A (ko) * 2019-02-22 2020-09-02 삼성디스플레이 주식회사 표시장치
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