EP4213210A1 - Halbleiterstruktur und herstellungsverfahren dafür - Google Patents

Halbleiterstruktur und herstellungsverfahren dafür Download PDF

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Publication number
EP4213210A1
EP4213210A1 EP22741413.3A EP22741413A EP4213210A1 EP 4213210 A1 EP4213210 A1 EP 4213210A1 EP 22741413 A EP22741413 A EP 22741413A EP 4213210 A1 EP4213210 A1 EP 4213210A1
Authority
EP
European Patent Office
Prior art keywords
circuit region
semiconductor structure
active pillars
trenches
word line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP22741413.3A
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English (en)
French (fr)
Other versions
EP4213210A4 (de
Inventor
Deyuan Xiao
GuangSu SHAO
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Changxin Memory Technologies Inc
Beijing Superstring Academy of Memory Technology
Original Assignee
Changxin Memory Technologies Inc
Beijing Superstring Academy of Memory Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CN202111440983.7A external-priority patent/CN116209241A/zh
Application filed by Changxin Memory Technologies Inc, Beijing Superstring Academy of Memory Technology filed Critical Changxin Memory Technologies Inc
Publication of EP4213210A1 publication Critical patent/EP4213210A1/de
Publication of EP4213210A4 publication Critical patent/EP4213210A4/de
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/39—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor and the transistor being in a same trench
    • H10B12/395—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor and the transistor being in a same trench the transistor being vertical
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H10B12/0383—Making the capacitor or connections thereto the capacitor being in a trench in the substrate wherein the transistor is vertical
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H10B12/0385—Making a connection between the transistor and the capacitor, e.g. buried strap
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H10B12/0387—Making the trench
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures

Definitions

  • the present disclosure relates to, but is not limited to, a semiconductor structure and a manufacturing method thereof.
  • the capacitor is widely used in the memory chip.
  • the integrated circuits develop to be more miniaturized, which requires the integrated circuits to have a higher integration density and a smaller feature size. In other words, it is required to dispose as many components as possible in a smaller-sized integrated circuit region to obtain higher performance.
  • the present disclosure provides a semiconductor structure and a manufacturing method thereof.
  • a first aspect of the present disclosure provides a semiconductor structure, including:
  • the active pillar is in a prismatic, cylindrical, or elliptical cylinder shape.
  • the predetermined angle is 60° to 120°.
  • the semiconductor structure further includes a plurality of capacitor structures, where each of the capacitor structures is correspondingly disposed above one of the active pillars, and projection formed by each of the capacitor structures on the active pillars covers a top surface of one of the active pillar.
  • the semiconductor structure further includes:
  • the semiconductor structure further includes:
  • the semiconductor structure further includes: a peripheral circuit region, where the peripheral circuit region is located outside the core circuit region, a circuit or component in the peripheral circuit region is connected to a circuit or component in the core circuit region, and the peripheral circuit region has a contour extending along the first direction and the second direction.
  • a second aspect of the present disclosure provides a method of manufacturing a semiconductor structure, including:
  • the first trench is deeper than the second trench.
  • the method further includes:
  • the method further includes:
  • the method further includes: forming a plurality of contact layers, where each of the contact layers covers a top surface of one of the active pillars.
  • the method further includes: forming a plurality of capacitor structures at a top of the active pillars, where projection formed by each of the capacitor structures on the substrate covers projection formed by one of the active pillars on the substrate.
  • the active pillar is in a prismatic shape
  • the method further includes: oxidizing the active pillar, such that the active pillar changes from the prismatic shape to a cylindrical or elliptical cylinder shape.
  • the method further includes:
  • the method further includes:
  • 01 array region; 10, substrate; 11, first trench; 100, first structure; 111, first gap; 12, second trench; 20, active pillar; 200, second structure; 211, second gap; 40, bit line; 40a, bit line layer; 41, initial bit line layer; 50, word line; 50a, initial word line layer; 51, gate oxide layer; 60, isolation structure; 61, first isolation layer; 62, second isolation layer; 70, capacitor structure; 71, contact layer; 80, core circuit region; 81, sense amplification circuit region; 810, sense amplifier; 82, word line driving circuit region; 820, word line driver; 90, peripheral circuit region; 910, peripheral circuit; 920, peripheral electrical member; D1, first direction; D2, second direction; D3, third direction; and D4, fourth direction.
  • the semiconductor structure is not limited in this embodiment.
  • the semiconductor structure is described below by taking a dynamic random access memory (DRAM) as an example, but this embodiment is not limited to this, and the semiconductor structure in this embodiment may further be another structure.
  • DRAM dynamic random access memory
  • an exemplary embodiment of the present disclosure provides a semiconductor structure, including: an array region 01, a plurality of bit lines 40 extending along a first direction D1, and a plurality of word lines 50 extending along a second direction D2.
  • the array region 01 is provided with a plurality of active pillars 20.
  • the plurality of bit lines 40 are located at bottoms of the active pillars 20. Any one of the word lines 50 covers sidewalls of a column of the active pillars 20 arranged along the second direction D2.
  • the plurality of word lines 50 correspondingly cover sidewalls of a plurality of columns of the active pillars 20 arranged along the second direction D2 respectively.
  • the first direction D1 and the second direction D2 form a predetermined angle, and the predetermined angle is an acute angle or an obtuse angle.
  • the first direction D1 and the second direction D2 intersect to form an acute angle or an obtuse angle.
  • the plurality of active pillars 20 are arranged in a parallelogram array along a non-orthogonal direction.
  • a plurality of active pillars 20 are arranged in a plurality of rows along the first direction D1.
  • a plurality of active pillars 20 are arranged in a plurality of columns along a second direction D2.
  • the arrangement manner of the active pillars 20 in this embodiment improves the arrangement density of the active pillars 20 per unit area.
  • the angle between the first direction D1 and the second direction D2 may be 30° to 70°, such as 30°, 35°, 45°, 55°, 65° or 70°, or may be 110° to 150° such as 110°, 120°, 130°, 140° or 150°.
  • the predetermined angle is 60° or 120°, a largest quantity of active pillars 20 are arranged in the array region 01, with a largest arrangement density.
  • the active pillar 20 is prismatic, and in FIG. 4 , the active pillar 20 may further be cylindrical or elliptical.
  • the semiconductor structure further includes a plurality of capacitor structures 70, where each of the capacitor structures 70 is correspondingly disposed above one of the active pillars 20, and projection formed by each of the capacitor structures 70 on the active pillars 20 covers a top surface of one of the active pillars 20.
  • any one of the bit lines 40 is connected to a row of the active pillars 20 arranged along a first direction D1.
  • Any one of the word lines 50 covers sidewalls of a column of the active pillars 20 arranged along the second direction D2.
  • the plurality of word lines 50 correspondingly cover sidewalls of a plurality of columns of the active pillars 20 arranged along the second direction D2 respectively.
  • the bit line 40 and the word line 50 are staggered at the active pillar 20.
  • the capacitor structure 70 is correspondingly disposed at an intersection of the bit line 40, the word line 50, and the active pillar 20.
  • the capacitor structures 70 are arranged in a parallelogram array according to the active pillars 20, to improve the space utilization of the semiconductor structure, such that more capacitor structures 70 can be disposed per unit area. In addition, in this embodiment, disposing more capacitor structures 70 further improves the charge storage capacity of the semiconductor structure.
  • the semiconductor structure further includes: a plurality of contact layers 71.
  • Each of the contact layers 71 covers a top surface of one of the active pillars 20.
  • the contact layers 71 are disposed between the active pillars 20 and the capacitor structures 70.
  • the contact layer 20 is configured to fix the capacitor structure 70 to the active pillar 20.
  • the semiconductor structure further includes: an isolation structure 60, where the isolation structure 60 fills gaps between adjacent active pillars 20, between adjacent word lines 50, between adjacent bit lines 40, between the word line 50 and the bit line 40, and between the word line 50 and the capacitor structure 70.
  • an isolation structure 60 isolates a plurality of components in the semiconductor structure, to keep the components in the semiconductor structure independent, avoid a conductive interference between adjacent components, and prevent current leakage from occurring to the semiconductor structure, thereby enduring the electrical property of the semiconductor structure.
  • top surfaces of the word lines 50 are lower than that of the active pillars 20.
  • the isolation structure 60 covers the top surfaces of the word lines 50.
  • the word lines 50 are integrally disposed in the semiconductor structure. Because adjacent word lines 50 are separated by the isolation structure 60, when the semiconductor structure is connected to another semiconductor member, the another semiconductor member is not directly connected to the word lines 50, to avoid that a direct connection between the another semiconductor member and the word lines 50 causes a short circuit of the word lines 50.
  • the semiconductor structure of this embodiment further includes: a core circuit region 80 located on a periphery of the array region 01.
  • the core circuit region 80 is provided with a sense amplification circuit region 81 and a word line driving circuit region 82.
  • a plurality of sense amplifiers 810 arranged along the second direction D2 are disposed in the sense amplification circuit region 81, and the sense amplifier 810 is connected to the bit line 40; and a plurality of word line drivers 820 arranged along the first direction D1 are disposed in the word line driving circuit region 82, and the word line driver 820 is connected to the word line 50.
  • the arrangement directions of the sense amplification circuit region 81 and the word line driving circuit region 82 in the core circuit region 80 are kept consistent with extension directions of the bit line 40 and the word line 50 respectively, to prevent the core circuit region 80 from damaging the active pillar 20 in the array region 01, and ensure the integrity of the semiconductor structure.
  • the semiconductor structure further includes a peripheral circuit region 90.
  • the peripheral circuit region 90 has a contour extending along the first direction D1 and the second direction D2.
  • the peripheral circuit region 90 is located outside the core circuit region 80.
  • a peripheral circuit 910 and a peripheral electrical member 920 in the peripheral circuit region 90 are connected to a circuit and an electrical member in the core circuit region 80.
  • peripheral circuit region and the array region of the semiconductor structure in this embodiment have a same parallelogram outline, which facilitates circuit design and wiring, ensures the structural integrity of each internal member in the semiconductor structure, such that the array region is completely used.
  • the semiconductor structure of this embodiment may be a memory chip, and the memory chip may be used in a DRAM.
  • the memory structure may be further applied to a static random-access memory (SRAM), a flash memory (flash EPROM), a ferroelectric random-access memory (FRAM), a magnetic random-access memory (MRAM), a phase change random-access memory (PRAM), or the like.
  • SRAM static random-access memory
  • flash EPROM flash memory
  • FRAM ferroelectric random-access memory
  • MRAM magnetic random-access memory
  • PRAM phase change random-access memory
  • FIG. 8 is a flowchart of the method of manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure.
  • FIGS. 11 to 14 are schematic diagrams of the method of manufacturing a semiconductor structure at various stages. The method of manufacturing a semiconductor structure is described below with reference to FIGS. 11 to 14 .
  • the semiconductor structure is not limited in this embodiment.
  • the semiconductor structure is described below by using a DRAM as an example, but this embodiment is not limited thereto.
  • the semiconductor structure in this embodiment may further be another structure.
  • an exemplary embodiment of the present disclosure provides a method of manufacturing a semiconductor structure, including: Step S110: Provide a substrate.
  • the substrate 10 may be made of a semiconductor material.
  • the semiconductor material may be one or more selected from the group consisting of silicon, germanium, a silicon germanium compound, and a silicon carbon compound.
  • the semiconductor material may be an intrinsic semiconductor material or a semiconductor dopant material that is lightly doped with ions.
  • Step S120 Perform first etching on the substrate, to form a plurality of first trenches that extend along a first direction and are disposed at intervals in a direction perpendicular to the first direction.
  • the substrate 10 is partially removed through the first etching, that is, the substrate 10 is etched for the first time, to form the plurality of first trenches 11 therein.
  • Each first trench 11 extends along the first direction D1, and the plurality of first trenches 11 are disposed at intervals in a third direction D3 perpendicular to the first direction D1.
  • Step S130 Perform second etching on the substrate, to form a plurality of second trenches that extend along a second direction and are disposed at intervals in a direction perpendicular to the second direction, where the first direction and the second direction form a predetermined angle, and the predetermined angle is an acute angle or an obtuse angle.
  • second etching is performed on the substrate 10, that is, the substrate 10 is etched for a second time.
  • the etching process specifically includes: the substrate 10 is partially removed through the second etching, to form a plurality of second trenches 12.
  • Each second trench 12 extends along a second direction D2.
  • the plurality of second trenches 12 are disposed at intervals along a fourth direction D4 perpendicular to the second direction D2.
  • the plurality of first trenches 11 are disposed in parallel along the first direction D1.
  • the plurality of second trenches 12 are disposed in parallel along the second direction D2.
  • the plurality of first trenches 11 and the plurality of second trenches 11 intersect at a predetermined angle.
  • the remaining structure on the substrate 10 is divided into a plurality of active pillars 20 independent of each other.
  • the plurality of active pillars 20 form a quadrilateral array along the first direction D1 and the second direction D2.
  • the active pillars 20 are prismatic.
  • the angle between the first direction D1 and the second direction D2 may be 30°, 35°, 45°, 55°, 65° or 70°, or may be 110° to 150° such as 110°, 120°, 130°, 140° or 150°.
  • the angle between the first direction D1 and the second direction D2 is 60° or 120°.
  • the first trenches 11 and the second trenches 12 in this embodiment intersect to divide the substrate 10 into more active pillars 20.
  • a plurality of active pillars 20 are in a hexagonal close-packed arrangement, such that a largest quantity of active pillars 20 are formed per unit area, with a largest arrangement density.
  • the first trench 11 is as wide as the second trench 12.
  • a spacing between adjacent active pillars 20 in the first direction D1 and that in the second direction D2 are equal.
  • the active pillar 20 formed in this embodiment is a rhombus pillar with four sides of an equal length, such that the active pillar 20 occupies a smallest space of the semiconductor structure, to further improve the space utilization of the semiconductor structure.
  • the quantity of active pillars disposed on the semiconductor structure in this embodiment is the largest, with a largest arrangement density.
  • the spacing between two adjacent active pillars 20 in the first direction D1 may be greater or smaller than that between two adjacent active pillars 20 in the second direction D2.
  • the first trench 11 is deeper or shallower than the second trench 12.
  • the bit line 40 is formed in a deeper one of the first trench 11 and the second trench 12, and the word line 50 is formed in the other one.
  • the bit line 40 is formed in the first trench 11, and the word line 50 is formed in the second trench 12.
  • a plurality of first trenches and a plurality of second trenches are formed in a non-orthogonal arrangement, to divide the substrate into a plurality of active pillars disposed independently, and make the active pillars arranged denser, improving the space utilization of the semiconductor structure.
  • the method of manufacturing a semiconductor structure in this embodiment further includes: Step S140: Oxidize the active pillar, such that the active pillar changes from the prismatic shape to a cylindrical or elliptical cylinder shape.
  • the active pillar 20 when the active pillar 20 is oxidized, four corners of the prismatic active pillar 20 are partially oxidized at a faster rate, and the middle part between any two corners is oxidized at a slower rate, thereby oxidizing four corners of the active pillar 20 into chamfers (with reference to FIGS. 13 and 14 ). Therefore, the active pillar changes from the prismatic shape to a cylindrical or elliptical cylinder shape.
  • An oxide layer is formed on a sidewall of the sidewall 20 through the oxidation. To prevent the oxide layer from affecting the conductivity of the active pillar 20, after the oxidation, the oxide layer on the sidewall of the active pillar 20 is removed through dry or wet etching, to ensure a favorable electrical performance of the active pillar 20.
  • a thermal oxidation process may be used to oxidize the active pillar 20.
  • the semiconductor structure is placed in a reaction chamber with a temperature of 600°C to 1000°C. Oxygen is introduced into the reaction chamber. The treatment time is 60 to 300 seconds. After the thermal oxidation treatment, the active pillar 20 is cleaned with an acid solution to remove the oxide layer on the surface of the active pillar 20.
  • a plurality of active pillars 20 arranged independently are formed on the substrate 10.
  • the plurality of active pillars 20 are arranged in a parallelogram array along the first direction D1 and the second direction D2. Any two adjacent ones of the plurality of active pillars 20 are separated by the first trench 11 or the second trench 12.
  • the semiconductor structure formed in this embodiment is used as a first structure 100.
  • oxidizing the active pillar can repair the defects formed on the surface of the active pillar during the first etching and the second etching, that is, reduce the defects on the surfaces of the first trench and the second trench, and reduces a stress between the isolation structure formed subsequently and the active pillar, to make the subsequently formed isolation structure have a better isolation effect, thereby preventing current leakage from occurring to the members in the semiconductor structure.
  • FIG. 9 is a flowchart of a method of manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure.
  • FIGS. 12 to 25 are schematic diagrams of the method of manufacturing a semiconductor structure at various stages. The method of manufacturing a semiconductor structure is described below with reference to FIGS. 12 to 25 .
  • the semiconductor structure is not limited in this embodiment.
  • the semiconductor structure is described below by using a DRAM as an example, but this embodiment is not limited thereto.
  • the semiconductor structure in this embodiment may further be another structure.
  • an exemplary embodiment of the present disclosure provides a method of manufacturing a semiconductor structure, including: S210: Provide a first structure.
  • a first structure 100 in this embodiment is formed by in the foregoing embodiment.
  • the first structure 100 includes a plurality of active pillars 20. Any two adjacent ones of the plurality of active pillars 20 are separated by a first trench 11 or a second trench 12.
  • the first trench 11 and the second trench 12 intersect at a predetermined angle, and the predetermined angle is an acute angle or an obtuse angle.
  • the plurality of active pillars 20 are arranged in a parallelogram array.
  • S220 Form a plurality of bit lines in the first trenches, where the bit lines extend along the first direction, and top surfaces of the bit lines are lower than bottom surfaces of the second trenches.
  • the bit lines 40 are formed in the first trenches 11.
  • the bit lines 40 extend along the first direction D1 and are disposed below a row of the active pillars 20 arranged along the first direction D1.
  • forming the bit lines 10 in the first trenches 11 includes the following process: An isolation material is deposited in the first trenches 11 and the second trenches 12. As shown in FIG. 17 , the isolation material in the first trenches 11 is etched back by a predetermined depth. The predetermined depth is greater than a depth of the second trench 12 and smaller than a depth of the first trench 11. As shown in FIG. 18 , with reference to FIG. 12 , a conductive material is deposited to form an initial bit line layer 41 in the first trenches 11, and the top surface of the initial bit line layer is lower than the bottom surfaces of the second trenches 12. As shown in FIG. 19 , the initial bit line layer 41 is removed through etching.
  • a first gap 111 extending along the first direction 11 is formed in each of the first trenches 11.
  • the remaining part of the initial bit line layer 41 is divided by the first gaps 111 into a plurality of bit lines 40.
  • the initial bit line layer 41 located in each of the first trenches 11 is divided by the first gap 111 into bit line layers 40a disposed on both sidewalls of the first trench 11.
  • Each bit line 40 is connected to a row of the active pillars 20 extending along the first direction D1.
  • Each bit line 40 includes two bit line layers 40a disposed at two sides of each row of the active pillars 20.
  • the two bit line layers 40a of each bit line 40 are disposed in two adjacent first trenches 11.
  • S230 Form a first isolation layer, where the first isolation layer covers the bit lines and fills gaps between adjacent bit lines, a part of each of the first trenches, and a part of each of the second trenches.
  • an isolation material is deposited to fill the gap between two adjacent bit lines 40.
  • the isolation material in the first trenches 11 and the second trenches 12 is etched back by a depth that is not bigger than a depth of the second trench 12. The remaining part of the isolation material forms a first isolation layer 61.
  • S240 Form a gate oxide layer, where the gate oxide layer covers exposed sidewalls of the active pillars.
  • an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process may be used for deposition to form the gate oxide layer 51.
  • the gate oxide layer 51 covers the sidewalls of the active pillars 20 exposed by the first trenches 11 and the second trenches 12.
  • the gate oxide layer 51 may be made of a dielectric material such as silicon oxide and/or silicon oxynitride.
  • S250 Form a plurality of word lines, where the word lines extend along an extension direction of the second trenches, and the word lines cover a part of the gate oxide layer and fill a partial structure of the first trench between two adjacent ones of the active pillars.
  • the process of forming the plurality of word lines 50 includes: The ALD process or the CVD process may be used to deposit a word line material.
  • the word line material fills the first trenches 11 and the second trenches 12 to form an initial word line layer 50a.
  • the initial word line layer 50a is etched back until its top surface is lower than the top surfaces of the active pillars 20.
  • the isolation material is deposited to cover the initial word line layer 50a.
  • a mask is provided. As shown in FIG.
  • each word line 50 partially covers sidewalls of a column of the active pillars 20 arranged along the second direction D2.
  • the plurality of word lines 50 correspondingly cover sidewalls of a plurality of columns of the active pillars 20 along the second direction D2 respectively.
  • a material of the word line 50 includes one or more selected from the group consisting of conductive metal, conductive metal nitride, and conductive alloy.
  • the material of the conductive metal may be titanium, tantalum, or tungsten.
  • the initial word line layer 50a is etched back to be lower than the active pillars 20. Then, the isolation material is deposited to cover the top surface of the initial word line layer 50a, to prevent the material forming the word line 50 from being oxidized by air, improving the electrical property of the formed word line 50.
  • S260 Form a second isolation layer, where the second isolation layer fills gaps between adjacent word lines, and unfilled regions of the first trenches and the second trenches.
  • an isolation material is deposited to fill the second gaps 211.
  • the isolation material in the second gaps 211 and the isolation material covering the top surfaces of the word lines 50 form the second isolation layer 62.
  • the first isolation layer 61 and the second isolation layer 62 form an isolation structure 60.
  • S270 Form a plurality of contact layers, where each of the contact layers covers a top surface of one of the active pillars.
  • a plurality of contact layers 71 are correspondingly disposed on the active pillars 20.
  • Each of the contact layers 71 is correspondingly disposed on the top surface of one of the active pillars 20.
  • Each of the contact layers 71 is configured to form a capacitor structure 70 in the subsequent manufacturing process.
  • Step S280 Form a plurality of capacitor structures at a top of the active pillars, where projection formed by each of the capacitor structures on the substrate covers that formed by one of the active pillars on the substrate.
  • a capacitor structure 70 is correspondingly formed on each of the contact layers 71.
  • Each capacitor structure 70 is correspondingly disposed on one active pillar 20.
  • the capacitive structure 70 is connected to the active pillar 20 through the contact layer 71.
  • a silicon germanium compound is deposited to fill a gap between the capacitor structures 70.
  • the plurality of bit lines 40 extending along the first direction D1 the plurality of word lines 50 extending along the second direction D2, the isolation structure 60, the contact layer 71, and the plurality of capacitor structures 70 corresponding to the plurality of active pillars 20 respectively are formed on the first structure 100.
  • the semiconductor structure formed in this embodiment is used as a second structure 200.
  • the capacitor structure and active pillars are formed in a same parallelogram array, to improve the packing density of the capacitor structure per unit area, and improve the storage capacity of the semiconductor structure, which can further meet the integration development of the semiconductor structure, and is especially beneficial to miniaturing the size of a gate-all-around (GAA) semiconductor structure.
  • GAA gate-all-around
  • the semiconductor structure formed in this embodiment has more capacitor structures 70 per unit area, the capacitor structures 70 are in a hexagonal closest-packed arrangement, and the capacitor structures 70 are arranged most densely.
  • FIG. 10 is a flowchart of a method of manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure. The method of manufacturing a semiconductor structure is described below with reference to FIGS. 5 to 7 .
  • the semiconductor structure is not limited in this embodiment. Description is made by using the semiconductor structure as a memory chip, but this embodiment is not limited thereto, and the semiconductor structure in this embodiment may further be another structure.
  • an exemplary embodiment of the present disclosure provides a method of manufacturing a semiconductor structure, including: Step S310: Provide a second structure.
  • the second structure 200 of this embodiment is formed in the foregoing embodiment.
  • the second structure 20 has an outer contour of a parallelogram.
  • Step S320 Form a core circuit region, where the core circuit region includes a sense amplification circuit region and a word line driving circuit region.
  • a sense amplification circuit region 81 extending along the second direction D2 is formed first.
  • a plurality of sense amplifiers 810 arranged along the second direction D2 are formed in the sense amplification circuit region 81.
  • the sense amplifier 810 is connected to the bit line 40.
  • forming the core circuit region 80 further includes: forming a word line driving circuit region 82 extending along the first direction D1, where a plurality of word line drivers 820 arranged along the first direction D1 are disposed in the word line driving circuit region 82, and the word line driver 820 is connected to the word line 50.
  • the core circuit region 80 is arranged according to the arrangement direction of the bit lines 40 and the word lines 50, which can prevent the core circuit region 80 disposed in this manner from damaging the active pillars 20 in the second structure 200.
  • Step S330 Form a peripheral circuit region outside the core circuit region, where the peripheral circuit region has a contour extending along the first direction and the second direction.
  • a peripheral circuit 910 or peripheral member 920 in the peripheral circuit region 90 is electrically connected to a circuit or component in the core circuit region 80.
  • the peripheral circuit region 90 is disposed along the outer contour of the second structure 200.
  • the outer contour of the semiconductor structure formed in this embodiment and the second structure 200 are in a same parallelogram shape.
  • the semiconductor structure formed in this embodiment may be a memory chip, and the memory chip may be used in a DRAM.
  • the memory structure may be further applied to a static random-access memory (SRAM), a flash memory (flash EPROM), a ferroelectric random-access memory (FRAM), a magnetic random-access memory (MRAM), a phase change random-access memory (PRAM), or the like.
  • SRAM static random-access memory
  • flash EPROM flash memory
  • FRAM ferroelectric random-access memory
  • MRAM magnetic random-access memory
  • PRAM phase change random-access memory
  • a peripheral circuit region is formed along a contour edge of the second structure, and the outer contour of the formed semiconductor structure is a parallelogram, which omits the steps of cutting the semiconductor structure into regular squares or rectangles and shorten the production process. Therefore, each active pillar and each capacitor structure in the semiconductor structure are not damaged by the cutting, and the array region is fully used.
  • a plurality of active pillars of the semiconductor structure are arranged in a parallelogram array, improving an arrangement density of the active pillars per unit area and a space utilization of the semiconductor structure.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
EP22741413.3A 2021-11-30 2022-02-24 Halbleiterstruktur und herstellungsverfahren dafür Pending EP4213210A4 (de)

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CN202111440983.7A CN116209241A (zh) 2021-11-30 2021-11-30 半导体结构及其制作方法
PCT/CN2022/077658 WO2023097901A1 (zh) 2021-11-30 2022-02-24 半导体结构及其制作方法

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CN108493188B (zh) * 2018-05-09 2023-10-13 长鑫存储技术有限公司 集成电路存储器及其形成方法、半导体集成电路器件
CN110896074A (zh) * 2018-09-12 2020-03-20 长鑫存储技术有限公司 集成电路存储器及其制造方法
CN113540088B (zh) * 2020-04-16 2024-02-13 长鑫存储技术有限公司 存储器结构及存储器结构的形成方法
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