EP4049372A1 - Convertisseur analogique-numérique sigma-delta avec gmc-vdac - Google Patents

Convertisseur analogique-numérique sigma-delta avec gmc-vdac

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Publication number
EP4049372A1
EP4049372A1 EP20797710.9A EP20797710A EP4049372A1 EP 4049372 A1 EP4049372 A1 EP 4049372A1 EP 20797710 A EP20797710 A EP 20797710A EP 4049372 A1 EP4049372 A1 EP 4049372A1
Authority
EP
European Patent Office
Prior art keywords
switching element
connection
converter
transconductance stage
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP20797710.9A
Other languages
German (de)
English (en)
Inventor
Friedel Gerfers
Marcel RUNGE
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Technische Universitaet Berlin
Original Assignee
Technische Universitaet Berlin
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Technische Universitaet Berlin filed Critical Technische Universitaet Berlin
Publication of EP4049372A1 publication Critical patent/EP4049372A1/fr
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/322—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M3/358—Continuously compensating for, or preventing, undesired influence of physical parameters of non-linear distortion, e.g. instability
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/322—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M3/324—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement
    • H03M3/326—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement by averaging out the errors
    • H03M3/328—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement by averaging out the errors using dither
    • H03M3/33—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement by averaging out the errors using dither the dither being a random signal
    • H03M3/332—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement by averaging out the errors using dither the dither being a random signal in particular a pseudo-random signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H03M3/412—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution
    • H03M3/422—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/17—Function evaluation by approximation methods, e.g. inter- or extrapolation, smoothing, least mean square method
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45183—Long tailed pairs
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45475—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using IC blocks as the active amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/458—Analogue/digital converters using delta-sigma modulation as an intermediate step
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/458—Analogue/digital converters using delta-sigma modulation as an intermediate step
    • H03M3/494—Sampling or signal conditioning arrangements specially adapted for delta-sigma type analogue/digital conversion systems
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45138—Two or more differential amplifiers in IC-block form are combined, e.g. measuring amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H03M3/436—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the order of the loop filter, e.g. error feedback type
    • H03M3/456—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the order of the loop filter, e.g. error feedback type the modulator having a first order loop filter in the feedforward path

Definitions

  • the present invention relates to a sigma-delta analog-to-digital converter.
  • Sigma-delta analog-to-digital converters are known in the art. The principle of sigma-delta modulation is based on a measurement of the input signal. The resulting measurement error is integrated and gradually compensated for via feedback.
  • An exemplary embodiment of a sigma-delta converter is shown in FIG.
  • the sigma-delta converter shown in FIG. 2 essentially has three components.
  • a filter in the simplest case an integrator 20 connected in series with a quantizer 12.
  • the output signal y (n) of the quantizer 12 is fed back by means of a feedback 14 via a digital-to-analog converter 13 (DAC - digital to analog converter) via a summing element fed back to the integrator 20.
  • the output y (n) is a digital signal.
  • the integrator represents an analog block. Therefore, a digital-to-analog converter 13 is used in the feedback to convert the digital signal into an analog signal.
  • Known sigma-delta modulators in particular continuous-time (CT) sigma-delta modulators, use continuous-time integration.
  • continuous-time integrators are implemented as active resistor-capacitor integrators (RC integrators) based on operational amplifiers.
  • FIG. 3 shows a continuous-time integrator in the form of an RC integrator.
  • the continuous-time integrator shown in FIG. 3 has an operational amplifier 24 (OpAmp) which converts the differential voltage at the two inputs into a proportional output current.
  • the capacitance 22 and the resistor 23 are connected as an external circuit. The time constant is determined by this wiring.
  • RC integrators Due to the virtual ground of the operational amplifier, a current flows through the resistor, which is integrated on the capacitance 22 and generates the output voltage u (t). This is provided to a quantizer (not shown) for generating an output signal y (n).
  • RC integrators have a high integrator linearity and thus a high analog-digital converter accuracy. Disadvantage with the RC integrators is the relatively high power dissipation of the operational amplifier. Another disadvantage is the time constant to be set via the RC circuit.
  • Circuits with active gm-C or gm-LC filters represent an alternative and more energy-efficient embodiment of the continuous-time implementation.
  • a simple implementation of a gm-C integrator, as shown in FIG. 4, has a transconductance stage 11 (gm Cell, transconductance amplifier) and a capacitance lld at the output.
  • a gm-LC filter also has a coil (not shown) connected in parallel with the capacitance.
  • the transconductance stage 11 converts the input voltage vin (t) into a current.
  • the transconductance stage 11 is an active block, which ensures a quotient of output current and input voltage that is as constant as possible and thus ensures the voltage-current conversion of the input signal vin (t).
  • the feedback current provided by the current digital / analog converter 21 is subtracted from the input signal vin (t) and the difference is integrated over the capacitance lld.
  • the input signal vin (t) is converted into a current via the transconductance stage 11 and the output current of the current digital-to-analog converter 21 is subtracted from gm * vin (t).
  • the gmC integrator shown in FIG. 4 is designed as an open-loop gmC integrator which is energy-efficient.
  • the disadvantage of this embodiment is that the gm stage sees the entire signal swing vin (t) at the input (cf. FIG. 6), so that there is a high variation in the transconductance over the signal swing vin (t).
  • FIG. 6 shows an exemplary illustration of the modulation for the gm of the gmC integrator of FIG.
  • the gm results from the output current and the input signal Vin (t). It can be seen from FIG. 6 that gm is not linear, but rather becomes smaller and corresponds to the shape of a parabolic curve.
  • a possible alternative for improving the linearity can be achieved by the gm-RC configuration according to FIG.
  • the resistor-DAC combination creates a kind of “virtual GND” node at the front end of the gm-RC configuration, which reduces the signal swing at the input of the gm-RC configuration and thus improves the linearity .
  • a current is generated via the resistor 23 and the resulting difference between the current through the resistor 23 and the fed-back current idac (t) becomes smaller, which means that there is also less signal swing and the gm of the embodiment shown in FIG. 5 becomes more linear.
  • the required resistor 23 is disadvantageous in the embodiment of FIG. 5.
  • the resistor 23 increases the noise power.
  • the input bandwidth is limited via the resistor 23. In this regard, this refinement can no longer be used with high bandwidths.
  • the linearity can be achieved via source degeneration.
  • the source degeneration can comprise a transistor with a resistor. A rising control signal of the transistor results in an increase in the current through the transistor due to the gm. At the same time, however, the voltage drop across the resistor increases, which at the same time reduces the voltage Vgs (gate-source voltage) and thus also the effectiveness of the gm.By means of source degeneration, the linearity can be improved, but has a very high thermal noise (gm Reduction). In addition, this configuration has a poor degree of efficiency and a corresponding negative energy efficiency. Rather, an increased factor of energy must be supplied in order to be able to provide a comparable gm.
  • a first aspect of the present invention comprises a sigma-delta analog-digital converter according to the invention.
  • the sigma-delta analog-digital converter comprises a transconductance stage with a first connection, a second connection, a third connection and a capacitance connected in parallel to the third connection.
  • the sigma-delta analog-digital converter comprises a quantizer at the third connection of the transconductance stage.
  • the output of the quantizer is connected to a feedback by means of a voltage-digital-to-analog converter for feeding back a feedback signal to one of the connections of the transconductance stage.
  • the present invention is based on the knowledge that the use of a voltage-digital-analog converter (VDAC) for a sigma-delta analog-digital converter reduces the effective signal swing without the use of source degeneration and thus simultaneously increases it Signal-to-noise ratio (SNR) and high linearity with minimal power dissipation is achieved.
  • VDAC voltage-digital-analog converter
  • SNR Signal-to-noise ratio
  • the signal swing of the gm stage - and thus the signal-to-noise ratio - and the linearity of the gm stage can be optimized independently of one another without the use of an additional degeneration resistor.
  • VDAC voltage digital to analog converter
  • improved energy efficiency is also achieved.
  • a constant performance can be achieved with the supply of less energy or a performance increase and thus more bandwidth can be achieved with the same energy supply.
  • the form factor is significantly smaller and the noise, which represents more power consumption, is improved.
  • the positioning of the quantizer directly on the third connection has surprisingly also proven to be very advantageous.
  • the effect was particularly surprising since the reduction of a filter order - ie the direct connection of the quantizer to the first gm stage - usually reduces the noise shaping and accordingly worsens the signal-to-noise ratio.
  • This loss was caused by the inventive sigma-delta analog-to-digital converter and the associated therewith compensated for higher sampling rate and the entire converter is designed to be more robust compared to internal nonlinearities of the filter or further disturbances.
  • the first connection is designed as a non-inverting input and the second connection is designed as an inverting input.
  • the non-inverting input is designed to receive an analog input voltage signal.
  • the inverting input is connected to the digital-to-analog converter (DAC).
  • DAC digital-to-analog converter
  • the digital-to-analog converter is designed as a voltage-to-digital-to-analog converter (VDAC).
  • VDAC voltage-to-digital-to-analog converter
  • the voltage digital / analog converter can be used to provide an analog voltage signal from a digital signal, for example a “WORD”.
  • WORD digital signal
  • the sigma-delta analog-digital converter output signal can be fed back via the voltage digital-analog signal.
  • the maximum modulation of the transconductance stage corresponds to the difference between the received input voltage signal and the feedback signal.
  • a low-pass filter is connected in the feedback between the quantizer and the digital-to-analog converter.
  • the transconductance stage is designed as a single-ended transconductance stage with a first switching element and a second switching element.
  • a differential signal swing can be provided via the single-ended transconductance stage.
  • the first switching element and the second switching element are connected to an energy source by means of a connection via a voltage node and by means of a further connection in each case via a summing element to the third connection of the transconductance stage.
  • the first switching element is switched via an input voltage signal and the second switching element is switched to a respective control connection via a feedback signal. Due to the feedback, the feedback signal (Vdac (t)) follows the input voltage signal (Vin (t)).
  • the two differential currents can be subtracted from one another via the summing element and made available to the resulting current at the output node.
  • the transconductance stage is designed as a differential transconductance stage.
  • the differential transconductance stage comprises a first differential pair input combination with a first switching element and a second switching element, which are each connected to one another via a first connection.
  • the differential transconductance stage comprises a second differential pair combination with a third switching element and a fourth switching element, which are each connected to one another via a first connection.
  • the input signal and the feedback signal can advantageously be combined in the gm stage in such a way that a common-mode signal is established at the corresponding source node of the differential pair input combinations.
  • the concept of source denial by means of a resistor is not necessary.
  • the embodiment is thus significantly more energy-efficient and, due to the small modulation of the gm stage, a significant improvement in the linearity of the modulator can be achieved.
  • the first differential pair input combination are each connected to an energy source via a voltage node and the second differential pair input combination via a voltage node.
  • the first and the second differential pair input combination each have a pair of switching elements, in particular a first and a second switching element, as well as a third and a fourth switching element.
  • the other connections of the first switching element and the third switching element have a common node and the other connections of the second switching element and the fourth switching element have a common node.
  • the common nodes are each connected to the third connection of the transconductance stage via a summing element.
  • the first switching element and the fourth switching element are switched via an input voltage signal and the second switching element and the third switching element are switched via a feedback signal to a respective control connection.
  • the first differential pair input combination are each connected to a fifth switching element via a voltage node and the second differential pair input combination via a voltage node.
  • the further connections of the first switching element and the third switching element have a common node and the further connections of the second switching element and the fourth switching element have a common node.
  • the common nodes are each connected to the third connection of the transconductance stage via a summing element.
  • the first switching element and the fourth switching element are switched via an input voltage signal and the second switching element and the third switching element are switched via a feedback signal to a respective control connection.
  • the fifth switching element is a possible implementation of an energy source, for example a current source.
  • the fifth switching element supplies a constant current.
  • a sixth switching element is formed on the side of the first differential pair input combination between the voltage node and the fifth switching element and on the side of the second differential pair input combination between the voltage node and the fifth switching element, or the differential pair input combination has a sixth switching element.
  • the energy source experiences a data-dependent voltage drop as a result of the common-mode signal obtained at the voltage node or the voltage node.
  • the output signal of the energy source actually implemented by the fifth switching element has an undesirable dependency of the current on the voltage across the fifth switching element.
  • the channel length modulation effect occurs here. If the output signal of the energy source is modulated in a data-dependent manner, this in turn can result in non-linearities.
  • the voltage drop across the fifth switching element can advantageously be kept constant, thus preventing any possible modulation of the current.
  • the sixth switching element of the first and second differential pair input combination is switched by an amplifier-amplified output signal of the fifth switching element.
  • the data-dependent voltage drop at the fifth switching element can advantageously be further minimized or eliminated.
  • a gain-boosted cascode, for example, can be used for this.
  • the amplifier controls the sixth switching element so that a constant and therefore data-independent voltage is applied to the fifth switching element.
  • the output signal of the fifth switching element is therefore completely independent of data.
  • the first switching element and the second switching element are switched via the input voltage signal and the third switching element and the fourth switching element are switched via the feedback signal.
  • the input signals are advantageously interconnected by means of the differential stages in such a way that there is no longer a common-mode signal at the respective voltage node. This advantageous embodiment enables a single energy source to be operated at the respective voltage nodes.
  • a second aspect of the present invention includes one
  • Sigma-delta analog-digital converter for processing audio signals in communication systems, in particular in mobile communication systems.
  • FIG. 1 shows a schematic representation of a sigma-delta analog-digital converter according to a first embodiment
  • Fig. 2 is a schematic representation of a prior art sigma-delta analog-to-digital converter
  • FIG. 3 shows a further schematic illustration of a sigma-delta analog-digital converter with an RC integrator known in the prior art
  • 4 shows a further schematic illustration of a sigma-delta analog-digital converter with a gm-C integrator known in the prior art
  • 5 shows a further schematic illustration of a sigma-delta analog-digital converter with a gm-R-C integrator known in the prior art
  • FIG. 6 shows a diagram of the input signal swing of the sigma-delta analog-digital converter shown in FIG. 4 with a gm-C integrator;
  • Fig. 7 is a diagram of the input signal swing of the embodiment shown in Fig. 1;
  • Fig. 8 is a spectrum of the gm-C integrator shown in Fig. 4 and the embodiment shown in Fig. 1;
  • FIG. 9 shows a schematic illustration of a single-ended transconductance stage for an embodiment of the sigma-delta analog-digital converter
  • FIG. 10 shows a schematic illustration of a differential transconductance stage for an embodiment of the sigma-delta analog-digital converter
  • FIG. 11 shows a schematic illustration of a further differential transconductance stage for an embodiment of the sigma-delta analog-digital converter
  • 12 shows a schematic illustration of a further differential transconductance stage for an embodiment of the sigma-delta analog-digital converter
  • 13 shows a schematic illustration of a further differential transconductance stage for an embodiment of the sigma-delta analog-digital converter
  • FIG. 14 shows a schematic illustration of a further differential transconductance stage of an embodiment of the sigma-delta analog-digital converter.
  • the sigma-delta analog-digital converter 10 has a transconductance stage 11 (gm stage).
  • the transconductance stage 11 has a first input 11a and a second input 11b, as well as an output 11c.
  • An input signal vin (t) is applied to input 11a.
  • the DAC can be designed as an R-2-R-DAC, as an M-2-M-DAC or C-2-C-DAC.
  • the feedback signal Vdac (t) is provided as a feedback signal via the VDAC 13.
  • the VDAC 13 is designed to generate and provide a voltage from a digital signal, for example a digital “WORD”.
  • the sigma-delta analog-digital converter 10 also has a quantizer 12.
  • the quantizer 12 is connected in series with the transconductance stage 11.
  • the output signal y (n) of the quantizer 12 is switched to the input of the VDAC 13 via a feedback circuit 14.
  • the sigma-delta analog-digital converter 10 has a capacitance lld.
  • the capacitance lld is connected in parallel to the output of the transconductance stage 11.
  • An output voltage u (t) is provided to the quantizer 12.
  • the sigma-delta analog-digital converter 10 can have a low-pass filter 15 at the input of the VDAC 13.
  • the quantization noise can be minimized via the low-pass filter 15.
  • a feedback signal Vdac (t), in particular a voltage, is provided via the VDAC 13.
  • the VDAC 13 converts a digital signal y (n) into a voltage Vdac (t).
  • the VDAC 13 compares the voltages vin (t) and the output signal y (n).
  • the feedback signal Vdac (t) comes very close to the input signal Vin (t), so that only a voltage difference remains which corresponds to the quantization error.
  • the voltage difference between the input signal Vin (t) and the feedback signal Vdac (t) is therefore very small.
  • the feedback signal Vdac (t) thus corresponds to the input signal Vin (t) at the input 11a of the transconductance stage 11 plus the quantization noise and results in
  • the quantization noise can be further minimized using a low-pass filter.
  • the modulation or the signal swing which is applied to the transconductance stage 11 can thus advantageously be minimized.
  • Fig. 7 the reduced modulation is shown.
  • the effective input signal vq (t) of the transconductance stage 11 according to the present invention is significantly flatter than, for example, the input signal of the embodiment known from the prior art according to FIG. 4.
  • a complete signal swing results as the input signal for the transconductance stage 11 in FIG. 6.
  • the input signal Vin (t) and the feedback signal vdac (t) are combined at the transconductance stage 11 in such a way that a common-mode signal is established at the output.
  • the maximum modulation of the transconductance stage 11 corresponds to vd (t) or -vq (t). There is a significant improvement in linearity. It can be seen from FIG. 7 that the signal swing is limited to vq (t) with the same input signal vin (t).
  • FIG. 8 shows a spectrum of the gm-C integrator shown in FIG. 4 and the embodiment of the present invention shown in FIG.
  • the spectrum shown shows this Simulation result with a gmC integrator known in the prior art according to the embodiment shown in FIG.
  • Reference number 40 denotes the spectrum of said gmc integrator.
  • Reference numeral 30 denotes the spectrum generated with the present invention of a gmVC integrator. Both gm stages were provided with the same components and are constructed identically. The only difference between the gm stages is the corresponding wiring.
  • a VDAC is provided in the gmVC integrator, which switches the voltage signal vdac (t) to the inverting input of the transconductance stage 11.
  • the spectrum 30 of the sigma-delta analog-digital converter with a gmVC integrator has a spectrum without distortion at multiples of the input frequency (le6 Hz).
  • the spectrum 40 of the gmc integrator known in the prior art has harmonic distortions in the frequency profile at multiples of the input frequency (le6 Hz). The greatest harmonic distortion is -45dB.
  • a gm stage consists of a switch, for example a bi-polar transistor or a field effect transistor. Further semiconductor switching elements can be used to switch the transconductance stage.
  • a voltage-current conversion is carried out by the switching elements TI and T2.
  • the switching elements TI and T2 each have a connection to a common voltage node 1 via a first connection.
  • An energy source E preferably a current source, is connected across the voltage node 1.
  • the gm with the current of the energy source E is provided by the switching elements TI and T2. The current results from
  • the switching elements TI and T2 each have a further connection for connection to a summing element S.
  • the switching element TI is controlled via the input signal Vin (Vin (t)).
  • the switching element T2 is controlled via the input signal Vdac (Vdac (t)).
  • the input swing reduces the quantization noise in such a way that the linearity of the gm stage is significantly improved.
  • the signal swing falls, as shown in FIG. 9, via the energy source E.
  • the respective differential currents of the first switching element TI and the second switching element T2 are subtracted from one another and the resulting current is made available at the third connection 11c of the transconductance stage 11 (see FIG. 1).
  • the current at the third connection 11c is integrated and converted into the voltage u (t) at the third connection 11c.
  • the feedback signal is applied to the connection 11b (see FIG. 1) instead of to the output 11c.
  • VDAC voltage-mode DAC
  • FIG. 10 shows a schematic illustration of a differential transconductance stage 11 for an embodiment of a sigma-delta analog-digital converter.
  • the transconductance stage 11 comprises a first differential pair input combination and a second differential pair input combination.
  • the first differential pair input combination comprises a first switching element TI and a second switching element T2.
  • the first switching element TI and the second switching element T2 have a common voltage node 1 at a respective connection.
  • An energy source E preferably a current source, is connected to the voltage node 1.
  • the switching element TI is via a node with the Summing member S connected.
  • the switching element T2 is connected to the summing element S via a further node.
  • the second differential pair input combination comprises a third switching element T3 and a fourth switching element T4.
  • the third switching element T3 and the fourth switching element T4 have a common voltage node 2 at a respective connection.
  • a further energy source E preferably a current source, is connected to the common voltage node 2.
  • the voltage node 1 and the voltage node 2 can be switched via a common energy source E.
  • the switching element T3 is connected to the switching element TI and the summing element S via a node.
  • the switching element T4 is connected to the switching element T2 and the summing element S via the further node.
  • the two differential currents of the first switching element TI and the third switching element T3, as well as the second switching element T2 and the fourth switching element T4 are subtracted from one another via the summing element S and made available to the resulting current at the connection 11c of the transconductance stage 11.
  • This current made available is integrated by means of the capacitance lld and converted into the voltage u (t) at the connection 11c.
  • the input signal vin (t) and the feedback signal vdac (t) are combined in the transconductance stage 11 in such a way that a common-mode signal is established at the node of the differential pair input combination.
  • the resistance R required in the prior art for the source degeneration can advantageously be disregarded.
  • the embodiment of FIG. 10 is more energy-efficient and, due to the smaller modulation of the transconductance stage 11, a significant improvement in the linearity of the modulator can be achieved.
  • the output signals Voutp and Voutn shown in FIG. 10 correspond to the differential connections of the transconductance stage 11 and thus a differential consideration of the third connection 11c shown in FIG. 1.
  • the output signal at the third connection 11c (Voutp-Voutn).
  • the quantizer 12 can accordingly be constructed differentially.
  • the input signal Vin (t) and the feedback signal vdac (t) are designed accordingly differentially.
  • 11 shows a schematic illustration of a further differential transconductance stage 11 for an embodiment of a sigma-delta analog-digital converter.
  • the configuration in FIG. 11 comprises the same elements in the same interconnection as the configuration in FIG. 10.
  • a further switching element T5 is provided in each differential pair input combination.
  • the switching element T5 is connected to the respective voltage nodes 1 and 2 via a connection.
  • the switching element T5 can be designed, for example, as a bipolar transistor or as a field effect transistor.
  • the switching element T5 can be a possible implementation of a current source. In this embodiment, the current through the switching element T5 corresponds to the output signal.
  • FIG. 12 shows a schematic illustration of a further differential transconductance stage 11 for an embodiment of a sigma-delta analog-digital converter.
  • the transconductance stage 11 has a first differential pair input combination and a second differential pair input combination with a first switching element TI and second switching element T2, as well as a third switching element T3 and a fourth switching element T4 according to FIG. 11.
  • the transconductance stage 11 has a series connection of the fifth switching element T5 and a sixth switching element T6.
  • the fifth switching element T5 and the sixth switching element T6 can be designed as bi-polar transistors or field effect transistors. This configuration advantageously makes the ideal current source more efficient through the fifth switching element T5 and the sixth switching element T6. In particular, this configuration improves the interest rate.
  • the switching element T5 has a resistance R DS (drain-source resistance). An improved interest rate and thus an increased interest rate results from the R DS of switching element T5 and the voltage gain A Vi of switching element T6
  • Zin RDS * AVI.
  • the output resistance is improved.
  • Fig. 13 shows a schematic representation of a further differential transconductance stage 11 for an embodiment of a sigma-delta analog-to-digital converter.
  • the transconductance stage has an amplifier V at the control input of the sixth switching element T6.
  • a further voltage gain A V 2 can be provided via the amplifier V, so that the improved Zin increases
  • the feedback signal Vdac (t) follows the input to the digital-to-analog converter (DAC) 13, thus causing voltage nodes 1 and 2 in Figure 13 to move in proportion to the common mode voltage of each differential pair input configuration.
  • a constant gate-source voltage VGS of the input transistors can thus be ensured. This minimizes the transconductance gm modulation over the input voltage.
  • the influence of the current modulation can be reduced via the cascaded current source used in FIG. 13.
  • the data-dependent voltage drop across the switching element T5 can be further minimized or eliminated by the cascaded current source (gain-boosted cascode).
  • the amplifier V regulates the switching element T6 so that a constant and thus data-independent voltage is applied to the switching element T5.
  • the output signal of the switching element T5 is therefore completely independent of the data.
  • FIG. 14 shows a schematic illustration of a further differential transconductance stage of an embodiment of a sigma-delta analog-digital converter.
  • 14 shows a differential form of implementation with alternative signal control.
  • the transconductance stage in FIG. 14 is designed with the same components as the transconductance stage according to FIG. 13.
  • the first switching element TI is switched via the input signal Vinp (positive component) and the second switching element T2 via the input signal Vinn (negative component) Share).
  • the third switching element T3 is controlled via the feedback signal Vdacn and the fourth switching element T4 is controlled via the feedback signal Vdacp. It results for:
  • T1 / T2 combination gm * [(Vinp-Vdinn) T3 / T4 combination gm * [(Vdacp-Vdacn)

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Abstract

La présente invention concerne un convertisseur analogique-numérique sigma-delta. Le convertisseur analogique-numérique sigma-delta comporte un étage à transductance ayant un premier, un deuxième et un troisième raccordement. Un condensateur est monté en parallèle au niveau du troisième raccordement. Le convertisseur analogique-numérique sigma-delta comporte en outre un quantificateur au niveau du troisième raccordement de l'étage à transductance avec une rétroaction au moyen d'un convertisseur numérique-analogique de tension pour la rétroaction d'un signal de rétroaction vers l'un des raccordements de l'étage à transducteur.
EP20797710.9A 2019-10-25 2020-10-23 Convertisseur analogique-numérique sigma-delta avec gmc-vdac Pending EP4049372A1 (fr)

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DE102019128876.2A DE102019128876A1 (de) 2019-10-25 2019-10-25 Sigma-Delta-Analog-Digital-Wandler mit gmC-VDAC
PCT/EP2020/079938 WO2021078960A1 (fr) 2019-10-25 2020-10-23 Convertisseur analogique-numérique sigma-delta avec gmc-vdac

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EP (1) EP4049372A1 (fr)
JP (1) JP2022553548A (fr)
KR (1) KR20220087462A (fr)
CN (1) CN114600375A (fr)
DE (1) DE102019128876A1 (fr)
WO (1) WO2021078960A1 (fr)

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GB2393055B (en) * 2002-09-10 2006-08-30 Wolfson Ltd Transconductance amplifiers
US8760330B2 (en) * 2012-01-31 2014-06-24 Intel Mobile Communications GmbH Analog-to-digital converter, signal processor, and method for analog-to-digital conversion
US9335429B2 (en) * 2012-09-25 2016-05-10 Cirrus Logic, Inc. Low power analog-to-digital converter for sensing geophone signals
EP2887553B1 (fr) * 2013-12-18 2018-07-18 Nxp B.V. Étape d'entrée de convertisseur analogique/numérique assurant une correspondance à haute linéarité et gain entre plusieurs canaux d'adaptation

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JP2022553548A (ja) 2022-12-23
KR20220087462A (ko) 2022-06-24
DE102019128876A1 (de) 2021-04-29
CN114600375A (zh) 2022-06-07
WO2021078960A1 (fr) 2021-04-29

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