EP3991299A1 - Appareils et procédés pour réaliser une conversion de données - Google Patents

Appareils et procédés pour réaliser une conversion de données

Info

Publication number
EP3991299A1
EP3991299A1 EP19739590.8A EP19739590A EP3991299A1 EP 3991299 A1 EP3991299 A1 EP 3991299A1 EP 19739590 A EP19739590 A EP 19739590A EP 3991299 A1 EP3991299 A1 EP 3991299A1
Authority
EP
European Patent Office
Prior art keywords
data conversion
time
conversion according
cyclic
ring oscillator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP19739590.8A
Other languages
German (de)
English (en)
Inventor
Okko JARVINEN
Siddiqui WAQAS
Marko Kosunen
Kari Stadius
Jussi Ryynanen
Vishnu UNNIKRISHNAN
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Huawei Technologies Co Ltd
Original Assignee
Huawei Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Technologies Co Ltd filed Critical Huawei Technologies Co Ltd
Publication of EP3991299A1 publication Critical patent/EP3991299A1/fr
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/50—Analogue/digital converters with intermediate conversion to time interval
    • H03M1/502—Analogue/digital converters with intermediate conversion to time interval using tapped delay lines

Definitions

  • TECHNICAL FIELD Generally, the following description relates to the field of electronic devices. More specifically, the following description relates to apparatuses and methods for performing a data conversion using an arrangement for providing a time resolution for an electronic device. BACKGROUND
  • High resolution timing is an important aspect in many modern integrated circuit applications.
  • One example of an application with a need for high resolution timing is modern data communication networks. These networks involve use of high-speed and high-resolution analog-to-digital converters and time-to-digital converters.
  • An example of such modern data communication network is so called 5G, wherein high bandwidth and latency requirements cause a need for high resolution timing.
  • the design of analog-to-digital converters using time-domain circuit techniques involves converting the analog input signal into a time domain signal using a voltage- to-time converter. The resulting dime-domain signal is then sampled and quantized into a digital signal using a time-to-digital converter. The resolution of a time-domain analog-to-digital converter is determined by the gain of the voltage-to-time conversion together with the resolution of the time-to-digital conversion.
  • Apparatuses and methods for performing a data conversion using a high time resolution for an electronic device are disclosed.
  • High time resolution is important in many modern applications.
  • Improved data communication networks have high data bandwidths and low latencies together with high time resolution. This can be achieved by using a cyclic coupled ring oscillator for providing the time resolution.
  • Using a cyclic coupled ring oscillator for providing the time resolution gives a possibility to use sub-gate delay resolution.
  • the apparatus comprises a cyclic coupled ring oscillator, wherein the cyclic coupled ring oscillator comprises a number M of ring oscillators having N stages, wherein each of ring oscillators having N stages are coupled in a cyclic manner, wherein the apparatus is configured to perform data conversion with a time resolution defined by the cyclic coupled ring oscillator; and an output configured to output the converted data.
  • the apparatus further comprises an input configured to receive an analog signal and the output is configured to use a continuous-time integrated and quantized version of the analog input as the generated time resolution. It is beneficial to implement an apparatus so that it can receive an analog input as the input signal and convert it into continuous-time integrated and quantized version. This provides a high accuracy conversion.
  • the apparatus further comprises a digital signal processor having a first input connected to the output, and the digital signal processor further comprises a second input configured to receive a pulse signal. It is beneficial to connect the cyclic coupled ring oscillator to a digital signal processor for performing high accuracy conversions using a digital signal processor.
  • the predefined time resolution is a sub-gate delay time resolution.
  • the sub-gate delay time provides particularly improved accuracy in the data conversion.
  • the apparatus further comprises delay stage inverters in ring oscillators and coupling inverters having a weaker drive strength than delay stage inventers in the ring oscillators and wherein the coupling inverters are configured to couple ring oscillators in a cyclic manner.
  • weak drive strength provides enhanced capability to achieve a desired mode of oscillation for the cyclic coupled ring oscillator.
  • the coupled N-stage oscillators oscillate in a desired mode of oscillation, wherein each possible mode corresponds to a certain distinct phase relationship between the N-stage horizontal oscillators.
  • the overall arrangement is capable of better producing the desired high precision time resolution.
  • the apparatus is configured to receive a time domain signal as an input. It is beneficial to be able to receive a time domain signal as an input. This improves flexibility of the arrangement.
  • the apparatus further comprises a voltage-to- time converter and the voltage-to-time converter is configured to receive an analog input and to provide a time domain output. It is beneficial to be able to receive an analog signal as an input. This improves flexibility of the arrangement.
  • the apparatus is a time-to-digital converter. It is beneficial implement a time-to-digital converter that can be used in various applications.
  • the apparatus is an analog-to-digital converter. It is beneficial implement a analog-to-digital converter that can be used in various applications.
  • the apparatus is a radio receiver. It is beneficial to use a cyclic coupled ring oscillator based data conversion apparatus in the implementation as it increases the accuracy and performance of the implementation.
  • the apparatus is an all-digital phase-locked loop. It is beneficial to use a cyclic coupled ring oscillator based data conversion apparatus in the implementation as it increases the accuracy and performance of the implementation.
  • the apparatus is a time-of-flight sensor. It is beneficial to use a cyclic coupled ring oscillator based data conversion apparatus in the implementation as it increases the accuracy and performance of the implementation.
  • the apparatus is a three-dimensional imager. It is beneficial to use a cyclic coupled ring oscillator based data conversion apparatus in the implementation as it increases the accuracy and performance of the implementation.
  • the apparatus is a radar. It is beneficial to use a cyclic coupled ring oscillator based data conversion apparatus in the implementation as it increases the accuracy and performance of the implementation.
  • a method for performing data conversion comprises performing a data conversion using a sub-gate-delay time resolution provided by a cyclic coupled ring oscillator , wherein the cyclic coupled ring oscillator comprises a number M of ring oscillators having N stages, wherein each of ring oscillators having N stages are coupled toin a cyclic manner.
  • the method is performed using a ring oscillator comprising delay stage inverters and coupling inverters, wherein the coupling inverters have a weaker drive strength than delay stage inventers.
  • weak drive strength provides enhanced capability to achieve a desired mode of oscillation for the cyclic coupled ring oscillator.
  • the method further comprises: selecting a mode of oscillation for each of the ring oscillators.
  • selecting a mode of oscillation for each of the ring oscillators When coupled N-stage oscillators each oscillate in desired mode of oscillation the overall arrangement is capable of better producing the desired high precision time resolution.
  • the method further comprises: receiving a time domain signal as an input. It is beneficial to be able to receive a time domain signal as an input. This improves flexibility of the method.
  • the method further comprises: receiving an analog signal as an input and converting the received analog signal into time domain signal. It is beneficial to be able to receive an analog domain signal as an input. This improves flexibility of the method.
  • FIG. 1 a shows an example of a schematic diagram illustrating an analog to digital converter
  • Fig. 1 b shows an example of an apparatus with a CCRO to realize a high-precision signal processing system that can process both analog and asynchronous-digital signals;
  • Fig. 1 c shows an example of an apparatus with a CCRO in an analog signal processing unit that can be implemented with digital hardware
  • Fig. 2 shows an example of a regular ring oscillator
  • Fig. 3 shows an example of a cyclic coupled ring oscillator
  • Fig. 4 shows an example of a time to digital converter using a cyclic coupled ring oscillator
  • Fig. 5 shows an example of a receiver front-end for the fifth generation telecommunication network
  • Fig. 6 shows an example of a high-performance frequency synthesis and all-digital phase-locked loop
  • a disclosure in connection with a described method may also hold true for a corresponding device or system configured to perform the method and vice versa.
  • a corresponding device may include a unit to perform the described method step, even if such unit is not explicitly described or illustrated in the figures.
  • the features of the various exemplary aspects described herein may be combined with each other, unless specifically noted otherwise.
  • FIG 1 a a basic implementation of an analog-to-digital converter is shown.
  • the example analog-to-digital converter may be used as a basis for an embodiment for the described arrangements for providing a time resolution.
  • the analog-to-digital converter of figure 1 receives an analog input 100 at a voltage-to-time converter 101.
  • the received analog input, usually voltage-represented signal, 100 is then converted into a time-domain signal 102 using a voltage-to-time converter (VTC) 101.
  • VTC voltage-to-time converter
  • the resulting time-domain signal 102 is then sampled and quantized into a digital signal using a time-to-digital converter (TDC) 103 for providing a digital output 104.
  • TDC time-to-digital converter
  • the resolution of a time-domain ADC is determined by the gain of the voltage- to-time conversion together with the resolution of the time-to-digital conversion. The arrangement described below in detail helps improving the resolution of the time-to- digital conversion thereby also improving the resolution of the analog-to-digital conversion.
  • Figure 1 b shows an example of an apparatus with a CCRO 105 to realize a high- precision signal processing system that can process both analog and asynchronous-digital signals.
  • the pulse signal input 106 can contain time-encoded analog information or an asynchronous-digital information that requires processing.
  • the digital signal processing unit 107 can realize a variety of signal processing tasks by comparing/combining the information in the pulse signals 106 with the high- precision instantaneous phase signal provided by the CCRO 105, thereby realizing a phase-domain signal processing system.
  • the processed signals are then provided as an output signal 108.
  • Figure 1 c shows an example of an apparatus with a CCRO in an analog signal processing unit that can be implemented with digital hardware.
  • the example of figure 1 c provides opportunities in high-performance energy-efficient analog signal processing in highly-scaled semiconductor technologies (which is otherwise difficult) and design-cost saving using design automation.
  • a CCRO 1 10 is used as a time-domain integrator for analog signals 109 when the CCRO 1 10 is used as a voltage controller oscillator.
  • the analog input 109 controls the frequency of the CCRO 1 10.
  • the phase output of the CCRO then provides a continous-time integrated and quantized version of the analog input 1 1 1.
  • This is a versatile signal processing unit that can find use in realizing a variety of complex signal processing tasks.
  • Figure 2 shows an example of a regular ring oscillator 200.
  • a regular ring oscillator divides its phase into 2N steps where N is the number of inverters in the ring. Hence, the time resolution that is created is still in steps of inverter delays.
  • the regular ring oscillator 200 is a regular ring oscillator with 5 inverters and the resulting phase interpolation are shown in the figure below the ring oscillator 200.
  • the minimum inverter delay for the specific load conditions is assumed to be t mv-mm . Note that the minimum time step possible in the circuit, f m/n , is the same as t mv-min .
  • Cyclic coupled ring oscillator refers to an arrangement where a number of ring oscillators ( M) are coupled in a cyclic fashion, forming a ring of rings.
  • M ring oscillators
  • the individual ring oscillators establish a phase relationship among themselves such that 2xA/x/W phase steps uniformly distributed between 0 and 2p can be extracted from the structure.
  • the resulting time step between temporally adjacent phase steps is approximately 1/M of the inverter delay.
  • a sub-gate- delay resolution is achieved.
  • FIG 3 an example of a cyclic coupled ring oscillator is shown.
  • the cyclic coupled ring oscillator comprises three regular 5-stage ring oscillators 300 - 302.
  • the newly introduced coupling inverters 305 are marked with c.
  • the coupling inverters are arranged into a ring 304 for coupling the regular ring oscillators 300 - 302 in a cyclic manner.
  • the coupling inverters 305 are usually designed to have relatively weak drive strength compared to regular inverters 303.
  • the 5-stage oscillators 300 - 302 are cyclically coupled with coupling inverters which in turn forms a set of vertical ring oscillators.
  • the coupled oscillators oscillate in the desired mode of oscillation, wherein each possible mode corresponds to a certain distinct phase relationship between the 5-stage horizontal oscillators, the desired phase interpolation as shown in Fig. 3 below the cyclic coupled ring oscillator is achieved.
  • Fig. 3 There are usually several different modes that provide the desired phase interpolation and hence it is easy to design the structure to ensure a desired mode of oscillation. It can be seen from Fig. 3 that the minimal time step present in the circuit, t mm is now tinv-min/M, which less than the minimum inverter delay Thus, the desired sub-gate-delay resolution is achieved.
  • FIG. 4 shows an example of a TDC using a cyclic coupled ring oscillator 400.
  • a cyclic coupled ring oscillator 400 achieves an arbitrarily small sub-gate-delay phase quantization step.
  • TDC or ADC cyclic coupled ring oscillator based data converter
  • the phase quantization step approaches a picosecond or even shorter.
  • the phase output of the cyclic coupled ring oscillator needs to be sampled by registers 402 and 403.
  • the sampled phase of the oscillator is then encoded into a number inside the digital signal processor block 404 in order to generate a digital output sample.
  • figure 4 additionally shows a counter 401 that can be used for counting values of received from the cyclic coupled ring oscillator.
  • a counter 401 that can be used for counting values of received from the cyclic coupled ring oscillator.
  • This is just an example of an additional component that can be included in a data converter. Instead of a counter it is possible to use also other additional components in the arrangement.
  • a method for performing a data conversion may be used.
  • the data conversion is using a sub-gate- delay time resolution provided by a cyclic coupled ring oscillator, wherein the cyclic coupled ring oscillator comprises a number M of ring oscillators having N stages, wherein each of ring oscillators having N stages are coupled in a cyclic manner.
  • the method may be used in any of the above examples or similar examples for the purpose of data conversion.
  • FIG 5 a receiver front-end for fifth generation telecommunication network is shown.
  • the receiver front-end uses an RF-digitizing approach, using a high performance ADC.
  • the receiver front end comprises a receiving section 500 for receiving analog signals.
  • the required converter with a very high bandwidth as well as a high resolution is realized with a time-interleaved architecture where individual converters 501 - 503 are implemented with the time-domain approach to take advantage of the superior time resolution of the advanced processes.
  • the front-end further comprises a digital signal processor 504 for processing the received and converted signal.
  • FIG 6 an example of a high-performance frequency synthesis and all-digital phase-locked loop (ADPLL) is shown as a use case example.
  • All-digital phase- locked loops are gaining popularity as an attractive architecture to implement frequency synthesizers and similar applications in highly-scaled semiconductor technologies.
  • the resolution and conversion speed of the TDC block 601 in an ADPLL is crucial in determining the performance and bandwidth of the circuit. It receives an input 600 and provides it further to a digital loop filter 602 and to a digitally controlled oscillator 604, which provides an output 606.
  • the digitally controlled oscillator of the example is further connected back to the TDC block 601 through a divider 605.
  • the arrangement can be useful in mitigating the performance limitations of ADPLLs and frequency synthesizers designed in modern semiconductor technologies by enabling fast and high-resolution time-to-digital conversion.
  • Phase-locked loops and frequency synthesizers are used extensively in radio transceivers and high-speed serial communication transceivers.
  • Time-of-flight sensors are used in a wide range of radar applications including automotive radar and other consumer electronic radar applications.
  • the arrangements using a cyclic coupled ring oscillator for generating a time resolution as described above may be implemented in hardware, such as a mobile telephone, tablet computer, computer, telecommunication network base station or any other network connected device, or as a method.
  • the method may be implemented as a computer program.
  • the computer program is then executed in a computing device.
  • the apparatus such as apparatus for transmitting signals in a communication network, is configured to perform one of the methods described above.
  • the apparatus comprises necessary hardware components. These may include at least one processor, at least one memory, at least one network connection, a bus and similar. Instead of dedicated hardware components it is possible to share, for example, memories or processors with other components or access at a cloud service, centralized computing unit or other resource that can be used over a network connection.
  • a computer program may be stored/distributed on a suitable medium, such as an optical storage medium or a solid-state medium supplied together with or as part of other hardware, but may also be distributed in other forms, such as via the Internet or other wired or wireless telecommunication systems.
  • a suitable medium such as an optical storage medium or a solid-state medium supplied together with or as part of other hardware, but may also be distributed in other forms, such as via the Internet or other wired or wireless telecommunication systems.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

L'invention concerne des appareils et des procédés permettant d'effectuer une conversion de données à l'aide d'une résolution temporelle élevée pour un dispositif électronique. Dans de nombreuses applications modernes, il est important de disposer d'une résolution temporelle élevée. Les réseaux de communication de données améliorés présentent des largeurs de bande de données élevées et de faibles latences qui nécessitent une résolution temporelle élevée. Pour ce faire, on utilise un oscillateur en anneau couplé cyclique pour fournir la résolution temporelle. L'utilisation d'un oscillateur en anneau couplé cyclique pour fournir la résolution temporelle permet d'utiliser une résolution de retard de sous-porte.
EP19739590.8A 2019-07-11 2019-07-11 Appareils et procédés pour réaliser une conversion de données Pending EP3991299A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/EP2019/068703 WO2021004635A1 (fr) 2019-07-11 2019-07-11 Appareils et procédés pour réaliser une conversion de données

Publications (1)

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EP3991299A1 true EP3991299A1 (fr) 2022-05-04

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Family Cites Families (2)

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Publication number Priority date Publication date Assignee Title
JP5632712B2 (ja) * 2010-11-05 2014-11-26 ルネサスエレクトロニクス株式会社 クロック発振回路及び半導体装置
WO2016081046A2 (fr) * 2014-09-03 2016-05-26 University Of Southern California Convertisseur analogique-numérique basé sur un vco de nyquist à large bande

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