Classifications

• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
  • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
  • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
  • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2300/00—Aspects of the constitution of display devices
  • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
  • G09G2300/0809—Several active elements per pixel in active matrix panels
  • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2300/00—Aspects of the constitution of display devices
  • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
  • G09G2300/0809—Several active elements per pixel in active matrix panels
  • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
  • G09G2300/0857—Static memory circuit, e.g. flip-flop
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2340/00—Aspects of display data processing
  • G09G2340/12—Overlay of images, i.e. displayed pixel being the result of switching between the corresponding input pixels
  • G09G2340/125—Overlay of images, i.e. displayed pixel being the result of switching between the corresponding input pixels wherein one of the images is motion video

Definitions

• the invention relates to the field of electronics, and more specifically to that of matrix display devices. It relates to a matrix display type LED, OLED or any other type.
• This matrix display allows the dynamic or static display of images, or an overlay of these two types of display; to allow this dual display it includes a new architecture of each sub-pixel.
• Matrix display systems which implement on each sub-pixel a different architecture depending on the type of static or dynamic display desired on the interface.
• the device includes a data processing unit for adapting the signals for display on the display matrix. This post treatment of data allows for an overlay, but it is based on a dynamic display; therefore the energy consumption of the device remains important. Another device for superimposing images is described in US 2002/0093472.
• an object of the present invention is to remedy, at least partially, the disadvantages of the prior art mentioned above by proposing a very low consumption display as for the static mode but which also allows the dynamic display (video mode) of very good quality.
• This display should also allow a simple way to superimpose graphic images (in "overlay” mode) on images in video mode.
• the problem is solved by using a matrix of elementary electroluminescent emitting zones which has two addressing modes: a first mode (called “video mode”) using a video type interface, preferably standardized, which allows display video images of good quality (with typically eight to ten bits of gray levels and a good refresh rate (also called refresh rate), typically between 30 Hz and 120 Hz, preferably between 60 Hz and 120 Hz) , but which does not need to keep the image in permanent memory, and a second mode (called "graphic mode”) using a data type interface, preferably standardized (for example of type SPI) which keeps in memory the image, knowing that this graphic mode requires only a small number of gray levels (for example one or two bits per sub-pixel), and that the stored image can either be displayed alone or superimposed on a video image entered in the display by the video interface.
• video mode a first mode
• video type interface preferably standardized, which allows display video images of good quality (with typically eight to ten bits of gray levels and a good refresh rate (also called refresh rate), typically
• each elementary electroluminescent emitting zone may be a sub-pixel or a pixel.
• Each elementary electroluminescent emitter zone has two independent memories: a static memory, advantageously of the SRAM type, intended for graphic data, and an analog dynamic memory for the data coming from the video stream; said dynamic memory can be a capacity.
• the data is synchronous data, refreshed (updated) periodically, this refresh being typically controlled by a clock.
• the image can be static and reprogrammed (ie updated) as needed (ie each elementary emitter zone can be refreshed by sending a new given only when the contents of its static memory will change following this recording of the new data in said static memory), or refreshed periodically.
• each elementary emitter zone can be refreshed by sending a new given only when the contents of its static memory will change following this recording of the new data in said static memory, or refreshed periodically.
• it is asynchronous data, which does not depend on a clock; in the second case it may be synchronous data.
• the refresh rate of the image may be low, especially less than 0.1 Hz (or even 0 Hz); it is advantageously of the order of 0.1 Hz to 1 Hz, but can reach a frequency greater than 10 Hz.
• updated data is recorded in all the static memories at the same time, even if for certain elementary emitter zones this updated data is identical to the previous data which is replaced by the newly recorded data.
• the refresh rate can be fixed or variable.
• the refresh rate of the graphic data is independent of that of the video data; it is advantageously lower, but may also be greater.
• the subject of the invention is an electroluminescent display device comprising:
• a matrix of electroluminescent pixels formed of a plurality of pixels deposited on a substrate, in a matrix arrangement in rows and columns, each pixel being formed of at least one elementary emitter zone;
• a first control block configured to control a stream of graphical and / or alphanumeric data capable of being displayed on said matrix of electroluminescent pixels by using the static memory of the pixel;
• a second control block configured to control a video data stream capable of displaying on said pixel array using the dynamic memory of the pixel;
• each elementary emitter zone is connected to a static memory, addressed by said first control block, and to a dynamic memory, addressed by said second control block;
• said first and second control blocks are configured to display alternately or simultaneously data on the same array of electroluminescent pixels.
• Said first and second control blocks are configured to be able to display on the pixel matrix only the video data stream, or only the flow of graphical and / or alphanumeric data, or else to overlay said graphic and / or alphanumeric data stream video data stream.
• Said first control block is configured to send images to the matrix of the static memories of the pixels, for example via a first system of "select" lines and "data” columns.
• the first control block may include a clock or be controlled by a clock.
• Said second control block is configured to send:
• the second control block must include a clock or be controlled by a clock, the video data stream being a synchronous data stream.
• each elementary emitter zone comprises a dynamic memory, preferably a capacity, intended for video data.
• Each elementary emitting zone is connected to at least one, and preferably several (for example two or three), static memories, preferably of the SRAM type, destined for the static display. or with a lower refresh rate and / or with a lower number of intensity levels; these data may be graphical and / or alphanumeric data, static images or video data with a temporal and / or visual resolution lower than the video data passing through the dynamic memory.
• said first and second control blocks are configured so that said first control block has a number of bits of emission intensity levels lower than that of said second control block.
• said first control block is configured on three to eight bits of emission intensity levels, and / or said second control block is configured on at least eight bits of emission intensity levels; for example the second control block can be configured on ten, twelve or even fourteen bits of transmission level.
• said second control block has a refresh rate higher than that of said first control block. This refresh rate is preferably at least 25 Hz, more preferably at least 30 Hz, still more preferably at least 60 Hz, and optimally at least 90 Hz, and / or said second unit.
• control unit comprises a memory unit for storing said graphic and / or alphanumeric data for a static display.
• Figure 1 is a general view of the architecture of the display element illustrating an installation for displaying a video stream and / or graphics data.
• Figure 2a is a general view of the architecture of the display element illustrating an installation for displaying a video stream.
• Figure 2b is a general view of the architecture of the display element illustrating an installation for displaying a graphical data.
• Fig. 3 is a representation of the electrical scheme of a sub-pixel for the first embodiment.
• FIG. 4 is a representation of the electrical diagram of a sub-pixel for the second embodiment.
• Fig. 5 is a representation of the electrical scheme of a sub-pixel for the third embodiment.
• FIG. 6 is a timing diagram of transmission duration control signals applied to the inputs S1 to S4 of the pixel circuits.
• Figure 7 is a representation of the electrical diagram of a sub-pixel having an alternative embodiment.
• FIG. 1 relates to two different display modes that are implemented on a matrix of single electroluminescent elementary emitter zones, which carries the reference 38 in FIG.
• This may be in particular an OLED pixel matrix, and the present description refers to this case, knowing that the present invention also applies to a matrix of electroluminescent pixels using inorganic semiconductors or light-emitting diodes ( LED).
• each elementary emitter zone generally corresponds to one pixel; for a color screen each pixel is broken down into several individually addressed sub-pixels, and it is these sub-pixels that then correspond to the elementary emitter zones.
• FIG. 1 depicts a general view of the architecture of an installation 1 according to the invention which is provided with two separate image channels, namely a so-called video channel (with an incoming digital data stream) and a voice channel. so-called graphical data (with an incoming flow of digital data). These two paths are connected in the pixel only; each of the video and graphics channels has its own addressing system and a separate wiring at the level of the elementary emitter zone.
• This architecture is designed to control each elementary elementary emitter zone (i.e. each OLED sub-pixel) in constant current, but it can also be applied to a voltage control, with minor modifications (not shown in the figures).
• the incoming digital video signal is transformed into an analog signal corresponding to the gray levels by means of a system that includes a counter, a current source, a reference voltage generator, and optionally a correction table, associated with comparators at the level of the columns.
• the analog video signal thus obtained is stored temporarily in a dynamic memory associated with the elementary emitter zone.
• the graphics data channel addresses a matrix of SRAM direct access digital random access memory by means of a write procedure (and optionally also read) for this type of memory.
• the video block of the device comprises a counter (for example eight bits) and a comparator at the end of each column which compares the values of the counter with the video data.
• the meter feeds a weighted current source system (ie a reference voltage generator).
• a weighted current source system ie a reference voltage generator.
• the reference voltage of the generator is transferred first to the buffer buffer of the column, and then during the next cycle in the elementary emitter zone, via the column .
• the reference voltage generator generates a voltage which introduces into the elementary emitter zone a current proportional to the value applied to the input.
• FIG. 2a shows the circuit of the video channel for displaying a video stream 31 on the matrix of electroluminescent pixels 38.
• This figure shows a first block called control block 2 which will not be used in this display mode and whose operation will be explained below in relation to the second display mode.
• It is a second block 3 which allows the management of the video stream 31 until it is displayed on the pixel matrix 38.
• Said video stream 31, which is a digital data stream is sent to a horizontal shift register demultiplexer 34 then to a digital comparator 35 (which generates an analog data stream) then to a sampling and holding circuit 36 and finally to the vertical gates of the pixel matrix 38.
• a control signal 32 is sent to a sequencer 33 which supplies a line control element 37 (typically a vertical shift register or a demultiplexer) which gives the commands on the horizontal lines of the pixel matrix 38.
• a line control element 37 typically a vertical shift register or a demultiplexer
• a reference voltage generator unit 4 generates the reference voltage. It comprises an eight-bit counter module 41 which sends a signal 45 to a table of correspondence 42 (known by the acronym “LUT” for "Look-Up Table”), optional but recommended, which allows non-linear encoding.
• the value from the look-up table 42 is transmitted to a 10-bit coded reference voltage generator 44.
• the latter comprises another input for bringing a current source 43 weighted on ten bits.
• the outgoing reference voltage 47 of the voltage generator 44 supplies the sampling and holding circuit 36 of the second control block 3.
• the operation related to FIG. 1 is based on a digital video data stream 31 which is transformed by a set of digital comparator 35, counter 41, correspondence table 42 (optional) and reference voltage generator 44 into a signal analog to the end of each column and transmitted to the matrix of pixels 38.
• This type of flow requires fast processing for instant display.
• the video stream 31 is decomposed by the demultiplexer 34 to address to each pixel of the pixel array 38 the information to be displayed.
• the sequencer 33 transmits to the vertical shift register 37 the order to display the information on each pixel. This order is based on a control signal 32 which can be of the type:
• HSELNC Horizontal Synchronization
• VSELCH Vertical synchronization
• FIG. 2b is a general view of the architecture illustrating an installation 1 allowing the display of a graphic data item on said matrix of electroluminescent pixels 38.
• This architecture comprises a first control block 2, mentioned above, which comprises a serial data bus 121 transmitted to a module 122 capable of decoding the signals and sending them to a signal processor 123 for decoding the signals and sending them to the static memories of the pixel matrix 38, in a known manner and used in memory circuits.
• Said signal processor 137 is a control unit that generates the signal lines and columns for the first control block 2. It can be a signal generator or a microcontroller or, for more systems complex, of a microprocessor.
• the first control block 2 sends the data signal 131 graphics and / or alphanumeric to the table 132 of the second control block 3.
• the addressing table 132 is a horizontal addressing table which controls the addressing of the columns of the matrix of electroluminescent pixels 38; it also receives the horizontal addressing signal 133.
• the second control block 3 furthermore comprises a line control element 137 (vertical addressing table) which receives the vertical addressing signal 134 which controls the addressing of the lines of the electroluminescent display 38.
• the pixel matrix 38 also receives a reference voltage from unit 4 called the reference voltage generation unit.
• This last unit 4 comprises a reference voltage generator 44, a source module of current 43 and, optionally, a Pulse Width Modulation Type PWM signal generator (PWM, Pulse Width Modulation) 145.
• PWM Pulse Width Modulation Type PWM signal generator
• the operation related to FIG. 2b results from digital processing in a slow display process and implementing at the pixel level an SRAM type memory.
• the information is decomposed in the first control block 2, the set of information, data 131 and addressing 133, 134, makes it possible to display the graphic data on the matrix of pixels 38.
• the reference voltages 147 (here V ref , V refi and V ref 2) are generated by a reference voltage generator 44. They define the value of the current or of the output voltage of the transistors whose gate they drive, and therefore of the current or of the voltage on the pixel matrix 38. The reference voltages are therefore common to the matrix of electroluminescent pixels and give continuous signals to define gray levels.
• FIGS. 1, 2a and 2b correspond to modes of implementation for a dynamic or static display which are distinguished by their management of the data flow and by the refresh rate of the information displayed on the pixel matrix.
• the architecture of the device according to the invention combines these two functions on the same matrix of pixels 38.
• the architecture of the pixel matrix 38 comprises a plurality of pixels aligned horizontally and vertically.
• each pixel comprises four subpixels as elementary emitter zones; said subpixel may be mainly red, green and blue, while the fourth subpixel may be a complement in white or any other color. It can obviously provide only three sub-pixels per pixel, or it can be expected that each pixel is formed of a single elementary emitter zone.
• each elementary electroluminescent emitting zone has two independent memories: a static memory, intended for the graphic data, and a dynamic memory, intended for data from the video stream.
• FIGS. 3, 4, 5 and 7 show circuit embodiments at an elementary electroluminescent emitting zone, the structure and operation of which, in particular with respect to static or dymanic memory units, will be explained in FIG. larger detail below.
• FIG. 3 shows the electrical diagram 200 of a single elementary emitter zone 290 (which may be a sub-pixel) according to a first embodiment.
• the circuit comprises three parts, one for the dynamic part 270, another for the static part 280, and the display on the sub-pixel 290.
• the dynamic part 270 of the circuit comprises the arrival of the analog video stream 31 and a selection voltage 47 coming from the sequencer 33 on the gate of a transistor SW1 205.
• the cathode of the transistor 205 supplies a capacitor 210 and the gate of a TANAI transistor 215.
• the anode of the TANAI transistor 215 is connected to a voltage VANA.
• the cathode of the TANAI transistor 215 is connected to the sub-pixel 290 of display.
• This sub-pixel consists of a transistor SW2 220 connected to an OLED element 225.
• the transistor SW2 220 is also optional and allows for example to modulate the emission of the OLED element 225.
• the static portion 280 of the circuit (circled in FIG. 3 with a dotted line), intended for displaying graphical data, consists of a transistor T ANA 235 in series with a transistor SW3 245 in parallel with a transistor T ANA 3,240, this denier in series with a transistor SW4 250.
• the anodes of T A NA2 235 and TANA3 240 are connected to the anode of TANAI 215 and the cathodes of SW3 245 and SW4 250 are connected to the cathode of SW2 220 or TANAI 215 (when SW2 is optional).
• Each of the gates of T A NA2 235 and T A NA3 240 is connected to the reference voltage V re f 147.
• Each of the gates of the two transistors SW3 245 and SW4 250 is controlled by an SRAM cell memory function 255, 260.
• the memory cell is typically of type six transistors. In the diagram, only the BL ("Bit line”) and WL ("word line”) inputs, which are respectively fed by the line addressing signal 134 (vertical addressing signal) and the data line 131, are used.
• the programming of the memory is done by establishing a digital signal, ⁇ 'or T on the column BL and its opposite digital signal ⁇ ' or ⁇ 'on the column BLB ("Bit Line Bar") of each SRAM cell. Then a pulsed signal, generally positive, on the signal WL ("Word Line”) just record the signals BL and BLB in the memory of the SRAM type cell.
• the circuit according to FIG. 3 can be used in three different ways.
• the first use is the video mode, which essentially involves the dynamic portion 270, i.e., the memory is leveled 0 throughout the array, and data is transmitted by the video interface only; in other words the pixel is controlled only by the video data channel.
• a video stream 31 feeds the anode SW1 205.
• the transistor turns on only when the voltage V is enabled iect to turn on the display subpixel 290.
• the capacitor CS 210 is optional but highly recommended: it allows limit the overload as well as the maintenance of the voltage during a period of time on the power supply at the terminals of TANAI 215; so it acts as dynamic memory.
• this capacitor 210 may be functionally substituted by the gate capacitance of the transistor A NAI 215, especially in the case where the refresh rate of the video stream is sufficiently high. Since the static part 280 is not powered in this video operating mode, no current flows in this part.
• the second use is the graphic mode which essentially involves the static part 280.
• the memory function of the SRAM 245,250 cells makes it possible to keep the transistors SW3 245 and SW4 250 open or closed.
• the controlled openings of SW3 245 and SW4 250 allow the passage of the reference voltage V ref 147 to the OLED element 225.
• Mode 00 When the two transistors SW3 245 and SW4 250 are not conducting, the current flowing in the circuit is zero, as previously mentioned in the pure dynamic mode.
• Mode 01 The transistor SW4 250 is on, the relative current is sent to the display device of the sub-pixel 290.
• Mode 10 The transistor SW3 245 is on, the relative current is sent to the display device of the sub-pixel 290.
• Mode 1 1 the transistors SW3 245 and SW4 250 are on, the relative current is sent to the sub-pixel display device 290.
• the third use is a mixed mode called superposition: it applies both a video signal by the dynamic channel 270 and a graphic signal by the static part 280.
• the current in the OLED therefore corresponds to the superposition of the two signals; the display of the sub-pixel 290 is controlled by the converter formed by T A NA2 235 in series with SW3 245 and TANA3 240 in series with SW4 250 as well as TANAI 215.
• FIG. 3 proposes an advantageous embodiment of a four-level display (two bits) for the graphic part by using two SRAM 255,260 type memory cells; it may comprise complementary memory cells (for example 3, 4 or 5 SRAM cells) which will increase the capacity of the analog to digital converter in number of bits and therefore of possible modes.
• the architecture shown above is designed to power the OLED 225 in constant current, however it can also be applied to a voltage supply with minor modifications.
• Figure 4 depicts a second embodiment 300 of the arrangement at one of the subpixels.
• the circuit comprises three parts, one for the dynamic part 370, one for the static part 380, and one for the sub-pixel display 390.
• the dynamic part 370 comprises the arrival of the analog video signal 31 on the the anode and a line selection voltage 47 on the gate of a transistor SW1 305.
• the cathode of the transistor 305 supplies a capacitor 310 (acting as dynamic memory) and the gate of another transistor TANA 315.
• the anode of transistor TANAI 315 is connected to a voltage V ana .
• the cathode of the TANAI transistor 315 is connected to the sub-pixel display 390.
• the latter comprises a transistor SW2320 (optional) connected to an assembly comprising the OLED element 325.
• the static part 380 (surrounded in FIG. 4 by a dotted line) consists of two transistors SW3 345 and SW4 350 which are connected by their cathode to that of the transistor SW1 305.
• the anode of these two transistors is respectively connected respectively at a reference voltage 147 V refi and V ref 2.
• Each of the gates of the two transistors SW3 and SW4 is controlled by a memory function of the SRAM cell type 355,360.
• the memory cell is of type 6 or more transistors.
• the inputs BL ("Bit Line") and WL (“Word Line”) are respectively fed by the line address 134 and the data line 131.
• the circuit according to FIG. 4 can be used in three different ways.
• a first mode of use only the dynamic part 370 of the circuit is used.
• a video stream 31 feeds the anode SW1 305.
• the transistor turns on only when the voltage V seiect allows it to turn on the display portion 390.
• the capacitor CS 310 allows the maintaining the voltage for a period of time on the power supply of the gate of TANAI 315.
• the static part 380 is not powered, no voltage flows in this part.
• a second mode of use only the static part 380 of the circuit is used.
• the memory function of the SRAM 345,350 cells makes it possible to keep the transistors SW3 345 and SW4 350 open or closed.
• the display part 390 reacts to the different voltages applied to TANA 315, as indicated for example in the table above.
• the voltage state of the gate of the transistor T A NA is not necessarily known and it can be in a case of high impedance, in which case the transistor remains blocked.
• the Applicant proposes to use a Vseiect voltage to initialize the TANA transistor. To do this in the case of a graph only mode, the voltage V IECT is not controlled by the sequencer 33 but comes from the generating unit of the reference voltage 4.
• the signal of the voltage V is iect makes it possible to reset the transistor TANA before each write in the memory cells.
• the third mode of use is a mixed mode called superposition, which involves both the static portion 280 and the dynamic portion 270 of the circuit.
• the display of the sub-pixel 290 is controlled by the converter formed by T A NA 315.
• the display portion 390 passes both the video signal 31 and the stream from the different memory cells 355,360.
• circuits are described in which the display of sub-pixels 290 is current-driven, but the circuits can be voltage-controlled with minor modifications.
• Figure 5 depicts the third embodiment 400 of the arrangement of the circuit at one of the subpixels, for a particular case with four gray level bits.
• the circuit comprises three parts, a first part 470 for the dynamic display, a second part 480 for the static display, and a third part for the display on the sub-pixel 490.
• the dynamic part 470 comprises the arrival of the signal Analog video 31 on the anode of a transistor SW2 405 and a line selection voltage 47 on the gate of the transistor SW2 405.
• the cathode of the transistor 405 supplies a capacitor 410 (acting as dynamic memory) and the gate of a transistor T A NA 415.
• the anode of the transistor TANA 415 is connected to a voltage V A NA.
• the cathode of the TANA transistor 415 is connected to the subpixel display 490.
• the latter consists of a transistor SW2 420 connected to the OLED element 425.
• the static part 480 (circled in FIG. 5 of a line dotted line) consists of a transistor SW1 435 which is connected by its cathode to the gate of transistor T A NA 415.
• the anode of transistor SW1 435 is connected to a reference voltage V re f 147.
• the cathode of transistor SW1 435 is controlled by five signals from of the anode of transistors 440, 445, 450, 455, 460 arranged in parallel.
• the four control signals 146, S1, S2, S3, S4 control the gates of the four transistors 440, 445, 450, 455 which allow the transmission data from the cell memories 441, 446, 451, 456 respectively disposed on their anode to the gate of SW1 435.
• the fifth transistor 460 is connected by its cathode to the anode of SW1 435 and comprises a VANA analog power supply on its anode and a signal V reS and on its gate.
• the memory cell may be of the type with six or more transistors.
• the subpixel 425 of the display portion 480 operates at a single luminance level, it is therefore by controlling the emission time of the latter that the gray levels are achieved.
• the circuit according to FIG. 5 can be used in three different ways. According to a first mode of use only the dynamic part 470 of the circuit is used. A video stream 31 feeds the anode SW2 405. The transistor turns on only when the voltage Vseiect (from the module 33) allows it to turn on the display portion 490.
• the capacitor CS 410 allows the maintenance of the voltage during a time on the power supply to the terminal of TANA 415.
• the static part 480 transmits the signals S1, S2, S3 and S4 with a logic level of 1, and the level of the memory cells then has no effect on the voltage the sampling capacity of the capacitor CS 410 and therefore on the video signal 31.
• the static part 480 of the circuit is used.
• the writing in the memory cells 441, 446, 451, 456 is completely random.
• the signal refresh rate must be greater than 85 Hz or less than 12 ms. It is preferable to use an even higher frequency, around 120 Hz, to limit the interference concerning the writing and transmission times of the memory cells.
• the voltage state of the gate of the TANA transistor is not necessarily known and it can be in a case of high impedance, in which case the transistor remains blocked.
• the Applicant proposes to use a Vseiect voltage to initialize the TANA transistor.
• the voltage V IECT is not controlled by the sequencer 33 but comes from the generator 44 reference voltage 147.
• the signal of the voltage V is iect makes it possible to reset the transistor TANA before each write in the memory cells.
• the third mode of use is a mixed mode called superposition, which involves both the static portion 480 and the dynamic portion 470 of the circuit.
• the dynamic portion 270 sends the video signal 31 to the sampling capacity CS 410.
• the voltage level on the capacitor can be forced by the data from the cell memories 441, 446, 451, 456 which will force the display of the part.
• the voltage V is iect takes the characteristics of the signal of the sequencer 33 through the vertical shift register 37.
• FIG. 6 describes a timing diagram of control signals 146 of the transmission duration applied to the inputs S1 to S4 of the pixel circuits for blocking the transistor TANA between two conductions.
• This chronogram is presented as an example. It comprises four gray level bits modulated by the four control signals 146, S1, S2, S3, S4.
• the timing diagram describes the control signals S1, S2, S3, S4 by gray level bit.
• the transmission time generated by S1 corresponds to the first gray level, S2 to the second gray level bit to S4.
• the maximum luminance is reached if S1, S2, S3 and S4 are at 1.
• the control signals 146 which control S1, S2, S3, S4 are generated by the generator unit of the reference voltage 4 and more particularly by the pulse width modulated signal generator (abbreviated MLI) 145.
• MLI pulse width modulated signal generator
• Figure 6 also shows the signal of voltage V se iect. This modulated signal makes it possible to reset the gate of T A NA before each write in the memory cells. This signal applies to the last two embodiments.
• the diagram shown provides an advantageous embodiment, it may however be composed of complementary memory cells to increase the number of gray levels.
• Figure 7 shows a variant 500 of the first embodiment but may be declined in the three embodiments.
• This variant consists of adding a memory cell 505 connected to the gate of SW2 in each of the embodiments. Whatever the mode of polarization of the OLED, voltage or current, and whatever the embodiment using SRAM type memories, this memory cell can turn off the video data of the pixel to leave than the graphic way on the pixel. This modification makes it easier to implement the overlay mode.
• All of the embodiments use reference voltages or intensities 47 which are ideally generated by the reference voltage generating unit 4. It is possible to generate these reference intensities or voltages locally through supply voltages or analog / digital converters. This choice involves integrating on each set of sub-pixel electrical elements to build these reference voltages.
• All embodiments use current OLED control.
• all represented transistors of the PMOS type must be replaced by NMOS transistors.
• the voltage V A NA is typically of the order of 1.0 V to 3.3 V (for example 1.8 V)
• the voltage V Cath is typically of the order of -2 V to -9 V (for example -8Volt).
• the graphics data may have either priority (in the embodiment shown in Fig. 4) or overlap (in the embodiments shown in Figs. Figures 3, 5 and 7); in the latter case the currents in the OLED diode add up.
• the transistor SW1 is open and therefore the graphic value is written on the capacitor CS and therefore takes precedence over the video signal.
• the voltages V and V refi ref 2 may vary, which can in some cases cause a visible effect on the graphic display. This effect can be minimized if the impedance of the block 37 is much lower than that of the block 36, because in this case the control by the voltages V re fi and V re f2 takes over the control by the video voltages 305.

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• Computer Hardware Design (AREA)
• General Physics & Mathematics (AREA)
• Theoretical Computer Science (AREA)
• Control Of Indicators Other Than Cathode Ray Tubes (AREA)
• Control Of El Displays (AREA)
• Electroluminescent Light Sources (AREA)

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• 2018
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• 2019
  • 2019-05-15 WO PCT/FR2019/051100 patent/WO2019220055A1/fr unknown
  • 2019-05-15 EP EP19737162.8A patent/EP3794578A1/de active Pending
  • 2019-05-15 CN CN201980031461.6A patent/CN112106130B/zh active Active
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