EP3769593A1 - Éprouvette et procédé de vérification d'une carte de circuits imprimés - Google Patents

Éprouvette et procédé de vérification d'une carte de circuits imprimés

Info

Publication number
EP3769593A1
EP3769593A1 EP19712561.0A EP19712561A EP3769593A1 EP 3769593 A1 EP3769593 A1 EP 3769593A1 EP 19712561 A EP19712561 A EP 19712561A EP 3769593 A1 EP3769593 A1 EP 3769593A1
Authority
EP
European Patent Office
Prior art keywords
test
layers
circuit board
coupon
printed circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP19712561.0A
Other languages
German (de)
English (en)
Inventor
Josef Reitner
Daniel Schindler
Alexander-Manuel Stark
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BSH Hausgeraete GmbH
Original Assignee
BSH Hausgeraete GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BSH Hausgeraete GmbH filed Critical BSH Hausgeraete GmbH
Publication of EP3769593A1 publication Critical patent/EP3769593A1/fr
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0266—Marks, test patterns or identification means
    • H05K1/0268—Marks, test patterns or identification means for electrical inspection or testing
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/0929—Conductive planes
    • H05K2201/09336—Signal conductors in same plane as power plane
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0097—Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4638—Aligning and fixing the circuit boards before lamination; Detecting or measuring the misalignment after lamination; Aligning external circuit patterns or via connections relative to internal circuits

Definitions

  • the invention relates to a test coupon, which makes it possible to check the construction of a printed circuit board in a reliable and non-destructive manner. Furthermore, the invention relates to a method for checking a printed circuit board based on the test coupon described in this document.
  • Such manufacturing errors can typically only be detected within the framework of an examination method in which a printed circuit board is destroyed. For example, one or more micrographs of a printed circuit board can be made and measured under a microscope to detect a manufacturing error.
  • the present document deals with the technical task to enable an efficient and non-destructive quality assurance of a printed circuit board production.
  • a test coupon for use with at least one printed circuit board is described.
  • the printed circuit board and the test coupon are manufactured on a common use and therefore typically have the same layer structure.
  • the printed circuit board or the utility typically have M-1 substrates.
  • M masks can be provided for the M layers of utility.
  • a mask has the design or the layout of a respective desired position of the printed circuit board and the design or the layout of a test layer of the test coupon.
  • the layer designs or layouts can each be applied in pairs to a two-ply benefit.
  • dual-layered benefits may be mismatched (for example, in the wrong order) and / or false substrates may be used to merge the two-ply benefits (e.g., with a defective thickness and / or a defective dielectric property).
  • the printed circuit board produced may be defective.
  • a manufacturing defect of a printed circuit board can be detected in an efficient and non-destructive manner.
  • the test coupon M includes test layers for the corresponding M layers of the printed circuit board.
  • the M test layers may each have an electrically conductive reference surface and a test lead electrically insulated therefrom.
  • an isolation region can be created around the test lead of a test layer (by removing the electrically conductive material of the layer).
  • the reference surfaces of the M test layers preferably cover in each case 70%, 80% or more of the total area of the respective test layer.
  • the reference surfaces of the M test layers are designed such that the reference surface of a test layer is designed as a reference layer or as an electrical reference for the test line of at least one directly adjacent test layer.
  • the M test layers can be designed such that, for all M test layers, the reference surfaces of the one or more directly adjacent test layers form a reference layer or an electrical reference for the test line of the respective test layer.
  • the reference surfaces of the M test layers may be over one or more vias be electrically connected to each other.
  • the reference surfaces of the M test layers can each be connected to ground and / or ground.
  • test coupon with M test plots wherein the M test plots each have at least one (possibly exactly one) test lead.
  • the test leads each have reference layers in one or more directly adjacent test layers, and thus can be reliably used to measure one or more electrical properties of the test layers, and based thereon, to identify the different test layers. Due to the one-to-one relationship between test layers of the test coupon and layers of the printed circuit board can thus be concluded by measuring one or more electrical properties of the test layers on a manufacturing error of the printed circuit board.
  • the circuit board to be checked may have M set positions each having a target design (i.e., a target layout of the conductor pattern) in a target state (in particular, a healthy state).
  • a target design i.e., a target layout of the conductor pattern
  • the one or more, in particular the M-1, substrates of the printed circuit board in the target state in each case setpoints with respect to the substrate thickness and / or with respect to a dielectric property (in particular the dielectric constant of the material of the substrate).
  • the M test layers of the test coupon may be designed to deliver different reference values in the target state (i.e., in a defect-free production of the benefit) in a nondestructive measurement of at least one electrically relevant property of the M test layers.
  • at least one reference value can be provided for each measured property.
  • the reference values of the measured property for the different test layers may at least partially differ.
  • the at least M different reference values for at least one electrically relevant property can then be used to distinguish the M test positions of the test coupon from one another.
  • the M test layers may be associated with the M target layers in a one-to-one relationship so that a manufacturing defect of the printed circuit board may be detected by performing the nondestructive measurement on the test coupon.
  • a manufacturing error may include in particular: a faulty order of the M target positions; at least one layer of the printed circuit board which does not correspond to the required nominal position; and / or at least one substrate with a defective thickness and / or a faulty dielectric property.
  • the M test layers of a test coupon can thus be assigned as reference test layers to the different desired positions of the printed circuit board.
  • the M test layers in particular the test lines of the M test layers, can have a different design or layout.
  • the designs or layouts differ in such a way that the different test layers can be distinguished from one another by the non-destructive measurement of at least one electrically relevant characteristic of the test layers. If the measurement shows that the actual values measured for the test layers correspond to the reference values for the reference test positions, a manufacturing error can be ruled out. On the other hand, if the actual values at least partially deviate from the reference values, the presence of a manufacturing error can be detected. Possibly. Also, a particular manufacturing defect (e.g., a faulty location or an erroneous order of locations) may be identified.
  • the test coupon may have a longitudinal direction and a transverse direction, wherein the test coupon is greater in the longitudinal direction than in the transverse direction (eg by a factor of 2, 3, 4 or more).
  • the test leads of the M test layers can then each extend for the most part along the longitudinal direction (for example to 80%, 90% or more). It can be a Test line have a length which is substantially greater than the width of the test line, for example by a factor of 10, 20, 50 or more.
  • the test coupon may have a centerline along the length of the test coupon that divides the test coupon into a first half and a second half.
  • the test leads of the M test layers can then be arranged alternately in the first half and in the second half.
  • the reference surfaces of the M test layers may be arranged alternately at least for the most part (possibly also completely) in the second half and in the first half, in a complementary manner to the test lines.
  • the test leads of the M test layers can each have a contact point via which the test leads can each be electrically contacted individually.
  • the measurement of the at least one electrically relevant characteristic of a test layer can take place via the contact point of the test line of this test layer.
  • a time domain reflectometer can be connected to the contact point of a test line in order to carry out the measurement of the at least one electrically relevant property.
  • the M test layers in particular the test lines of the M test layers, may differ from one another such that the M test layers can be distinguished from one another on the basis of current and / or voltage measurements on the M test lines (in particular at the contact points of the M test lines).
  • the M test layers may differ from one another in such a way that it is possible to distinguish the M test layers by means of the measurements of a time domain reflectometer.
  • the test lines of the M test layers may at least partially have different lengths.
  • the test lines of the M test layers may have at least partially different impedances.
  • the test lines of the M test layers can at least partially have a separate reflection point from the end (remote from the contact point) of the respective test line, at which an electrical pulse is at least partially reflected.
  • the test leads of the M test layers may at least partially have reflection sites which differ from each other with respect to the position and / or with respect to the shape.
  • the M test layers, in particular the test lines of the M test layers can thus each have a different design or layout, which makes it possible to distinguish the M test layers by means of a current and / or voltage measurement, in particular by means of a time domain reflectometer measurement. Thus, a particularly efficient detection of a manufacturing error of a printed circuit board is made possible.
  • a method for checking a printed circuit board is described.
  • the printed circuit board was produced in a utility together with a test coupon, the test coupon preferably being designed as described in this document.
  • the printed circuit board has M layers, with M equal to 2 or more, the layers being electrically isolated from each other by a substrate or a laminate.
  • the test coupon has corresponding M test layers, the M layers of the printed circuit board being assigned in a desired state (ie the M desired positions) to M reference test layers of the test coupon.
  • the M reference test layers provide M reference values for the measurement of at least one electrically relevant property.
  • the one or more, in particular the M-1, substrates of the printed circuit board in the nominal state can each have reference values with respect to a substrate thickness and / or with respect to a dielectric property.
  • the method comprises capturing sensor data for the M test layers of the test coupon by measuring the at least one electrically relevant property.
  • sensor data can be detected by means of a time domain reflectometer.
  • the time domain reflectometer can be connected to the individual contact points of test leads of the M test layers.
  • the method includes detecting a manufacturing error of the printed board based on the sensor data and based on the reference values.
  • the detected sensor data may include an actual value corresponding to the reference value for each test position.
  • the sensor data may be such that an actual value corresponding to the reference value can be determined on the basis of the sensor data for each test position.
  • the method may then include (possibly in pairs) comparing the actual values with the corresponding reference values. It can then be detected based on the comparison, a manufacturing error of the printed circuit board.
  • an order of the M reference test positions and the positions of the printed circuit board assigned to the M reference test positions can be determined.
  • the electrically relevant property used to detect the different reference test locations may include one or more of: the impedance of a test lead or a test pad; a property of a test line or a test location determined by time domain reflectometry; the length of a test line; the presence of a reflection point separate from the end of a respective test line on a test line at which an electrical pulse is at least partially reflected; and / or the position and / or the shape of a reflection point on a test line.
  • the method may include determining, on the basis of the sensor data, actual impedance values of the respective impedance of the M test layers, in particular the Test leads of the M test layers.
  • the reference values can indicate reference impedance values for the M test positions, in particular for the M test lines. On the basis of the actual impedance values (and on the basis of the reference impedance values), a defective thickness and / or a faulty dielectric property of at least one substrate of the printed circuit board can then be detected.
  • an actual length of at least one of the test lines of the M test layers, and / or an actual position and / or an actual shape of a reflection point on at least one of the test lines of the M test layers can be determined on the basis of the sensor data.
  • the reference values may include a reference length of the at least one test line, a reference position of the reflection point and / or a reference shape of the reflection point of the at least one test line. It can then be detected on the basis of the actual length, the actual position and / or the actual shape (and on the basis of the reference length, the reference position and / or the reference shape) a faulty position of the printed circuit board.
  • test coupon described in this document and the method described in this document may be combined in a variety of ways.
  • features of the claims can be combined in a variety of ways.
  • FIG. 1 a shows an exemplary benefit with a multiplicity of printed circuit boards and a test coupon in a plan view
  • FIG. 1b shows an exemplary multi-layer printed circuit board or an exemplary multi-layered benefit in a side view
  • FIG. 2a shows an exemplary layer structure of a test coupon
  • FIGS. 2b to 2d show exemplary test layers of a test coupon
  • FIG. 3 shows a flow diagram of an exemplary method for checking a printed circuit board on the basis of a test coupon.
  • FIG. 1 a shows a utility 100 (ie, a total circuit board) that has multiple (possibly identical) circuit boards or circuit boards 101 in the illustrated example.
  • the utility 100 is manufactured in a single manufacturing process, thus making it possible to produce multiple circuit boards 101 in a single manufacturing process.
  • a patch of the benefit 100 may be used to make at least one test coupon 110.
  • a test coupon 110 may be used, for example, to check the impedance values of the lines of individual layers of the printed circuit boards 101.
  • 1 b shows the layer structure of an exemplary four-ply benefit 100.
  • a laminate or substrate 122 can be coated from both sides with a conductive layer or layer 121 (in particular a layer of copper).
  • a conductive layer or layer 121 in particular a layer of copper.
  • conductor tracks can then be produced in the layers 121.
  • a two-layer printed circuit board with electrical leads on both sides of a substrate 122 can be manufactured.
  • two-layer printed circuit boards can be produced with layers 121 having a specific design or layout.
  • Exemplary manufacturing defects are:
  • Defective properties e.g., thickness, material, dielectric constant, etc.
  • a swapping of the layers 121 (for example, several two-ply
  • Circuit boards are assembled in the wrong order to produce a utility 100 and a printed circuit board 101, respectively.
  • test coupon 110 of a benefit 100 is produced in the same manufacturing process as the leader cards 101 on the benefit 100. As a result, manufacturing errors in the production of a benefit 100 also affect a test coupon 110 io
  • test coupon 110 of a benefit 100 can thus be used to detect manufacturing errors.
  • the test coupon 110 has a reference surface 212 and at least one test line 211, 213 in each layer 241 (also referred to as test layer in this document).
  • the test power 211 may be formed in an outer layer 241 as a microstrip and the test line 213 of an intermediate layer 241 as a stripline.
  • the reference surface 212 of a layer 241 can be formed by the largely continuous electrically conductive layer (in particular the copper layer) of the layer 241. In one or more localized isolation regions 215, the electrically conductive layer of the layer 241 may be removed to form a test line 211 electrically isolated from the reference surface 212.
  • reference surfaces 212 and test lines 21 1, 213 can alternate in directly successive layers 24, so that the test line 213 of an intermediate layer 241 is surrounded by the reference surfaces 212 of the two directly adjacent layers 241. Furthermore, the test line 211 of an outer layer 241 has a reference surface 212 in exactly one directly adjacent layer 241.
  • Fig. 2a further illustrates vias (vias) 214 through which the reference surfaces 212 of the different layers 241 may be electrically conductively connected (particularly grounded).
  • Such a layer construction may provide a test coupon 110 comprising for each layer 241 at least one test line 211, 213 having a unique relationship with at least one reference surface 212 and / or at least one reference potential (e.g., GND).
  • a test coupon 110 comprising for each layer 241 at least one test line 211, 213 having a unique relationship with at least one reference surface 212 and / or at least one reference potential (e.g., GND).
  • FIGS. 2b to 2d show exemplary layers 241 of a test coupon 110 in a top view (ie along the surface of a test coupon 110).
  • the layers 241 each have an electrically conductive reference surface 212 which can cover much of the total area of a layer 241 (eg 70%, 80% or more).
  • the layers 241 each have a test line 21 1, 213, which is electrically insulated from the reference surface 212 by an insulating region 215.
  • the insulating region 215 may be formed by removing the conductor material of a layer 241.
  • test leads 21 1, 213 may be arranged alternately on a first side (see FIG. 2 b) or on a second side (see FIG. 2 c) of the test coupon 110 (with respect to a transverse direction 232 of the test coupon 110 ). Furthermore, the test leads 21 1, 213 may extend along a longitudinal direction 231 of the test coupon 110.
  • the test line 211, 213 of a layer 241 is preferably designed such that the test line 21 1, 213 can be electrically contacted via a contact point or via a contact point 220.
  • the test coupon 110 may be constructed such that the individual test leads 21 1, 213 of the individual layers 241 can each be contacted electrically individually via a contact point 220.
  • test lines 21 1, 213 in the different layers 241 can be constructed differently.
  • the test lines 21 1, 213 may have different property values for one or more measurable characteristics.
  • the one or more properties may be such that they can be detected by means of an electrical measuring method (in particular by means of a time domain reflectometer). For example, properties are
  • M test lines 21 1, 213 or M test layers can be defined, each of which has a uniquely identifiable combination of property values of one or more properties exhibit.
  • the different layers 121 of a printed circuit board 101 to be produced can then each be assigned one of the different test layers 241 as reference test layers.
  • the properties of the test layers 241 and the test lines 21 1, 213 can then be used to check whether or not there is a manufacturing error of the printed circuit board 101.
  • the assignment preferably takes place in such a way that, in the case of a defect-free production 100, the alternating structure of test line 211, 213 and reference surface 212 shown in FIG. 2b results.
  • the properties of the different test layers 241 of the test coupon 110 can be measured.
  • a Time Domain Reflectometer may be used to detect sensor data related to the length 221 of a test line 21 1, 213 and / or to an impurity 223 on a test line 21 1, 213.
  • sensor data relating to the individual test layers 241 of a test coupon 110 can be detected.
  • a test line 211, 213 in each case a microstrip 21 1 in the outer layers 241, in each case one stripline 213 in the one or more inner layers 241) can thus be applied in each layer 241.
  • the test lines 21 1, 213 can each be measured with a Time Domain Reflectometer.
  • the test lines 21 1, 213 can be measured with regard to their impedance and / or their length 221.
  • a typical impedance results for each layer 121, 241 of the utility 100. If this impedance is exceeded or undershot for at least one layer 241 of a test coupon 110, then it can be concluded that false dielectrics or dielectrics with a different layer thickness have been used as substrates 122, 123.
  • the lengths 221 of the individual test lines 21 1, 213 of a test coupon 110 can be different and it can be determined by measuring the lengths 221 (position assignment over the length 221 of the individual test lines 21 1, 213), whether layers 121, 241 in the layer structure of the benefit 100 were reversed.
  • the test leads 211, 213 in the individual layers 241 of a test coupon 110 can also be at least partially the same length.
  • test lines 211, 213 (typically short) (reflection) locations 223 may have different impedance (e.g., line widening or line thinning). These impurities 223 may be in any position 241 of the test coupon 110 at a different position 224 to ensure a unique location assignment. It can thus be a position assignment on the position 224 of interference or reflection points 223 done. Alternatively or additionally, the interference or reflection points 223 in the individual layers 241 may have different lengths 226.
  • FIG. 3 shows a flowchart of an exemplary method 300 for testing a multilayer printed circuit board 101.
  • the printed circuit board 101 has been produced in a utility 100 together with a test coupon 110. Further, the circuit board 101 has M layers 121, with M equal to 2 or more, each electrically isolated from each other by a substrate 122, 123.
  • the test coupon 110 has corresponding M test plies 241.
  • the M layers 121 of the printed circuit board 101 are assigned in a desired state M reference test layers 241 of the test coupon 1 10.
  • the printed circuit board 101 in a desired state M may have target positions 121 with a specific desired design.
  • the different desired positions 121 are assigned M different reference test positions 241 of the test coupon 110. This can be achieved, for example, by virtue of the fact that the masks for producing the different layers 121 of the utility 100 each have the design a desired position 121 and the design of the respectively assigned reference test layer 241 have.
  • test coupon 110 has the M reference test plies 241 (in the correct order). If this is the case, it can be concluded that also the circuit board 101 manufactured in the same utility 100 has the M target layers 121 (in the correct order). On the other hand, it can be concluded that a manufacturing error of the printed circuit board 101. Furthermore, if necessary, a specific manufacturing defect can be identified.
  • the different reference test plies 241 can thus be identified by measuring one or more electrically relevant properties based on the reference values for the one or more electrically relevant properties. The measurement of values of the one or more electrically relevant properties can take place on the basis of a time domain reflectometry of the M reference test plies 214, in particular of the test leads 211, 213 of the M reference test plies 214.
  • the method 300 includes detecting 301 sensor data for the M test layers 241 of the test coupon by measuring the at least one electrically relevant property.
  • sensor data relating to the M test plies 241 can be detected by means of a time domain reflectometer.
  • the method 300 includes detecting 302 a manufacturing error of the printed board 101 based on the sensor data and based on the reference values.
  • the measures described in this document enable efficient quality assurance in the production of printed circuit boards 101.
  • it can be checked in particular whether the correct dielectrics have been used for the substrates 122, 123 of a printed circuit board 101.
  • the layer structure of a printed circuit board 101 are checked. It can do the verification without using a destructive
  • Measurement which leads to a reduction in the cost of quality assurance.
  • a production-accompanying test per benefit 100 and / or per production lot is made possible by the measures described.
  • the identification of manufacturing problems can be facilitated by the measures described.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)

Abstract

L'invention concerne une éprouvette (110) s'utilisant (100) avec au moins une carte de circuits imprimés (101). La carte de circuits imprimés (101) présente M couches (121), M étant égal à 2 ou plus, qui sont isolées chacune électriquement par un substrat (122, 123). L'éprouvette (110) comprend M couches témoin (241) pour les M couches (121) correspondantes de la carte de circuits imprimés (101). Les M couches témoin (241) présentent chacune une surface de référence (212) électroconductrice et une ligne témoin (211, 213) qui en est isolée électriquement. Selon l'invention, la surface de référence (212) d'une couche témoin (241) est conçue sous forme de couche de référence pour la ligne témoin (212, 213) d'une couche témoin (241) directement avoisinante.
EP19712561.0A 2018-03-19 2019-03-19 Éprouvette et procédé de vérification d'une carte de circuits imprimés Pending EP3769593A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102018204108.3A DE102018204108A1 (de) 2018-03-19 2018-03-19 Testcoupon und Verfahren zur Überprüfung einer Leiterplatte
PCT/EP2019/056782 WO2019179984A1 (fr) 2018-03-19 2019-03-19 Éprouvette et procédé de vérification d'une carte de circuits imprimés

Publications (1)

Publication Number Publication Date
EP3769593A1 true EP3769593A1 (fr) 2021-01-27

Family

ID=65861284

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19712561.0A Pending EP3769593A1 (fr) 2018-03-19 2019-03-19 Éprouvette et procédé de vérification d'une carte de circuits imprimés

Country Status (4)

Country Link
EP (1) EP3769593A1 (fr)
CN (1) CN111869336B (fr)
DE (1) DE102018204108A1 (fr)
WO (1) WO2019179984A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3982221A1 (fr) * 2020-10-12 2022-04-13 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Système de conception de coupon pour soutenir les tests de qualité de supports de composants

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1041637A (ja) * 1996-07-23 1998-02-13 Nec Corp 高密度多層配線基板

Family Cites Families (5)

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Publication number Priority date Publication date Assignee Title
US4510446A (en) * 1982-11-03 1985-04-09 Burroughs Corporation Test coupons for determining the registration of subsurface layers in a multilayer printed circuit board
JP2001251061A (ja) * 2000-03-02 2001-09-14 Sony Corp 多層型プリント配線基板
JP4834937B2 (ja) * 2001-08-22 2011-12-14 凸版印刷株式会社 高周波回路用多層配線板
US20070167056A1 (en) * 2006-01-17 2007-07-19 Universal Scientific Industrial Co., Ltd. Multi-layer printed circuit board, and method for detecting errors in laminating order of layers thereof
JP5335840B2 (ja) * 2011-03-15 2013-11-06 株式会社オーク製作所 露光装置

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1041637A (ja) * 1996-07-23 1998-02-13 Nec Corp 高密度多層配線基板

Also Published As

Publication number Publication date
CN111869336A (zh) 2020-10-30
CN111869336B (zh) 2024-09-03
WO2019179984A1 (fr) 2019-09-26
DE102018204108A1 (de) 2019-09-19

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