EP3679599A1 - Boîtiers multi-composants de haute densité en série - Google Patents

Boîtiers multi-composants de haute densité en série

Info

Publication number
EP3679599A1
EP3679599A1 EP18853638.7A EP18853638A EP3679599A1 EP 3679599 A1 EP3679599 A1 EP 3679599A1 EP 18853638 A EP18853638 A EP 18853638A EP 3679599 A1 EP3679599 A1 EP 3679599A1
Authority
EP
European Patent Office
Prior art keywords
high density
density multi
component package
interposer
component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP18853638.7A
Other languages
German (de)
English (en)
Other versions
EP3679599A4 (fr
Inventor
James A. BURK
John Bultitude
Galen W. MILLER
John E. Mcconnell
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kemet Electronics Corp
Original Assignee
Kemet Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US15/699,654 external-priority patent/US10681814B2/en
Priority claimed from US15/804,515 external-priority patent/US10707145B2/en
Priority claimed from US15/852,799 external-priority patent/US10178770B1/en
Application filed by Kemet Electronics Corp filed Critical Kemet Electronics Corp
Publication of EP3679599A1 publication Critical patent/EP3679599A1/fr
Publication of EP3679599A4 publication Critical patent/EP3679599A4/fr
Pending legal-status Critical Current

Links

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    • H05K2201/1053—Mounted components directly electrically connected to each other, i.e. not via the PCB
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    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10636—Leadless chip, e.g. chip capacitor or resistor

Definitions

  • the present invention is related to a high density package of electronic components, and a method of making the package, wherein increased functionality can be achieved in a limited footprint. More specifically, the present invention is specific to a high density package comprising combinations of interposers, higher temperature conductive adhesive (HTCA) and high temperature insulating adhesive (HTIA) which allows for serial connectivity of a variety of electronic components.
  • HTCA higher temperature conductive adhesive
  • HTIA high temperature insulating adhesive
  • MLCC multi-layer ceramic capacitors
  • TLPS transient liquid phase sintering
  • the leadless stacks provide capacitors in electrical parallel only and therefore the applications are somewhat limited.
  • Serially connected components can be achieved by bonding the terminals of the respective components end-to-end, rather than in a stack, however this increases the space required for mounting which is contrary to the overwhelming desire for miniaturization.
  • the present invention is related to high density multi-component packages. [0008] More specifically, the present invention is related to high density multi- component packages which allow for serial or parallel connectivity of different components in the package.
  • a particular feature of the invention is the ability to mount a high density package on a circuit board either vertically or horizontally.
  • the high density multi-component package comprises at least two electronic components wherein each electronic component of the electronic components comprise a first external termination and a second external termination. At least one interposer is between the adjacent electronic components and attached to the interposer by an interconnect wherein the interposer is selected from an active interposer and a mechanical interposer. Adjacent electronic components are connected serially.
  • the electronic circuit comprises a high density multi-component package comprising at least two electronic components wherein each electronic component comprises a first external termination and a second external termination.
  • An interposer is between adjacent electronic components wherein the interposer is selected from an active interposer and a mechanical interposer.
  • the adjacent electronic components are connected serially.
  • a circuit board is provided wherein the circuit board comprises traces wherein at least one trace is an active trace and at least one trace is a mechanical pad . At least one first external termination of a first electronic component is in electrical contact with one active trace and at least one second external termination of a second electronic component is in electrical contact with a mechanical pad.
  • each electronic component comprises a first external termination and a second external termination
  • interposer is selected from an active interposer and a mechanical interposer
  • each electronic component comprises a first external termination and a second external termination
  • interposer is selected from an active interposer and a mechanical interposer
  • first external terminations attaching the first external terminations to first traces on the interposer and second external terminations to second traces on the interposer with an interconnect wherein adjacent electronic components are connected serially; providing a circuit board comprising traces wherein at least one trace is an active trace and at least one trace is a mechanical pad;
  • a high density multi-component package has at least two electronic components wherein each electronic component comprises a first external termination and a second external termination. At least one first adhesive is between adjacent first external terminations of adjacent electronic components. At least one second adhesive is between the adjacent electronic component and at least two adjacent electronic components are connected serially.
  • the first adhesive and second adhesive are independently selected from a high temperature conductive adhesive and a high temperature insulating adhesive.
  • the electronic circuit has a high density multi-component package wherein the package comprises at least two electronic components wherein each electronic component comprises a first external termination and a second external termination, at least one first adhesive between adjacent first external terminations, at least one second adhesive between adjacent electronic components and wherein at least two adjacent electronic
  • the first adhesive and second adhesive are independently selected from a high temperature conductive adhesive and a high temperature insulating adhesive.
  • the electronic circuit also comprises a circuit board comprising traces wherein at least one trace is an active trace and at least one trace of said traces is a mechanical pad. At least one first external termination of a first electronic component is in electrical contact with one active trace. At least one second external termination of a second electronic component is in electrical contact with a mechanical pad.
  • Yet another embodiment is provided in a method for forming a high density multi-component package.
  • the method includes:
  • each electronic component comprises a first external termination and a second external termination
  • first adhesive and second adhesive are independently selected from the group consisting of a high temperature conductive adhesive and a high temperature insulating adhesive
  • a high density multi-component package comprising at least two electronic components. Each electronic component comprises a first external termination and a second external termination. At least one electrical connection is between adjacent first external terminations of adjacent electronic components. At least one mechanical connection is between adjacent electronic components. At least two adjacent electronic components are connected serially. [0018] Yet another embodiment is provided in a method for forming a high density multi-component package comprising:
  • each electronic component comprises a first external termination and a second external termination
  • FIGs. 1 and 1A are schematic side view representations of embodiments of the invention.
  • Fig. 2 is a schematic side view representation of an embodiment of the invention.
  • Fig. 3 is a schematic side view representation of an embodiment of the invention.
  • Fig. 4 is a schematic side view representation of an embodiment of the invention.
  • Fig. 5 is a schematic side view representation of an embodiment of the invention.
  • Fig. 6 is a schematic side view representation of an embodiment of the invention.
  • Fig. 7 is a schematic cross-sectional side view representation of an embodiment on the invention.
  • Fig. 8 is a schematic cross-sectional side view representation of an embodiment on the invention.
  • Fig. 9 is a schematic cross-sectional side view representation of an embodiment on the invention.
  • Fig. 10 is a schematic top view representation of an embodiment of the invention.
  • Fig. 1 1 is a schematic top view representation of an embodiment of the invention.
  • Fig. 12 is a schematic top view representation of an embodiment of the invention.
  • Fig. 13 is a schematic top view representation of an embodiment of the invention.
  • Fig. 14 is an electrical schematic representation of an embodiment of the invention.
  • Fig. 15 is an electrical schematic representation of an embodiment of the invention.
  • Fig. 16A is a schematic side view representation of an embodiment of the invention.
  • Fig. 16B is a schematic side view representation of an embodiment of the invention.
  • Fig. 17 is a schematic top view representation of an embodiment of the invention.
  • Fig. 18 is a schematic side view representation of an embodiment of the invention.
  • Fig. 19 is a schematic top view representation of an embodiment of the invention.
  • Fig. 20 is a schematic side view representation of an embodiment of the invention.
  • Fig. 21 is an electrical schematic representation of an embodiment of the invention.
  • Fig. 22 is an electrical schematic representation of an embodiment of the invention.
  • Fig. 23 is schematic side view representation of an embodiment of the invention.
  • Fig. 24 is schematic side view representation of an embodiment of the invention.
  • Fig. 25 is schematic side view representation of an embodiment of the invention.
  • Fig. 26 is schematic side view representation of an embodiment of the invention.
  • Fig. 27 is an electrical invention.
  • Fig. 28 is an electrical invention.
  • Fig. 29 is an electrical invention.
  • Fig. 30 is a schematic invention.
  • Fig. 31 is a schematic invention.
  • Fig. 32 is a schematic invention.
  • Fig. 33 is a schematic embodiment on the invention.
  • Fig. 34 is a schematic embodiment on the invention.
  • Fig. 35 is a schematic embodiment on the invention.
  • Fig. 36 is a schematic embodiment on the invention.
  • Fig. 37 is an electrical invention.
  • Fig. 38 schematic cross-sectional top view representation of an embodiment on the invention.
  • FIG. 39 schematic cross-sectional top view representation of an embodiment on the invention.
  • FIG. 40 schematic cross-sectional top view representation of an embodiment on the invention.
  • Figs. 41 and 42 are electrical schematic representations of embodiments of the invention.
  • Fig. 43 is an electrical schematic representation of an embodiment of the invention.
  • Fig. 44 is a schematic cross-sectional side view representation of an embodiment on the invention.
  • FIG. 45 schematic cross-sectional top view representation of an embodiment on the invention.
  • Fig. 46 is a schematic cross-sectional side view representation of an embodiment on the invention.
  • Fig. 47 is a schematic cross-sectional side view representation of an embodiment on the invention.
  • Figs. 48 and 48A are schematic cross-sectional top view representations of embodiments on the invention.
  • Fig. 49 is a schematic cross-sectional top view representation of an embodiment on the invention.
  • Fig. 50 is a schematic cross-sectional top view representation of an embodiment on the invention.
  • Fig. 51 is a schematic cross-sectional top view representation of an
  • the present invention is related to a high density multi-component package of electronic components wherein at least some of the electronic components are serially connected and the package minimizes surface area required on the circuit board. More specifically, the present invention is related to a stack of electronic components comprising a combination of high temperature conductive adhesives (HTCA), high temperature insulating adhesives (HTIA) and interposers between adjacent external terminations of adjacent electronic components or between adjacent electronic components.
  • HTCA high temperature conductive adhesives
  • HTIA high temperature insulating adhesives
  • interposer provides for a connection between one terminal of each adjacent component within the stack of electronic components.
  • the interposer may also provide for inter-component insulation and/or separation to avoid arcing in high voltage applications.
  • the package of electronic components can be surface mounted with the end terminals of the outermost components electrically connected to the circuit.
  • the high density multi-component package can be used to form high density packages containing mixed electronic components and provides the flexibility to connect the electronic component in electrical series as well as in electrical parallel thereby enabling high density packages of multifunctional components with a variety of electronic configurations.
  • the combination of HTCA and HTIA between adjacent electronic components provides for a serial configuration.
  • the HTCA provides for an electrical connection between terminals of adjacent components within the stack of electronic components.
  • the HTIA provides a mechanical bond and electrical insulation between adjacent components.
  • the combination of HTCA and HTIA allows components to be arranged in a higher density package with serial and parallel connectivity. This compaction can be beneficial in either the vertical or horizontal mounting configuration.
  • the package of electronic components can be surface mounted with the end terminals of the outermost
  • the high density multi-component package can be used to form high density packages containing mixed electronic components and provides the flexibility to connect the electronic component in electrical series as well as in electrical parallel thereby enabling high density packages of multifunctional components with a variety of electronic configurations.
  • the HTCA and HTIA can be bonded in the same process or separately. Furthermore, the components can be formed into a bonded stack and the stack subsequently mounted to a circuit board or the circuit board mounting and stack formation can occur in concert.
  • the interposers in an embodiment, have an electrical connection through the interposer as either a via through-hole or a conductive wrap around the substrate of the interposer as will be described.
  • Solder pads which may be a component of a trace, are preferably provided on the via or wrap to form a mechanical and electrical bond to the external termination of the electronic component.
  • the via may be filled or unfilled with electrically conductive material. In the unfilled case the via can be filled with interconnecting material during assembly to connect components on opposite sides.
  • Sintered metal pastes, conductive adhesives or TLPS are suitable interconnects since they can be cured or sintered to form a connection in the assembly without flowing out during the process.
  • These conductive pads can be formed using any conductive metal. Copper and aluminum are common in the case of organic interposers but for inorganic interposers any thick or thin conductive metals can be used. These may also be protected by over-plating.
  • Interposers are illustrated in cross-sectional schematic view in Figs. 1 and 2.
  • the interposer, 10 comprises active pads, 12, formed by a via, 14, extending through the substrate, 16, thereby providing electrical connection between conducting pads, 18, on either side of the substrate.
  • Mechanical pads, 20, are not in electrical contact with a mechanical pad opposite thereto on the substrate.
  • the active pad, 12, is in the form of a wrap-around pad, and the mechanical pads, 20, are portions of a trace on the surface of the substrate, 16.
  • An interposer with at least one active pad and at least one optional mechanical pad will be referred to herein as an active interposer.
  • An interposer with an unfilled via, 15, is illustrated in Fig. 1A wherein the via, 14', can be filled before or during assembly.
  • FIG. 3 wherein a high density multi-component package, 30, is illustrated in schematic side view.
  • a high density multi-component package, 30, is illustrated in schematic side view.
  • four electronic components are illustrated for the purposes of discussion without limit thereto.
  • Each electronic component is arbitrarily numbered for the purposes of illustration and discussion only.
  • interposers, 10 are between adjacent electronic components.
  • Each electronic component has one external termination, 32, in electrical contact with an active pad, 12, thereby forming an electrical connection and one external termination in contact with, and adhered to, a mechanical pad, 20, thereby forming a mechanical connection.
  • the active pad is
  • the external terminations are preferably bonded to the pads by an interconnect, 34, such as a conductive adhesive, a solder, polymer solder, TLPS bond, sintered metal interconnects, diffusion solders or direct copper bonds as will be discussed elsewhere herein.
  • interconnect 34 such as a conductive adhesive, a solder, polymer solder, TLPS bond, sintered metal interconnects, diffusion solders or direct copper bonds as will be discussed elsewhere herein.
  • Active pads and mechanical pads of adjacent interposers alternate thereby providing for an electronic path beginning arbitrarily at external termination, 32 1 , of electronic component 1 , and ending with external termination, 32 8 , of electronic component 4.
  • the four electronic components are therefore serially connected. While four electronic components are a sufficient number to illustrate the invention it is to be understood that the invention can be extended from two components to any number of electronic components and a large variety of variations as will be realized. It is preferable that the number of components is at least two to no more than 100.
  • FIG. 4 wherein a high density multi-component package, 30, is illustrated in schematic side view.
  • Fig. 4 four electronic components are illustrated for the purposes of discussion without limit thereto. Each electronic component is arbitrarily numbered for the purposes of illustration and discussion only.
  • HTCA's, 310, and HTIA's, 31 1 are between adjacent external terminations of adjacent electronic components.
  • Each electronic component has one external termination, 32, in either electrical contact with an adjacent external termination through a HTCA, 310, or physically attached with an electrically insulating bond through a HTIA, 311 , which is preferably between adjacent external terminations.
  • the HTCA forms an electrical connection and the HTIA forms a mechanical connection.
  • Fig. 4 an electronic path is formed beginning arbitrarily at external termination, 32 1 , of electronic component 1 , and ending with external termination, 32 8 , of electronic component 4.
  • the four electronic components are therefore all serially connected. While four electronic components are a sufficient number to illustrate the invention it is to be understood that the invention can be extended from two components to any number of electronic components and a large variety of variations as will be realized. It is preferable that the number of components is at least two to no more than 100.
  • FIG. 5 An embodiment of the invention will be described with reference to Figs. 5 and 6 wherein a high density multi-component package vertically mounted to a substrate, 36, is illustrated in schematic side view.
  • Active circuit traces, 38, on the substrate, 36 are in functional electronic connection with external terminations, 32 1 and 32 8 .
  • External termination, 32 1 is directly attached to active circuit trace 38 1 by an interconnect, 42, which may be the same as the interconnect between the external terminations and interposers or it may be different.
  • a connector, 44 is in electrical contact with external termination 32 8 and active trace 38 2 wherein the active traces, 38, are integral to the electronic circuit of a device.
  • the connector may be an electrical connection, such as a wire or jumper, and otherwise provide no further function or the connector may be a functional connection such as an electrical component.
  • Particularly preferred connectors include a resistor, a fuse, an inductor or a flexible circuit.
  • a mechanical pad, 40 provides mechanical stability and is directly attached to external termination 32 2 by an interconnect, 42.
  • a flex circuit connector, 144 shown in cross-sectional schematic view, comprises a flexible substrate, 160.
  • An optional but preferred mechanical pad, 20, provides for mechanical attachment to an external termination, such as 32 6 of Fig. 9, for mechanical robustness.
  • a pair of conducting pads, 18, are in electrical connection with vias, 14, which are in electrical contact with a trace, 146.
  • a conducting pad is in electrical contact with an external termination, 32 5 , and a conducting pad is in electrical contact with a circuit trace, 38 2 .
  • FIG. 10 and 1 1 wherein a high density multi-component package horizontally mounted to a circuit board, 36, is illustrated in schematic top view.
  • each external termination, 32 is attached to a trace of the circuit board with external terminations 32 1 and 32 8 attached to active traces 38 1 and 38 2 , respectively, which are in electrical contact with the circuit traces, 46, and the remaining external terminations are attached to mechanical pads, 40, preferably through a solder pad, 43, by an interconnect which is not shown.
  • the electronic components are all serially connected.
  • Fig. 10 and 1 1 the electronic components are all serially connected.
  • the HTIA, 31 1 is optional as the electronic components are mechanically secured to the circuit board.
  • the HTIA is still preferable as it provides mechanical stability and thus allows for the manufacture of a stack of electronic components prior to and independent of the board mounting process. This also facilitates part testing prior to board assembly.
  • FIG. 12 An embodiment of the invention will be described with reference to Figs. 12 and 13 wherein a high density multi-component package is illustrated in schematic top view as mounted to a substrate, 36.
  • electronic components 1 and 4 are mounted as illustrated and described relative to Figs. 10 and 11 .
  • Electronic components 1 and 4 are mounted as illustrated and described relative to Figs. 10 and 11 .
  • components 2 and 3 have an interconnect, 34, or HTCA, 310, forming an electrical connection directly there between and therefore the electronic components 2 and 3 are in electrical parallel.
  • a generic electrical schematic diagram is illustrated in Fig. 14 wherein electronic components 2 and 3 are in electrical parallel between serially connected electronic components 1 and 4.
  • An electrical schematic diagram is provided in Fig. 15 wherein electrical component 1 is an inductor, electrical components 2 and 3 are MLCC's and electrical component 4 is a fuse thereby providing a fused inductor capacitor high density component.
  • FIG. 9A the interposer comprises mechanical pads, 20, which are not in electrical contact with a mechanical pad opposite thereto on the substrate, 16.
  • the mechanical pads, 20, are electrically isolated portions of a trace on the surface of the substrate, 16.
  • the interposers illustrated in Figs. 9A and 9B do not have an active pad, as will be realized from further discussion, and will be referred to herein as a mechanical interposer.
  • FIG. 17 An embodiment of the invention will be described with reference to Figs. 17, 18, 19 and 20 wherein a portion of an electronic circuit of a device is illustrated in top schematic view in Figs. 17 and 19 and side schematic view in Figs. 18 and 20.
  • a series of pads, 58 are numbered sequentially.
  • Traces, 54, connecting adjacent pads are designated by the pads being electrically connected.
  • Traces are electrical paths which may include pad for connectivity.
  • Trace 54 23 for example, provides electrical conductivity between pads 58 2 and 58 3 .
  • Mechanical interposers, 50, or HTIA, 31 1 are between adjacent electronic components wherein pads 58 1 and 58 8 provide connectivity to the circuit by traces, 56.
  • a secondary electrical component, 5, electrically mounted in parallel with electrical components 2 and 3 at the external termination provides a combination of serial and parallel electrical connections and component 5 does not increase the surface area of the circuit board, 36, occupied by the package, 11 1 .
  • a secondary electrical component is an electrical component which is peripheral to the stack but electrically connected thereto. While demonstrated with five electrical components the number and arrangement of electrical components is not limited herein.
  • FIG. 21 A representative circuit diagram for the package illustrated in Figs. 17, 18, 19 and 20 is provided in Fig. 21 wherein electronic components 1 , 2, 3 and 4 are
  • FIG. 22 An exemplary embodiment is illustrated in Fig. 22 wherein electronic component 1 is an inductor, electronic components 2 and 3 are MLCC's, electronic component 5 is a resistor and electronic component 4 is a fuse.
  • FIG. 23 and 24 An embodiment of the invention will be described with reference to Figs. 23 and 24 wherein a high density multi-component package mounted to a substrate, 36, is illustrated in partial cross-sectional schematic view.
  • the electronic components are in parallel adjacent stacks with a secondary electronic component, P, spanning across electronic components N and M.
  • Electronic component P may be an additional electronic component providing functionality between those components being bridged or electronic component P can provide electrical conductivity as would be provided by an electrical jumper, conductive wire or conductive foil.
  • electronic component P could be an interposer or a flexible circuit with two active pads and a trace there between for electrical connectivity between the active pads.
  • pads, 62 are active pads in electrical communication with circuit traces, not shown, and pads, 60, are mechanical pads which are not otherwise electrically connected to the circuit.
  • An over-molding, 64 may be included to prevent surface arcing, to create a barrier to moisture penetration or to facilitate mechanical placement.
  • Pi, T, and LC filters are widely used in either feed through or surface mount configurations but there is a desire to continue to miniaturize these packages and provide a high density surface mountable solution.
  • An example of a Pi- filter package is shown in Figs. 25 and 26 wherein electronic component 2 is an inductor and electronic components 1 and 3 are MLCC's. The input and output of the inductor is connected through an MLCC to ground traces, 51 , thereby providing a Pi filter with an electrical schematic diagram illustrated in Figure 27. Only the active circuit traces are shown in Figs. 25 and 26 and other non-active pads may be added for a mechanical bond for increased mechanical stability.
  • An electronic schematic diagram for a "LC" filter is illustrated in Fig. 28 and an "T" filter is illustrated in Fig. 29.
  • an active interposer, 70 with a reorientation via can be used as shown in Fig. 30 wherein a conducting pad, 18, is electrically connected by a via, 14, to a conducting pad, 72.
  • a conducting pad, 18, is electrically connected by a via, 14, to a conducting pad, 72.
  • one of the faced down terminals is connected to the circuit and the other to one terminal of the next component, 76, by connection to the re-orientation via to form a serial connection.
  • Each pad, 74 independently represents either mechanical pads or conducting pads as necessary thereby allowing for flexibility in the design of the electronic components and the functionality of the high density multi-component package.
  • FIG. 33 and 34 An embodiment of the invention will be described with reference to Figs. 33 and 34.
  • a multiplicity of components, 1 -8 are illustrated with adjacent components in one plane, 1 and 2 or 3 and 4 or 5 and 6 or 7 and 8 for example, are serially connected through common electrical attachment using
  • mechanical pads, 20, or HTCA, 310 The mechanical connection to adjacent parallel electronic components, such as 2 and 3, are provided by the mechanical pads, 20, or by HTIA, 31 1 . Adjacent components are in electrical contact across the active interposer, 10, by active pads, 18, connected across the interposer by a via, 14, or by HTCA, 310. By providing multiple pads and combinations of active pads, mechanical pads, HTCA or HTIA multiple arrangements of components can be provided in a limited space.
  • a multiplicity of interposers provides the flexibility to form serial and parallel electrical connections.
  • Intrastack interposers, 210 which can independently be active interposers or mechanical interposers, between components in a stack allow for serial electrical connectivity as discussed herein.
  • An interstack interposer, 21 1 which is preferably an active interposer, provides electrical conductivity between adjacent stacks, Si and S2 of components wherein for the purposes of illustration stack Si comprises components 1 , 2 and 3 and stack S2 comprises components 4, 5 and 6.
  • interstack interposer has active pads, 18, in electrical contact by vias, 14, between adjacent components 3 and 6 and adjacent components 2 and 5 thereby providing a package with two groups of components 2-5 and 3-6 in electrical series with each set in electrical series with component 1 and 4 as
  • Fig. 36 the package is in electrical contact with active circuit traces, 38, on a circuit board, 36, with mechanical pads, 40, provided for mechanical support.
  • a mechanical pad, 40 1 for example, may be an active circuit thereby allowing for the use of a portion of the stack, only component 1 for example, with the functionality of component 1 , in this illustration, be isolated between traces 38 1 and 40 1 .
  • Figs. 35 and 36 allow for testing of individual components within the package.
  • a combination of HTCA, 310, and HTIA, 31 1 provides the flexibility to form serial and parallel electrical connections.
  • Inter-stack HTCA, 310 provides electrical conductivity between adjacent stacks, Si and S2 of components wherein, for the purposes of illustration, stack Si comprises components 1 , 2 and 3 and stack S2 comprises components 4, 5 and 6. For the purposes of illustration adjacent
  • components 3 and 6 and adjacent components 2 and 5 provide a package with two groups of components 2-5 and 3-6 in electrical series with each set in electrical series with component 1 and 4 as represented schematically in Fig. 37.
  • the package is in electrical contact with active circuit traces, 38, on a circuit board, 36, with
  • a mechanical pad, 40 1 may be an active circuit thereby allowing for the use of a portion of the stack, only component 1 for example, with the functionality of component 1 , in this illustration, to be isolated between traces 38 1 and 40 1 . This allows for testing of individual components within the package.
  • Fig. 38 active interposers are between adjacent components and with each external termination of each component in electrical contact with a circuit trace.
  • a package is provided which allows multi-terminal components to be connected to the circuit through the use of HTCA, 310, and HTIA, 311 .
  • Fig. 40 three components are illustrated, without limit thereto, with HTCA between adjacent components and with each external termination of each component in electrical contact with a circuit trace.
  • some circuit traces, 151 can be active and some can be mechanical.
  • traces 151 A , 151 c and 151 B can be utilized to provide the schematic of Fig. 41 which could provide the T-filter of Fig.
  • traces 151 A, 151 B and 151 E could be utilized to provide the schematic of Fig. 42 which could provide the LC, or L filter of Fig. 28 when component 1 is an inductor and component 2 is a capacitor.
  • circuit traces 151 A, 151 B, 151 C and 151 F could be utilized to provide the schematic of Fig. 43 which could provide the Pi filter of Fig. 27 if components 1 and 3 are capacitors and component 2 is an inductor.
  • a single package can provide multiple functions. It would be understood that the number of components can be quite large and therefore the functionality can be essentially limitless.
  • a functional interposer, 200 is illustrated in schematic cross-sectional view wherein the functional interposer comprises functional pads, 300, with at least one component, 1 , in electrical contact and between the functional pads.
  • Conductive pads, 302, in electrical contact by a trace, 304, provide electrical connectivity to additional components, 2-4, without limit to the number.
  • a functional pad and a conductive pad are each in electrical contact with active traces, 38.
  • the package may be encased in an overmolding, 64.
  • FIG. 45 An embodiment of the invention is illustrated in schematic cross-sectional view in Fig. 45.
  • two electronic components are illustrated with the understanding that the two electronic components could be a portion of a stack of electronic components.
  • external terminations 32 1 and 32 2 are in electrical contact through a HTCA, 310, as described elsewhere herein.
  • External terminations 32 3 and 32 4 are not in electrical contact having instead a spacer, 9, there between wherein the spacer can be an air gap or a non-conductive material wherein the non- conductive material may be an HTIA.
  • a secondary adhesive, 112 which is preferably not conductive, adheres the body of the adjacent electronic components for stability purposes. The adhesive may be in contact with one external termination of one electronic component and the body of the adjacent electronic component.
  • a secondary adhesive is an adhesive which is in mechanical contact with at least one body of at least one electronic component and may otherwise be in mechanical contact with a body of a second electronic component, an external termination of a second electronic component or a solder pad.
  • FIG. 46 An embodiment of the invention is illustrated in schematic side view in Fig. 46 wherein two stacks of electronic components, represented by 1 -8 without limit thereto, is illustrated mounted vertically to a substrate, 36.
  • a spacer, 17, is provided which functions as an insulator between adjacent external terminations of adjacent electronic components.
  • a stack as represented in Fig. 46 could be mounted horizontally, as in Fig. 1 1 , and alternate arrangements of HTCA, 310, HTIA, 311 , and spacers, 17 could be employed thereby allowing for combinations of serial and parallel electrical connections as set forth elsewhere herein.
  • FIG. 47 An embodiment of the invention is illustrated in schematic side view in Fig. 47.
  • a HTIA, 311 is between adjacent electronic components thereby allowing for serial connectivity of the stacked electronic component.
  • Adjacent external terminations are in electrical connection by HTCA's, 310, as described elsewhere herein.
  • a stack as represented in Fig. 47 could be mounted horizontally, as in Fig. 35, and alternate arrangements of HTCA and HTIA could be employed, with the further inclusion of spacers, thereby allowing for combinations of serial and parallel electrical connections as set forth elsewhere herein.
  • FIG. 48 and 48A An embodiment of the invention is illustrated schematically in Figs. 48 and 48A represented as a Pi filter, for the purposes of discussion, suitable for filtering out unwanted electrical interference.
  • a pair of electronic components, 1 and 2, preferably capacitors, are serially connected through an inductor comprising a conductor, 19, with at least one layer of an inductive material, 31 , and an optional electrical insulating material, 10. More preferably the conductor has an inductive material on each side.
  • Interconnects, 12, which can be a portion of an active interposer provides electrical conductivity to the electronic components.
  • the optional electrically insulating material which can be an interposer, preferably forms the outer layer of the inductor.
  • the inductive material is a metal flake composite material.
  • Particularly preferred inductive material comprise alloys of at least one of iron, aluminum and silicon preferably in the form of flakes.
  • the inductor can be formed as a sandwich of a conductive foil, or wire lead, forming an electrically connective path within or around the inductive material.
  • FIG. 50 An embodiment of the inductor is shown in partial cross-sectional view in Fig. 50 wherein the inductive material, 31 , is sandwiched between conductors, 19. Electrical connectivity to the adjacent conductors can be by the use of vias, 12.
  • An alternative embodiment of an inductor is illustrated in partial cross-sectional view in Fig. 51 wherein adjacent layers of inductive material are offset thereby allowing for electrical
  • the number of layers of inductive material and conductor is not particularly limited and the thickness of each layer of inductive material and conductor may be adjusted to obtain the required inductive performance.
  • FIG. 49 An alternate embodiment of a pi filter with electromagnetic interference suppressor is illustrated in schematic cross-sectional view in Fig. 49 wherein the inductor comprises offset layers as illustrated in Fig. 51.
  • a particular advantage of the instant invention is an improvement in inductance.
  • a high density multi-component stack mounting in a horizontal direction reduces stray inductance as the path length between the electronic component and circuit board is reduced, and therefore so is the Equivalent Series Inductance (ESL).
  • ESL Equivalent Series Inductance
  • An ESL of 0.9 nH in the vertical direction can be achieved compared to 2.9 nH in the horizontal direction.
  • the Equivalent Series Resistance (ESR) can also be lowered which is particularly important since it is directly proportional to the power dissipated when AC voltage is applied. This is particularly advantageous with MLCC because in the horizontal orientation of the electronic components the interior electrodes of the MLCC are vertical which is advantageous for inductance and the resistive length is lowered reducing ESR.
  • Each electronic component is preferably independently selected from the group consisting of jumper, wire, capacitor, resistor, varistor, inductor, diode, fuse, overvoltage discharge device, sensor, switch, electrostatic discharge suppressor, electromagnetic interference suppressor, semiconductor and integrated circuit.
  • the diode may be a light emitting diode.
  • the electronic elements are selected from the group consisting of capacitor, resistor, varistor, inductor, diode, fuse, overvoltage discharge device, sensor, switch, wire, jumper, electromagnetic
  • the capacitor is an MLCC and more preferably at least one of the electronic components is an MLCC.
  • a particularly preferred electromagnetic interference suppressor comprises a magnetic powder, preferably a soft magnetic powder which is annealed. Flaked magnetic particles are preferred with alloys comprising at least one of iron, aluminum and silicon being particularly suitable for demonstration of the invention.
  • the external terminations of the electronic components are not particularly limited herein with the proviso that they can be attached to a pad, either active or mechanical, by an HTCA or HTIA or by an interconnect such as solder, conductive adhesive, polymer solder, TLPS bond, sintered metal interconnects, diffusion solders or direct copper bonds.
  • TLPS is the preferred interconnect between the external termination of the electronic component and pad.
  • the external termination may be one component of TLPS, as will be more fully described herein, wherein additional components of the TLPS are either inserted between the external termination to be bound or is integral to the surface to which the external termination is to be bound.
  • the TLPS materials are compatible with surface finishes containing silver, tin, gold, copper, platinum, palladium, nickel, or combinations thereof, either as lead frame finishes, component connections or inner electrodes to form an electronically conductive metallurgical bond between two surfaces.
  • Transient liquid phase sintering (TLPS) adhesives form a termination to an electronic element or attach external terminations to a surface such as a solder pad or adjacent external termination thereby functioning as an interconnect.
  • TLPS Transient liquid phase sintering
  • terminations have the advantage of being able to accommodate different surface finishes as well as electronic elements of differing lengths. Furthermore, since no solder balls are formed electronic elements can be stacked on top of each other with only TLPS there between and without the gaps normally required for cleaning as with solder attachment technology. TLPS can be directly bonded with the inner electrodes of the electronic component, when the electronic element is an MLCC, and the termination can be formed at low temperature. In an embodiment, higher density terminations can be prepared by using a thermo-compression process thereby forming improved external lead attachment bonds.
  • Solders are alloys which do not undergo a change in composition after the first reflow. Solders have only one melting point and can be remelted an indefinite number of times. The most common solder is 60%Sn40%Pb. Solders have been the materials of choice in electronics to provide the mechanical and electrical interconnects between electronic elements and circuit boards or substrates. Solders are very well suited for mass volume production assembly processes. The physical properties of solder can be altered simply by changing the ratios or the metals used to create a solder alloy. When solder is referenced herein it will imply an alloy of at least two metals that can be remelted multiple times at nearly the same temperature.
  • Transient liquid phase sintering (TLPS) bonds are distinguishable from solders.
  • TLPS materials are mixtures of two or more metals or metal alloys prior to exposure to elevated temperatures thereby distinguishing the thermal history of the material.
  • TLPS materials exhibit a low melting point prior to exposure to elevated temperatures, and a higher melting point following exposure to these temperatures.
  • the initial melting point is the result of the low temperature metal or an alloy of two low temperature metals.
  • the second melting temperature is that of the intermetallic formed when the low temperature metal or alloy forms a new alloy with a high temperature melting point metal thereby creating an intermetallic having a higher melting point.
  • TLPS materials form a metallurgical bond between the metal surfaces to be joined. Unlike tin/lead or lead (Pb) free solders, the TLPS adhesives do not spread as they form the intermetallic joint.
  • Transient Liquid Phase Sintering is the terminology given to a process to describe the resulting metallurgical condition when two or more TLPS compatible materials are brought in contact with one another and raised to a
  • At least one of those metals is from a family of metals having a low melting point, such as tin (Sn) or indium (In), and the second metal is from a family having high melting points, such as copper (Cu) or silver (Ag).
  • Sn and Cu are brought together, and the temperature elevated, the Sn and Cu form CuSn intermetallics and the resulting melting point is higher than the melting point of the metal having a low melting point.
  • In and Ag when sufficient heat is applied to the In to cause it to melt it actually diffuses into the Ag creating a solid solution which in turn has a higher melting point than the In itself.
  • TLPS will be used to generically reference the process and the TLPS compatible materials used to create a metallurgical bond between two or more TLPS compatible metals.
  • TLPS provides an electrical and mechanical interconnect that can be formed at a relatively low temperature ( ⁇ 300°C) and having a secondary re-melt temperature >600°C. These temperatures are determined by the different combination of TLPS compatible metals.
  • the rate of diffusion or sintering is a time temperature function and is different for the different combinations of metals. The result is a solid solution having a new melt temperature approaching that of the high temperature melting metal.
  • the TLPS technology is particularly suited to providing both a mechanical and electrical conductive metallurgical bond between two mating surfaces preferably that are relatively flat.
  • the metals typically used for the TLPS process are selected from two metal families. One consists of low melting temperature metals such as indium, tin, lead, antimony, bismuth, cadmium, zinc, gallium, tellurium, mercury, thallium, selenium, or polonium and a second family consist of high temperature melting metals such as silver, copper, aluminum, gold, platinum, palladium, beryllium, rhodium, nickel, cobalt, iron and molybdenum to create a diffused solid solution.
  • low melting temperature metals such as indium, tin, lead, antimony, bismuth, cadmium, zinc, gallium, tellurium, mercury, thallium, selenium, or polonium
  • a second family consist of high temperature melting metals such as silver, copper, aluminum, gold, platinum,
  • TLPS is a sintering based process
  • the bond line is uniform and void free. Fluxes, which are necessary with solders, get entrapped in the joint and are subsequently burned out leaving a void.
  • these voids can create hot spots within the integrated circuit (l/C) which can lead to premature failure and reliability issues.
  • TLPS addresses this issue since TLPS is a sintering process and free of fluxes. When the two metals are mated together and heat is applied, the lower melting metal diffuses into the higher melting metal to create a solid solution across the mating surface area.
  • TLPS in paste form allows uneven surfaces to be joined. More specifically, the use of TLPS in paste form allows two irregular shaped surfaces to be joined with no intimate, or continuous, line of contact.
  • a TLPS compatible metal particle core combined with a liquid carrier material to form a paste can be applied between two non- planar non-uniform surfaces having mixed surface preparation technologies such as plating, sintered thick film, and or plated sintered thick film and then heating to the melting temperature of the metal having the lowest melting point and holding that temperature for a sufficient amount of time to form a joint.
  • a single metal particle core eliminates the need for multiple metals in a paste thus making the ratios of metals a non-issue. It is also possible to create a single particle by using silver, a metal having a high melting point of approximately 960°C as a core particle, and then coating that particle with a metal shell having a low temperature metal such as indium having a melting point of 157°C.
  • a two-step reflow can also be used with the transient liquid phase sintering process wherein in the first step an electrically conductive metallurgical bond is formed at low temperature using a relatively short time cycle, in the range of 5 seconds to 5 minutes, and low temperature, in the range of 180°C to 280°C, depending on the metals being used in the TLPS alloying process.
  • the part is subjected to an isothermal aging process using a temperature range of 200°C to 300°C for a longer duration such as, but not limited to, 5 minutes to 60 minutes. The shorter times required to form the initial bond are well suited for an automated process.
  • a single step process can be used wherein the TLPS forms a terminal, or conductive metallurgical bond, between the external leads and electronic element(s) at
  • temperatures of, for example, 250°C to 325°C for a duration of, for example, 10 seconds to 30 seconds.
  • Lower temperatures, such as 175°C to 210°C, can be used for a longer duration, such as 10 to 30 minutes. This is particularly useful when the electronic component itself is sensitive to temperature.
  • Indium powder mixed with a flux and solvent to form a paste can be applied to produce a TLPS metallurgical bond between two coupons having a base metal of copper overplated with Ni and then overplated with about 5 microns (200 ⁇ inches) of silver.
  • the samples can be prepared by dispensing the indium paste onto a coupon having the plated surfaces as mentioned and then placing two coupons in contact with one another and heating to 150°C for 5 seconds, followed by increasing the
  • the joint strength of the sample thus prepared can exhibit a pull weight in the range of 85-94 pounds equating to shear stress of 4, 177 psi and a pull peel weight in the range of 5-9 pounds with an average of 7 pounds can be achieved. These results are comparable to results for SnPb solders having shear strengths of approximately 3000 psi and pull peel strengths in the 7-10 pound range.
  • One major difference is that the Agin joint can withstand secondary melt temperatures exceeding 600°C.
  • the TLPS paste or preform may have inert fillers therein to serve two purposes.
  • One purpose is to minimize the cost due to expensive metals and the second purpose is to make direct electrical and metallurgical bonds directly to the non-terminated ends of the electronic element and exposed internal electrodes.
  • the cost can be reduced, particularly, when a gap is to be filled by replacing a portion of, particularly, the high melting metal component with an inert material or with a lower cost conductive material.
  • Particularly preferred fillers for use in place of the high melting point metal are non- metals such as ceramics with melting points > 300°C and glasses or high temperature polymers with glass transition temperatures (T g ) > 200°C.
  • An example would be thermosetting polymers such as polyimide.
  • the active low melting point metal of the TLPS with not be consumed by diffusion during the TLPS bond formation.
  • the second advantage of inert fillers when selected from a family of glasses having low melting points is that the glass within the mixture of the TLPS paste or preform will create a bond with the exposed glass frit of the non-terminated and exposed ceramic body of, for example, an MLCC.
  • the non-metals can also be coated with the low melting point metal by methods such a spraying or plating.
  • Sintered metal interconnects of silver as well as nano-silver and nano-copper can also be used to form interconnects.
  • the resulting interconnect can be formed using a low temperature sintering process but the bond formed has the high melting point associated with the metal, in the case of silver 960°C.
  • these processes often require elevated pressures for prolonged times in batch operation that can limit throughput compared to CuSn TLPS.
  • nano-sized metals can be prohibitively expensive.
  • Diffusion soldering can also be used as a joining method to form the interconnect. This combines features of conventional soldering and diffusion bonding processes. The process relies on reaction between a thin layer of molten solder and metal on the components to form one or more intermetallic phases that are solid at the joining temperature. Since a low melting point material, such as solder, reacts with a higher melting point metal this may also be considered in the broader definition of TLPS.
  • Direct copper bonding can also be used but this is a high temperature diffusion process primarily used in die attach so it could be detrimental to some components.
  • Methods to adhere an external termination to a solder pad can comprise coating two mating surfaces one with a high melting point metal and its mating surface with a low melting point metal.
  • the coating process may consist of vapor deposition or plating.
  • a second method is to sandwich a preform film made from a low melting point metal or an alloy of two or more low melting point metals between two planar surfaces coated with a high melting point metal.
  • a third method is to create a paste consisting of particles of a high melting point metal such as copper and then adding particles of two alloyed low melting point metals and mixed into a dual purpose liquid that cleans the surfaces to be bonded and serves as the liquid ingredient to the metal particles to form a paste mixture.
  • the joint can be subjected to a second heating process.
  • the joint, or assembly can be subjected to a temperature higher than that of the low melting point material and held for a period of time from 15 minutes up to 2 hours. The time and temperature can be varied to provide a desirable secondary reflow temperature as dictated by secondary assembly
  • indium/silver TLPS secondary melt temperatures in excess of 600°C can be achieved.
  • the preform can be a thin foil of the low temperature TLPS component.
  • the preform can be produced by casting and drying the paste to remove the solvent. The resulting solid preform can be placed between the surfaces to be bonded. In this case it may be necessary to add a suitable binder to the paste for additional strength after drying. In all these cases the preform should be malleable such that it can conform to the surfaces to be bonded.
  • a preferred embodiment of this invention is therefore to form a low porosity termination within the transient liquid phase sintering joint using a thermo-compression bonding process.
  • This process has the added advantage of using a low process time of 15 to 30 seconds at a temperature in the range of 225°C to 300°C in a single step making it suitable for automation.
  • Robust joints can be created for the application of attaching external leads to electronic elements, when leads are used, with a one-step low temperature in less than 30 seconds and in combination with thermo-compression bonding.
  • Thermo compression bonding is also a preferred processing method when using polymer solder because it assists in the formation of a high density metallurgical bond between the contacting surfaces.
  • the advantages of thermo-compression include a more robust bond with respect to secondary attachment processes and attachments with higher strength are achieved.
  • a compressive force of 0.5 to 4.5 Kilograms/cm 2 (7.1 to 64 psi) and more preferably 0.6 to 0.8 Kilograms/cm 2 (8.5 to 1 1 psi) is sufficient for demonstration of the thermo-compression teachings herein. About 0.63
  • Kilograms/cm2 (9 psi) is a particularly suitable pressure for demonstration of the teachings.
  • An HTCA can be an interconnect comprising a single metal, such as indium, contained within a paste which can be used to form a bond to a surface coated with a high melting point metal, such as silver.
  • a high melting point metal such as silver.
  • the diffusion of the indium into silver allows a lower temperature transient liquid phase to form that subsequently reacts to achieve a higher temperature bond.
  • Achieving a high rate of diffusion in the lower melting point paste is critical to this bond formation.
  • the addition of other metals to the paste may be desirable.
  • Coatings also have the desired effect of reducing the diffusion lengths between the different metallic elements of the paste allowing preferred phases to be more readily formed as opposed to a simple mixing of one or more additional metal powders to the single metal paste.
  • Conductive adhesives as HTCA's are typically cross linking polymers filled with silver or gold particles that cure or cross link within a specified temperature range, generally 150°C, to form a mechanical bond to the materials to be joined. Their conductivity is created by the metal particles making intimate contact with one another, within the confines of the polymer matrix, to form an electrically conductive path from one particle to another. Because the binder is organic in nature, they have relatively low temperature capabilities, normally in the range of about 150°C to about 300°C.
  • Conductive epoxies once cured, cannot be reworked. Unlike TLPS bonds, exposure to high heat or corrosive environments may decompose the polymeric bonds and oxidize the metal particles degrading the electrical properties. Both the electrical and mechanical performance of the interconnect can be compromised resulting in increased ESR and decreased mechanical strength.
  • Polymer solders HTCA's may comprise conventional solder systems based on Pb/Sn alloy systems or lead free systems, such as Sn/Sb, which are combined with crosslinking polymers which serve as cleaning agents.
  • the cross-linked polymers also have the ability to form a cross-linked polymer bond, such as an epoxy bond, that forms during the melting phase of the metals thereby forming a solder alloy and a mechanical polymeric bond.
  • An advantage of polymer solders is that the polymeric bond provides additional mechanical bond strength at temperatures above the melting point of the solder, thus giving the solder joint a higher operating temperature in the range of about 5 to 80°C above the melting point of the solder.
  • Polymer solders combine current solder alloys with a cross linking polymer within the same paste to provide both a metallurgical bond and a mechanical bond when cured, such as by heating, to provide additional solder joint strength at elevated temperatures.
  • the upper temperature limits and joint strength has been increased, just by the physical properties of the materials. A practical limit of 300°C remains whereas the bonds created by TLPS can achieve higher temperatures.
  • High temperature insulating adhesives can be a thermal or moisture set adhesives, UV cure adhesives or pressure sensitive adhesives.
  • Particularly preferred high temperature insulating adhesives include epoxy resins, phenolic formaldehyde resins, phenolic melamine formaldehyde resins, phenolic neoprene, resorcinol formaldehydes, polyesters, polyimides, cyanoacrylates, acrylics, styrene block copolymers, styrene butadiene copolymers, polyurethanes, polyarylenes, polysulfides, polyamides, silicones and waxes etc.
  • the HTIA may be selected to form a bond at the same time as the HTCA or in some circumstances, it may be preferable to provide a separate bonding process.
  • the HTIA bonding processes may be achieved by pressure, heating, UV curing, moisture curing or hot melt deposition. Additionally, the HTIA may contain inert fillers of sufficient size and dielectric properties to ensure minimal dielectric spacing between adjacent components as required by the circuit / stack design and service conditions.
  • the material of construction for the interposer is not particularly limited herein with standard printed circuit board (PCB) materials being suitable for use. Laminates, fiber reinforced resins, ceramic filled resins, specialty materials and flexible substrates are particularly suitable. Flame Retardant (FR) laminates are particularly suitable as an interposer material and especially FR-1 , FR-2, FR-3, FR-4, FR-5 or FR-6.
  • FR-2 is a phenolic paper, phenolic cotton paper or paper impregnated with phenol formaldehyde resin.
  • FR-4 is particularly preferred which is a woven fiberglass cloth impregnated with epoxy resin.
  • Composite epoxy materials are suitable and particularly CEM-1 , CEM-2, CEM-3, CEM-4 or CEM-5 each of which comprise reinforcement such as a cotton paper, non-woven glass or woven glass in epoxy.
  • Glass substrates are widely used such as G-5, G-7, G-9, G-10, G-11 and others with G-10 and G-1 1 being most preferred each of which is a woven glass in epoxy.
  • Polytetrafluoroethylene polytetrafluoroethylene
  • PTFE which can be ceramic filled, or fiberglass reinforced such as in RF-35, is a particularly suitable substrate.
  • Electronic grade ceramic materials such as polyether ether ketone (PEEK), alumina or yttria stabilized zirconia are available with 96% AI2O3 and 99.6% AI2O3 being readily available commercially.
  • BismaSeimide-Triazine (BT) epoxy is a particularly suitable substrate material Flexible substrates are typically a poiyimide such as a polyimide foil available commercially as Kapton or UPILEX or a polyimide-fluoropolymer composite commercially available as Pyralux. Ferrous alloys are also used such as Alloy 42, Invar, Kovar or non-ferrous materials such as Cu, Phosphor Bronze or BeCu.
  • the package, or portions of the package can be over-molded by a non- conductive polymer or resin.
  • the material used for overmolding is not particularly limited herein. Overmolding can be done to isolate the package, or components therein, from electrical interaction with other elements of a circuit or to protect the package, or components therein, from environmental variations. Overmolding can also be beneficial for labeling and for use with pick-and-place equipment since the over- molding can be applied with specific geometry identifiable by optical or mechanical equipment. Additionally, the package can be mechanically encapsulated in a case, shell or other assembly for use as a plug in electrical circuit or assembly utilizing commercially available electrical connections attached to the package via extant assembly methodologies.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Adhesives Or Adhesive Processes (AREA)
  • Powder Metallurgy (AREA)

Abstract

L'invention concerne un boîtier multi-composants de haute densité amélioré. Le boîtier comprend au moins deux composants électroniques. Chaque composant électronique comprend une première terminaison externe et une seconde terminaison externe. Au moins une connexion électrique se trouve entre des premières terminaisons externes adjacentes de composants électroniques adjacents. Au moins une liaison mécanique se trouve entre des composants électroniques adjacents. Au moins deux composants électroniques adjacents sont connectés en série.
EP18853638.7A 2017-09-08 2018-09-10 Boîtiers multi-composants de haute densité en série Pending EP3679599A4 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US15/699,654 US10681814B2 (en) 2017-09-08 2017-09-08 High density multi-component packages
US15/804,515 US10707145B2 (en) 2017-09-08 2017-11-06 High density multi-component packages
US15/852,799 US10178770B1 (en) 2017-12-22 2017-12-22 Higher density multi-component and serial packages
PCT/US2018/050142 WO2019051346A1 (fr) 2017-09-08 2018-09-10 Boîtiers multi-composants de haute densité en série

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EP3679599A1 true EP3679599A1 (fr) 2020-07-15
EP3679599A4 EP3679599A4 (fr) 2021-05-26

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Publication number Priority date Publication date Assignee Title
CN116097382A (zh) * 2020-09-10 2023-05-09 基美电子公司 谐振多层陶瓷电容器
KR20220078887A (ko) 2020-12-04 2022-06-13 삼성전기주식회사 전자 부품

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002280862A (ja) * 2001-03-19 2002-09-27 Murata Mfg Co Ltd 複合型ｌｃフィルタ回路及び複合型ｌｃフィルタ部品
JP2005216884A (ja) * 2004-01-27 2005-08-11 Matsushita Electric Ind Co Ltd 回路基板およびチップ部品実装方法
CN101467500B (zh) * 2006-06-27 2012-08-08 松下电器产业株式会社 中继基板以及电路安装结构体
US9472342B2 (en) 2010-05-26 2016-10-18 Kemet Electronics Corporation Leadless multi-layered ceramic capacitor stacks
US10366836B2 (en) * 2010-05-26 2019-07-30 Kemet Electronics Corporation Electronic component structures with reduced microphonic noise
JP2012248812A (ja) * 2011-05-31 2012-12-13 Sumitomo Electric Ind Ltd 半導体光集積素子の製造方法
US9171672B2 (en) * 2011-06-27 2015-10-27 Kemet Electronics Corporation Stacked leaded array
US8767408B2 (en) * 2012-02-08 2014-07-01 Apple Inc. Three dimensional passive multi-component structures
US9357634B2 (en) * 2012-04-27 2016-05-31 Kemet Electronics Corporation Coefficient of thermal expansion compensating compliant component
DE102013215149A1 (de) 2013-08-01 2015-02-19 Conti Temic Microelectronic Gmbh Mehrstufiges Dichtsystem zum Einsatz in einem Kraftfahrzeugsteuergerät
KR101607020B1 (ko) * 2014-10-23 2016-04-11 삼성전기주식회사 적층 세라믹 전자 부품 및 그 실장 기판
KR102139763B1 (ko) * 2015-01-08 2020-07-31 삼성전기주식회사 적층 세라믹 전자 부품 및 그 실장 기판
JP6358132B2 (ja) * 2015-03-03 2018-07-18 オムロン株式会社 立体回路構造体
JP6520398B2 (ja) * 2015-05-27 2019-05-29 Tdk株式会社 電子部品
US9867285B2 (en) * 2015-06-09 2018-01-09 Apple Inc. Printed circuit board components
KR102184562B1 (ko) * 2015-10-01 2020-12-01 삼성전기주식회사 복합 전자부품 및 그 실장 기판
JP6547569B2 (ja) * 2015-10-08 2019-07-24 Tdk株式会社 電子部品
CN205542769U (zh) * 2015-11-30 2016-08-31 奥特斯(中国)有限公司 电子装置和电子设备
US10224149B2 (en) * 2015-12-09 2019-03-05 Kemet Electronics Corporation Bulk MLCC capacitor module

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Publication number Publication date
EP3679599A4 (fr) 2021-05-26
JP7121797B2 (ja) 2022-08-18
JP2020534675A (ja) 2020-11-26
CN111052347B (zh) 2024-03-01
WO2019051346A1 (fr) 2019-03-14
CN111052347A (zh) 2020-04-21

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