Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
  • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
  • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
  • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
  • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
  • H01L21/30604—Chemical etching
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
  • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
  • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
  • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
  • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
  • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
  • H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
  • H01L21/465—Chemical or electrical treatment, e.g. electrolytic etching
  • H01L21/467—Chemical or electrical treatment, e.g. electrolytic etching using masks
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02107—Forming insulating materials on a substrate
  • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
  • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
  • H01L21/02247—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by nitridation, e.g. nitridation of the substrate
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02107—Forming insulating materials on a substrate
  • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
  • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
  • H01L21/02258—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by anodic treatment, e.g. anodic oxidation
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02107—Forming insulating materials on a substrate
  • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
  • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
  • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
  • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
  • H01L21/30604—Chemical etching
  • H01L21/30612—Etching of AIIIBV compounds

Definitions

• the present invention relates to the field of selective etchings of materials such as semiconductors (in particular III-V or II-VI), and in particular masks used to perform such etchings by etching.
• the technique of chemical etching masks still requires improvements, particularly in terms of the quality of protection of the mask covering the parts of the semiconductor to be protected, in terms of the fineness of the resulting etching, and others.
• the present invention improves this situation.
• the mask is made of a material comprising polyphosphazene.
• This material is particularly effective for the protection of the underlying materials, in particular semiconductors.
• the etching carried out at the second step of the above process can be carried out with very aggressive solutions and it has nevertheless been observed that, owing to the very effective protection of the mask, the etching remained particularly fine and perfectly defined, and therefore very localized in the unprotected area.
• the mask deposition comprises an electrochemically controlled deposition of the polyphosphazene.
• Mask deposition may include immersion in liquid ammonia followed by polyphosphazene deposition.
• the deposit can be simply without electrical assistance, according to a so-called “electroless” method.
• the process may then include the aforementioned immersion in liquid ammonia (possibly associated with dissolved phosphorus pentachloride or "PC15").
• the mask depot may further include:
• the pre-mask may be made of a material based on silicon oxynitride SiO x N y
• the removable pre-mask can be removed typically by immersion in solution of hydrogen fluoride.
• the polyphosphazene deposit can simply be beam etched to form the aforementioned mask covering the first zone.
• the beam may be an electron beam or a laser beam.
• the chemical etching of the semiconductor in regions not protected by the mask may be performed by applying an oxidizing etching solution (for example an "HBr" type solution described below).
• an oxidizing etching solution for example an "HBr" type solution described below.
• the present invention also relates to a protective mask of a semiconductor material vis-à-vis a etching etching, made of a material comprising polyphosphazene.
• this mask may then comprise a thickness of the order of a few nanometers only.
• Figure 1A schematically illustrates the deposition steps of a polyphosphazene mask in a first embodiment
• FIG. 1B schematically illustrates the deposition steps of the polyphosphazene mask in a second alternative embodiment
• FIG. 1C schematically illustrates the etching steps of the semiconductor partially covered by the polyphosphazene-based mask in one or the other of the aforementioned first and second embodiments;
• FIG. 2 shows the variations of the XPS (photoelectron spectroscopy for surface chemical analysis) signals for different atomic species, along a line comprising a succession of several masks covering an InP semiconductor in this example.
• XPS photoelectron spectroscopy for surface chemical analysis
• Polyphosphazene films have protective properties vis-à-vis the chemical reactivity of semiconductor material surfaces.
• Polyphosphazene is an inorganic polymer (without carbon atom) including in particular a specific skeleton made of phosphorus and nitrogen. It is described in particular in the document:
• the thicknesses obtained from polyphosphazene films are nanometric (for example between 2 and 10 nm) and it has been observed that such thicknesses are sufficient to ensure their protective function.
• the chemical inertia of the surfaces covered by this type of film is one of the first protective capabilities of the film, particularly with regard to the re-oxidation of the surfaces due to their interaction with the air (with oxygen , water vapor, or other).
• an InP type III-V alloy surface coated with a polyphosphazene film obtained by electroless was compared with an aqueous bromine solution (HBr / Br2), acidic or neutral.
• aqueous bromine solution HBr / Br2
• the aqueous solution triggers the dissolution of the InP semiconductor (n or p type, the polarization of the semiconductor having no influence).
• the dissolution is remarkable and rapid for the concentrations used (several micrometers per minute).
• the chemical stability of the semiconductor surfaces, covered with a polyphosphazene-based passivation obtained electrochemically or electrolessly, with respect to aqueous oxidizing solutions capable of generating significant dissolutions (one or more ⁇ / ⁇ ) on unprotected surfaces of the semiconductor by a conventional film (conventionally a silica film or more generally SiOx, or other) could be observed and is proposed here in an industrial application to the selective etching of semiconductors.
• the HBr acid or a bottom salt such as KBr is introduced into the etching solution in order to maintain the Br-/ Br 2 pair at a constant level by offering the possibility of testing different levels of pH.
• the etching capacity of the formulation remains constant over time at a level regulated by the concentration of Br 2 (or (Br 3) - in solution).
• the unprotected surfaces of the semiconductor undergo aggressive dissolution by oxidative etching, thus constant over time.
• the surfaces protected by the polyphosphazene film are perfectly free of dissolution. Indeed, it was carried out in solutions to detect traces or "ultra-traces" of indium and phosphorus dissolved in solution by "ICP-OES” (Inductively Plasma Coupled Optical Emission Spectrometry) with a threshold of detection approaching a few nm / cm 2 of dissolved surface. The tests on the totally protected surfaces were compared to those on bare surfaces, with the same chemical formulation and the same experimental conditions (hydrodynamics, temperature, etc.).
• ICP-OES Inductively Plasma Coupled Optical Emission Spectrometry
• the surface protection could be shown by XPS analysis of surfaces subjected to polyphosphazene film overlap treatment.
• XPS analysis photoelectron spectroscopy for surface chemical analysis gives an absolute chemical signature.
• the signal representative of a surface of InP covered with a polyphosphazene film (and a pre-mask) of the type presented in step S3 of FIG. 1A may consist of a combination characteristic signals specific to: nitrogen,
• the signals are perfectly complementary along the line comprising a succession of masks, all of these signals well reflecting the existence of a film covering a "buried" surface of InP which nevertheless remains visible. Thus, a film of nanometric thickness is present.
• the detection level of the matrix signal is a qualitative measurement tool for the thickness of the passivation film.
• the constancy of the XPS response over time has been observed and demonstrates a remarkable stability of the film in the presence of the aqueous oxidizing solution based on aqueous di-bromine, and this in agreement with the absence of detection of products of dissolution in solution on the protected samples on the entire immersed surface.
• the detection by XPS makes it possible to show in addition the total stability of the InP surface.
• the dissolved surface gives a very easily identifiable XPS signature with the growth of an oxide in a thin layer which gives contributions of phosphorus and especially of indium perfectly indexed.
• the analysis of surfaces protected by polyphosphazene shows a complete absence of such signals related to dissolution.
• the XPS analyzes thus give two proofs of the total absence of reactivity to the oxidizing solutions on the passivated surfaces. Surfaces coated with polyphosphazene are thus completely protected from chemical etching, making polyphosphazene a material of choice for use as a chemical mask.
• polyphosphazene has been found to be stable in acidic pH (HBr and / or H 2 SO 4 ), but also basic (in the case of ferricyanide etching for example), or neutral (in the presence of H 2 0 2 for example). It is therefore a material of choice for masks involved in etching processes (especially by any oxidizing solutions).
• polyphosphazene film as a chemical bond etching mask can be implemented in the context of microelectronics and / or optoelectronics involving localized masking to mirror localized etchings, localized passivations, resumption of contact or growth also localized. It has been shown above that a new family of polyphosphazene-based masking materials is compatible with such applications.
• areas of localized growth of polyphosphazene can be created by applying prior maskings of the semiconductor surfaces by deposition of, for example, silicon oxynitride SiO x N y units .
• a semiconductor surface SC (III-V or II-VI or other) to be treated, for example cleaned beforehand by chemical etching, deoxidizing, or other, is obtained. .
• step S1 PM pre-masks of SiOxNy can be deposited by selective zones according to techniques known per se for this type of masking material.
• These first level PM masks are compatible with liquid ammonia and associated electroless treatment formulations. These masks are also compatible with the growth of polyphosphazene films by electrochemistry.
• step S2 the surface of the step S1 with the premasks PM is covered with liquid ammonia AL, on which the polyphosphazene PLP is deposited.
• step S3 very thin films (of the order of a few nanometers) of polyphosphazene PLP covering the surfaces of the semiconductor SC left free by the PM pre-masks are obtained.
• the polyphosphazene PLP did not deposit on PM prepads.
• the PLP film is shown to be thinner than the thickness of the SiOxNy-based PM pre-masks. In reality, PLP film (a few nanometers) is much thinner than pre-masks (a few micrometers).
• a first step S21 may consist in completely covering the surface of the semiconductor SC with liquid ammonia AL, and then with polyphosphazene PLP for the purpose of depositing a thin film of the latter (a few nanometers thick) over the entire surface of the semiconductor SC as illustrated in step S22 of Figure 1B.
• a reagent beam for example an electronic beam eB (or "eBeam"), or an ion beam more generally, or a laser beam, is used to selectively etch the film of polyphosphazene.
• etching releases the exposed surface of the SC semiconductor leaving the PLP masks of polyphosphazene.
• a chemical etching HBr can be carried out on the free zones of the semiconductor SC as illustrated in step S31. of Figure 1C.
• the chemical etching can then eliminate the semiconductor SC in the uncovered areas and thus, the substrate SUB as illustrated in step S32 of FIG. 1C.
• the present invention is not limited to the embodiments described above by way of example; it extends to other variants.
• a deposition method of the PLP mask type "electroless" preceded by an application of liquid ammonia.
• an alternative may consist in covering areas of the surface of the semiconductor SC with an electrically insulating pre-mask, and then applying an electrochemical deposit of the polyphosphazene, the latter being deposited only on the areas left free of the surface of the semiconductor.

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• Engineering & Computer Science (AREA)
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• General Chemical & Material Sciences (AREA)
• Chemical Kinetics & Catalysis (AREA)
• Weting (AREA)
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• 2017
  • 2017-07-31 FR FR1757294A patent/FR3069701B1/fr active Active
• 2018
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  • 2018-07-31 EP EP18743834.6A patent/EP3662506A1/fr active Pending
  • 2018-07-31 US US16/633,028 patent/US11043390B2/en active Active
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