EP3662506A1 - Improved mask for protecting a semiconductor material for localized etching applications - Google Patents

Improved mask for protecting a semiconductor material for localized etching applications

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Publication number
EP3662506A1
EP3662506A1 EP18743834.6A EP18743834A EP3662506A1 EP 3662506 A1 EP3662506 A1 EP 3662506A1 EP 18743834 A EP18743834 A EP 18743834A EP 3662506 A1 EP3662506 A1 EP 3662506A1
Authority
EP
European Patent Office
Prior art keywords
mask
polyphosphazene
etching
semiconductor material
deposition
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP18743834.6A
Other languages
German (de)
French (fr)
Inventor
Arnaud Etcheberry
Anne-Marie GONCALVES
Jean-Luc Pelouard
Mathieu FREGNAUX
Anaïs LOUBAT
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Centre National de la Recherche Scientifique CNRS
Original Assignee
Centre National de la Recherche Scientifique CNRS
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Filing date
Publication date
Application filed by Centre National de la Recherche Scientifique CNRS filed Critical Centre National de la Recherche Scientifique CNRS
Publication of EP3662506A1 publication Critical patent/EP3662506A1/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/465—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/467—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02247—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by nitridation, e.g. nitridation of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02258—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by anodic treatment, e.g. anodic oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30612—Etching of AIIIBV compounds

Definitions

  • the present invention relates to the field of selective etchings of materials such as semiconductors (in particular III-V or II-VI), and in particular masks used to perform such etchings by etching.
  • the technique of chemical etching masks still requires improvements, particularly in terms of the quality of protection of the mask covering the parts of the semiconductor to be protected, in terms of the fineness of the resulting etching, and others.
  • the present invention improves this situation.
  • the mask is made of a material comprising polyphosphazene.
  • This material is particularly effective for the protection of the underlying materials, in particular semiconductors.
  • the etching carried out at the second step of the above process can be carried out with very aggressive solutions and it has nevertheless been observed that, owing to the very effective protection of the mask, the etching remained particularly fine and perfectly defined, and therefore very localized in the unprotected area.
  • the mask deposition comprises an electrochemically controlled deposition of the polyphosphazene.
  • Mask deposition may include immersion in liquid ammonia followed by polyphosphazene deposition.
  • the deposit can be simply without electrical assistance, according to a so-called “electroless” method.
  • the process may then include the aforementioned immersion in liquid ammonia (possibly associated with dissolved phosphorus pentachloride or "PC15").
  • the mask depot may further include:
  • the pre-mask may be made of a material based on silicon oxynitride SiO x N y
  • the removable pre-mask can be removed typically by immersion in solution of hydrogen fluoride.
  • the polyphosphazene deposit can simply be beam etched to form the aforementioned mask covering the first zone.
  • the beam may be an electron beam or a laser beam.
  • the chemical etching of the semiconductor in regions not protected by the mask may be performed by applying an oxidizing etching solution (for example an "HBr" type solution described below).
  • an oxidizing etching solution for example an "HBr" type solution described below.
  • the present invention also relates to a protective mask of a semiconductor material vis-à-vis a etching etching, made of a material comprising polyphosphazene.
  • this mask may then comprise a thickness of the order of a few nanometers only.
  • Figure 1A schematically illustrates the deposition steps of a polyphosphazene mask in a first embodiment
  • FIG. 1B schematically illustrates the deposition steps of the polyphosphazene mask in a second alternative embodiment
  • FIG. 1C schematically illustrates the etching steps of the semiconductor partially covered by the polyphosphazene-based mask in one or the other of the aforementioned first and second embodiments;
  • FIG. 2 shows the variations of the XPS (photoelectron spectroscopy for surface chemical analysis) signals for different atomic species, along a line comprising a succession of several masks covering an InP semiconductor in this example.
  • XPS photoelectron spectroscopy for surface chemical analysis
  • Polyphosphazene films have protective properties vis-à-vis the chemical reactivity of semiconductor material surfaces.
  • Polyphosphazene is an inorganic polymer (without carbon atom) including in particular a specific skeleton made of phosphorus and nitrogen. It is described in particular in the document:
  • the thicknesses obtained from polyphosphazene films are nanometric (for example between 2 and 10 nm) and it has been observed that such thicknesses are sufficient to ensure their protective function.
  • the chemical inertia of the surfaces covered by this type of film is one of the first protective capabilities of the film, particularly with regard to the re-oxidation of the surfaces due to their interaction with the air (with oxygen , water vapor, or other).
  • an InP type III-V alloy surface coated with a polyphosphazene film obtained by electroless was compared with an aqueous bromine solution (HBr / Br2), acidic or neutral.
  • aqueous bromine solution HBr / Br2
  • the aqueous solution triggers the dissolution of the InP semiconductor (n or p type, the polarization of the semiconductor having no influence).
  • the dissolution is remarkable and rapid for the concentrations used (several micrometers per minute).
  • the chemical stability of the semiconductor surfaces, covered with a polyphosphazene-based passivation obtained electrochemically or electrolessly, with respect to aqueous oxidizing solutions capable of generating significant dissolutions (one or more ⁇ / ⁇ ) on unprotected surfaces of the semiconductor by a conventional film (conventionally a silica film or more generally SiOx, or other) could be observed and is proposed here in an industrial application to the selective etching of semiconductors.
  • the HBr acid or a bottom salt such as KBr is introduced into the etching solution in order to maintain the Br-/ Br 2 pair at a constant level by offering the possibility of testing different levels of pH.
  • the etching capacity of the formulation remains constant over time at a level regulated by the concentration of Br 2 (or (Br 3) - in solution).
  • the unprotected surfaces of the semiconductor undergo aggressive dissolution by oxidative etching, thus constant over time.
  • the surfaces protected by the polyphosphazene film are perfectly free of dissolution. Indeed, it was carried out in solutions to detect traces or "ultra-traces" of indium and phosphorus dissolved in solution by "ICP-OES” (Inductively Plasma Coupled Optical Emission Spectrometry) with a threshold of detection approaching a few nm / cm 2 of dissolved surface. The tests on the totally protected surfaces were compared to those on bare surfaces, with the same chemical formulation and the same experimental conditions (hydrodynamics, temperature, etc.).
  • ICP-OES Inductively Plasma Coupled Optical Emission Spectrometry
  • the surface protection could be shown by XPS analysis of surfaces subjected to polyphosphazene film overlap treatment.
  • XPS analysis photoelectron spectroscopy for surface chemical analysis gives an absolute chemical signature.
  • the signal representative of a surface of InP covered with a polyphosphazene film (and a pre-mask) of the type presented in step S3 of FIG. 1A may consist of a combination characteristic signals specific to: nitrogen,
  • the signals are perfectly complementary along the line comprising a succession of masks, all of these signals well reflecting the existence of a film covering a "buried" surface of InP which nevertheless remains visible. Thus, a film of nanometric thickness is present.
  • the detection level of the matrix signal is a qualitative measurement tool for the thickness of the passivation film.
  • the constancy of the XPS response over time has been observed and demonstrates a remarkable stability of the film in the presence of the aqueous oxidizing solution based on aqueous di-bromine, and this in agreement with the absence of detection of products of dissolution in solution on the protected samples on the entire immersed surface.
  • the detection by XPS makes it possible to show in addition the total stability of the InP surface.
  • the dissolved surface gives a very easily identifiable XPS signature with the growth of an oxide in a thin layer which gives contributions of phosphorus and especially of indium perfectly indexed.
  • the analysis of surfaces protected by polyphosphazene shows a complete absence of such signals related to dissolution.
  • the XPS analyzes thus give two proofs of the total absence of reactivity to the oxidizing solutions on the passivated surfaces. Surfaces coated with polyphosphazene are thus completely protected from chemical etching, making polyphosphazene a material of choice for use as a chemical mask.
  • polyphosphazene has been found to be stable in acidic pH (HBr and / or H 2 SO 4 ), but also basic (in the case of ferricyanide etching for example), or neutral (in the presence of H 2 0 2 for example). It is therefore a material of choice for masks involved in etching processes (especially by any oxidizing solutions).
  • polyphosphazene film as a chemical bond etching mask can be implemented in the context of microelectronics and / or optoelectronics involving localized masking to mirror localized etchings, localized passivations, resumption of contact or growth also localized. It has been shown above that a new family of polyphosphazene-based masking materials is compatible with such applications.
  • areas of localized growth of polyphosphazene can be created by applying prior maskings of the semiconductor surfaces by deposition of, for example, silicon oxynitride SiO x N y units .
  • a semiconductor surface SC (III-V or II-VI or other) to be treated, for example cleaned beforehand by chemical etching, deoxidizing, or other, is obtained. .
  • step S1 PM pre-masks of SiOxNy can be deposited by selective zones according to techniques known per se for this type of masking material.
  • These first level PM masks are compatible with liquid ammonia and associated electroless treatment formulations. These masks are also compatible with the growth of polyphosphazene films by electrochemistry.
  • step S2 the surface of the step S1 with the premasks PM is covered with liquid ammonia AL, on which the polyphosphazene PLP is deposited.
  • step S3 very thin films (of the order of a few nanometers) of polyphosphazene PLP covering the surfaces of the semiconductor SC left free by the PM pre-masks are obtained.
  • the polyphosphazene PLP did not deposit on PM prepads.
  • the PLP film is shown to be thinner than the thickness of the SiOxNy-based PM pre-masks. In reality, PLP film (a few nanometers) is much thinner than pre-masks (a few micrometers).
  • a first step S21 may consist in completely covering the surface of the semiconductor SC with liquid ammonia AL, and then with polyphosphazene PLP for the purpose of depositing a thin film of the latter (a few nanometers thick) over the entire surface of the semiconductor SC as illustrated in step S22 of Figure 1B.
  • a reagent beam for example an electronic beam eB (or "eBeam"), or an ion beam more generally, or a laser beam, is used to selectively etch the film of polyphosphazene.
  • etching releases the exposed surface of the SC semiconductor leaving the PLP masks of polyphosphazene.
  • a chemical etching HBr can be carried out on the free zones of the semiconductor SC as illustrated in step S31. of Figure 1C.
  • the chemical etching can then eliminate the semiconductor SC in the uncovered areas and thus, the substrate SUB as illustrated in step S32 of FIG. 1C.
  • the present invention is not limited to the embodiments described above by way of example; it extends to other variants.
  • a deposition method of the PLP mask type "electroless" preceded by an application of liquid ammonia.
  • an alternative may consist in covering areas of the surface of the semiconductor SC with an electrically insulating pre-mask, and then applying an electrochemical deposit of the polyphosphazene, the latter being deposited only on the areas left free of the surface of the semiconductor.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Weting (AREA)
  • Drying Of Semiconductors (AREA)
  • Formation Of Insulating Films (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Materials For Photolithography (AREA)

Abstract

The invention relates to the chemical etching of a semiconductor material, including: - depositing at least one mask (PLP) on a first surface zone of a semiconductor material (SC); and - chemically etching (HBr) (S31) a second surface zone of the semiconductor material (SC) that is not covered by the mask (PLP). In particular, the aforementioned mask is produced in a material including polyphosphazene, which material protects the underlying semiconductor especially well.

Description

Masque perfectionné de protection d'un matériau semiconducteur pour des applications de gravure localisée  Advanced mask for protecting a semiconductor material for localized engraving applications
La présente invention concerne le domaine des gravures sélectives de matériaux tels que des semiconducteurs (notamment III-V, ou encore II- VI), et en particulier des masques utilisés pour effectuer de telles gravures par attaque chimique. The present invention relates to the field of selective etchings of materials such as semiconductors (in particular III-V or II-VI), and in particular masks used to perform such etchings by etching.
La technique des masques par attaque chimique nécessite encore des perfectionnements, notamment en termes de qualité de protection du masque recouvrant les parties du semiconducteur à protéger, en termes de finesse de la gravure résultante, et autres. La présente invention vient améliorer cette situation. The technique of chemical etching masks still requires improvements, particularly in terms of the quality of protection of the mask covering the parts of the semiconductor to be protected, in terms of the fineness of the resulting etching, and others. The present invention improves this situation.
Elle propose à cet effet un procédé de gravure par attaque chimique d'un matériau semiconducteur, comportant : un dépôt d'au moins un masque sur une première zone de surface de matériau semiconducteur, et It proposes for this purpose a method of etching by etching of a semiconductor material, comprising: depositing at least one mask on a first surface area of semiconductor material, and
- une gravure par attaque chimique d'une deuxième zone de surface du matériau semiconducteur non recouverte par le masque.  an etching by etching of a second surface area of the semiconductor material not covered by the mask.
En particulier, le masque est réalisé dans un matériau comportant du polyphosphazène. In particular, the mask is made of a material comprising polyphosphazene.
Ce matériau, comme illustré par des exemples de réalisation ci-après, est particulièrement efficace pour la protection des matériaux sous-jacents, notamment semiconducteurs. Ainsi, la gravure réalisée à la deuxième étape du procédé ci-dessus peut être réalisée avec des solutions très agressives et il a été observé néanmoins que, du fait de la protection très efficace du masque, la gravure restait particulièrement fine et parfaitement définie, et donc très localisée dans la zone non protégée. This material, as illustrated by the following embodiments, is particularly effective for the protection of the underlying materials, in particular semiconductors. Thus, the etching carried out at the second step of the above process can be carried out with very aggressive solutions and it has nevertheless been observed that, owing to the very effective protection of the mask, the etching remained particularly fine and perfectly defined, and therefore very localized in the unprotected area.
Dans une forme de réalisation, le dépôt de masque comprend un dépôt contrôlé par électrochimie du polyphosphazène. In one embodiment, the mask deposition comprises an electrochemically controlled deposition of the polyphosphazene.
Le dépôt de masque peut comprendre une immersion dans de l'ammoniac liquide suivie d'un dépôt de polyphosphazène. Alternativement à un dépôt par électrochimie, le dépôt peut être simplement sans assistance électrique, selon une méthode dite « electroless ». Dans les deux cas, le procédé peut comporter alors l'immersion précitée dans l'ammoniac liquide (associée éventuellement à du pentachlorure de phosphore ou « PC15 » dissous). Mask deposition may include immersion in liquid ammonia followed by polyphosphazene deposition. Alternatively to an electrochemical deposit, the deposit can be simply without electrical assistance, according to a so-called "electroless" method. In both cases, the process may then include the aforementioned immersion in liquid ammonia (possibly associated with dissolved phosphorus pentachloride or "PC15").
Le dépôt de masque peut comprendre en outre : The mask depot may further include:
- un dépôt d'au moins un pré-masque amovible sur ladite deuxième zone de surface du matériau semiconducteur, a deposit of at least one removable pre-mask on said second surface area of the semiconductor material,
- le dépôt de polyphosphazène (par électrochimie ou par aspersion d'ammoniac liquide), et, le polyphosphazène n'accrochant pas au pré-masque,  the deposition of polyphosphazene (by electrochemistry or by spraying of liquid ammonia), and the polyphosphazene not hooking to the pre-mask,
- un simple retrait du pré-masque amovible pour libérer ladite deuxième zone de surface du matériau semiconducteur, pour y réaliser ensuite l'opération de gravure elle-même.  - A simple removal of the removable pre-mask to release said second surface area of the semiconductor material, to then perform the etching operation itself.
Par exemple, le pré-masque peut être réalisé dans un matériau à base d'oxynitrure de silicium SiOxNy For example, the pre-mask may be made of a material based on silicon oxynitride SiO x N y
Le pré-masque amovible peut être retiré typiquement par immersion en solution de fluorure d'hydrogène. The removable pre-mask can be removed typically by immersion in solution of hydrogen fluoride.
Dans une réalisation alternative à l'utilisation d'un pré-masque, le dépôt de polyphosphazène peut simplement être gravé par faisceau pour former le masque précité recouvrant la première zone. In an alternative embodiment to the use of a pre-mask, the polyphosphazene deposit can simply be beam etched to form the aforementioned mask covering the first zone.
Le faisceau peut être un faisceau d'électrons ou encore un faisceau laser. The beam may be an electron beam or a laser beam.
L'attaque chimique du semiconducteur dans des régions non protégées par le masque peut être effectuée par application d'une solution oxydante de gravure (par exemple une solution de type « HBr » décrite plus loin). The chemical etching of the semiconductor in regions not protected by the mask may be performed by applying an oxidizing etching solution (for example an "HBr" type solution described below).
La présente invention vise aussi un masque de protection d'un matériau semiconducteur vis-à-vis d'une gravure par attaque chimique, réalisé dans un matériau comportant du polyphosphazène. Avantageusement, ce masque peut alors comporter une épaisseur de l'ordre de quelques nanomètres seulement. The present invention also relates to a protective mask of a semiconductor material vis-à-vis a etching etching, made of a material comprising polyphosphazene. Advantageously, this mask may then comprise a thickness of the order of a few nanometers only.
D'autres avantages et caractéristiques de l'invention apparaîtront à la lecture de la description détaillée d'exemples de réalisation non limitatifs, et à l'examen des dessins annexés sur lesquels : Other advantages and characteristics of the invention will appear on reading the detailed description of nonlimiting exemplary embodiments, and on examining the appended drawings in which:
La figure 1A illustre schématiquement les étapes de dépôt d'un masque à base de polyphosphazène dans un premier mode de réalisation ; Figure 1A schematically illustrates the deposition steps of a polyphosphazene mask in a first embodiment;
La figure 1B illustre schématiquement les étapes de dépôt du masque à base de polyphosphazène dans un deuxième mode de réalisation, alternatif ;  FIG. 1B schematically illustrates the deposition steps of the polyphosphazene mask in a second alternative embodiment;
- La figure 1C illustre schématiquement les étapes de gravure du semiconducteur recouvert partiellement par le masque à base de polyphosphazène dans l'un ou l'autre des premier et deuxième modes de réalisation précités ;  FIG. 1C schematically illustrates the etching steps of the semiconductor partially covered by the polyphosphazene-based mask in one or the other of the aforementioned first and second embodiments;
La figure 2 représente les variations des signaux de XPS (spectroscopie de photoélectron pour l'analyse chimique de surface) pour différentes espèces atomiques, le long d'une ligne comportant une succession de plusieurs masques recouvrant un semiconducteur InP dans cet exemple.  FIG. 2 shows the variations of the XPS (photoelectron spectroscopy for surface chemical analysis) signals for different atomic species, along a line comprising a succession of several masks covering an InP semiconductor in this example.
Des films de polyphosphazène présentent des propriétés protectrices vis-à-vis de la réactivité chimique des surfaces de matériaux semiconducteurs. Le polyphosphazène est un polymère inorganique (sans atome de carbone) comportant en particulier un squelette spécifique fait de phosphore et d'azote. Il est décrit notamment dans le document : Polyphosphazene films have protective properties vis-à-vis the chemical reactivity of semiconductor material surfaces. Polyphosphazene is an inorganic polymer (without carbon atom) including in particular a specific skeleton made of phosphorus and nitrogen. It is described in particular in the document:
"Fully Protective yet Functionalizable Monolayer on InP" (Anne -Marie Gonçalves, Nicolas Mézailles, Charles Mathieu, Pascal Le Floch, Arnaud Etcheberry), Chemistry of Materials, 2010, N°22, p.3114-3120. Ces films de polyphosphazène peuvent être obtenus par voie électrochimique ou sans prise de contact par un procédé de type « electroless » par exemple dans l'ammoniac liquide (en solution) additionné à du PC15. "Fully Protective and Functionalizable Monolayer on InP" (Anne -Marie Gonçalves, Nicolas Mézailles, Charles Mathieu, Pascal Floch, Arnaud Etcheberry), Chemistry of Materials, 2010, No. 22, p.3114-3120. These polyphosphazene films can be obtained electrochemically or without contacting by an "electroless" type process, for example in liquid ammonia (in solution) added to PC15.
Les épaisseurs obtenues de films de polyphosphazène sont nanométriques (par exemple entre 2 et 10 nm) et il a été observé que de telles épaisseurs suffisent à assurer leur fonction de protection. L'inertie chimique des surfaces recouvertes par ce type de film est l'une des premières capacités protectrices du film, vis-à-vis notamment de la ré-oxydation des surfaces du fait de leur interaction avec l'air (avec l'oxygène, la vapeur d'eau, ou autre). The thicknesses obtained from polyphosphazene films are nanometric (for example between 2 and 10 nm) and it has been observed that such thicknesses are sufficient to ensure their protective function. The chemical inertia of the surfaces covered by this type of film is one of the first protective capabilities of the film, particularly with regard to the re-oxidation of the surfaces due to their interaction with the air (with oxygen , water vapor, or other).
Cette première capacité de protection a pu être testée sur des durées supérieures à une année et les tests démontrent des capacités protectrices remarquables de ce film. Le comportement de ce type de film a été testé en présence de solutions aqueuses oxydantes qui génèrent une dissolution continue de semiconducteurs. De ce fait, ces solutions aqueuses oxydantes peuvent être utilisées comme solution de gravure en technologie humide pour générer des structures (dites « MESA », ou « en rubans », ou autres) sur des surfaces préalablement recouvertes de motifs de masquage délimités ici par des dépôts de film de polyphosphazène définissant les zones à protéger. This first protective capability has been tested for durations longer than one year and the tests demonstrate remarkable protective capabilities of this film. The behavior of this type of film has been tested in the presence of aqueous oxidizing solutions which generate a continuous dissolution of semiconductors. Therefore, these aqueous oxidizing solutions can be used as etching solution in wet technology to generate structures (called "MESA", or "in ribbons", or other) on surfaces previously covered with masking patterns delimited here by Polyphosphazene film deposits defining the areas to be protected.
A titre d'exemple ayant procuré des résultats satisfaisants, une surface d'alliage III-V de type InP recouverte d'un film de polyphosphazène obtenu par voie « electroless » a été mise en regard d'une solution aqueuse de brome (HBr/Br2), acide ou neutre. Sur les surfaces du semiconducteur qui n'ont pas été recouvertes par le film de polyphosphazène, la solution aqueuse déclenche la dissolution du semiconducteur InP (de type n ou p, la polarisation du semiconducteur n'ayant aucune influence). La dissolution est remarquable et rapide pour les concentrations utilisées (plusieurs micromètres par minute). By way of example having given satisfactory results, an InP type III-V alloy surface coated with a polyphosphazene film obtained by electroless was compared with an aqueous bromine solution (HBr / Br2), acidic or neutral. On the semiconductor surfaces which have not been covered by the polyphosphazene film, the aqueous solution triggers the dissolution of the InP semiconductor (n or p type, the polarization of the semiconductor having no influence). The dissolution is remarkable and rapid for the concentrations used (several micrometers per minute).
En revanche, il est observé une stabilité totale des surfaces protégées par le film de polyphosphazène, relativement au phénomène de gravure particulièrement agressif des solutions à base de di-brome aqueux. Le film s'étant avéré stable vis-à-vis de toutes les solutions acides, neutres ou basiques testées. Cette capacité de masquage par polyphosphazène, pour gravure humide, peut ainsi fonctionner avec toutes les solutions de gravure humide en technologie III-V ou II-VI. On the other hand, it is observed a total stability of the surfaces protected by the polyphosphazene film, relative to the phenomenon of particularly aggressive etching of solutions based on aqueous di-bromine. The film having proved stable vis-à-vis all the acidic solutions, neutral or basic tested. This polyphosphazene masking ability, for wet etching, can thus work with all wet etching solutions in III-V or II-VI technology.
Ainsi, la stabilité chimique des surfaces du semiconducteur, recouvertes d'une passivation à base de polyphosphazène obtenue par voie électrochimique ou par voie « electroless », vis-à-vis de solutions aqueuses oxydantes capables de générer des dissolutions importantes (un ou plusieurs μηι/ιηίη) sur des surfaces non protégées du semiconducteur par un film conventionnel (classiquement un film de silice ou plus généralement SiOx, ou autre) a pu être observée et est proposée ici dans une application industrielle à la gravure sélective de semiconducteurs. Thus, the chemical stability of the semiconductor surfaces, covered with a polyphosphazene-based passivation obtained electrochemically or electrolessly, with respect to aqueous oxidizing solutions capable of generating significant dissolutions (one or more μηι / ιηίη) on unprotected surfaces of the semiconductor by a conventional film (conventionally a silica film or more generally SiOx, or other) could be observed and is proposed here in an industrial application to the selective etching of semiconductors.
Dans l'exemple de réalisation présenté ici sans perte de généralité, le cas du semiconducteur III-V, de type InP, recouvert et non-recouvert d'un film de polyphosphazène (à des fins de comparaison), en présence d'une solution aqueuse de Br2 acide, montre que le polyphosphazène peut être utilisé en tant que masque protecteur très efficace pour des attaques chimiques très agressives qui habituellement « empiètent » sur les zones protégées par le masque. Ainsi, l'emploi du polyphosphazène devrait permettre d'utiliser des solutions chimiques très agressives, alors que le masquage reste d'une épaisseur de l'ordre de quelques nanomètres. Par ailleurs, la protection du polyphosphazène est très durable et améliore ainsi la qualité des composants à base de semiconducteurs dans leur durée de fonctionnement. In the exemplary embodiment presented here without loss of generality, the case of the III-V semiconductor, of the InP type, covered and not covered with a polyphosphazene film (for comparison purposes), in the presence of a solution aqueous Br 2 acid, shows that polyphosphazene can be used as a very effective protective mask for very aggressive chemical attacks that usually "encroach" on areas protected by the mask. Thus, the use of polyphosphazene should allow the use of very aggressive chemical solutions, while the masking remains of a thickness of the order of a few nanometers. In addition, the protection of polyphosphazene is very durable and thus improves the quality of semiconductor-based components in their operating life.
Dans cet exemple de réalisation, l'acide HBr ou un sel de fond tel que KBr est introduit dans la solution d'attaque chimique afin de maintenir à un niveau constant le couple Br-/Br2 en offrant la possibilité de tester différents niveaux de pH. Ainsi, les capacités d'attaque de la formulation restent constantes dans le temps à un niveau réglé par la concentration en Br2 (ou (Br3)- en solution). In this embodiment, the HBr acid or a bottom salt such as KBr is introduced into the etching solution in order to maintain the Br-/ Br 2 pair at a constant level by offering the possibility of testing different levels of pH. Thus, the etching capacity of the formulation remains constant over time at a level regulated by the concentration of Br 2 (or (Br 3) - in solution).
Les surfaces non protégées du semiconducteur subissent une dissolution agressive par attaque oxydante, ainsi constante dans le temps. The unprotected surfaces of the semiconductor undergo aggressive dissolution by oxidative etching, thus constant over time.
En revanche, les surfaces protégées par le film de polyphosphazène sont parfaitement exemptes de dissolution. En effet, il a été procédé à des dosages en solution pour détecter des traces ou « ultra-traces » de l'indium et du phosphore dissouts en solution par « ICP-OES » (Spectrométrie d'Émission Optique Couplée à Plasma Inductif) avec un seuil de détection avoisinant quelques nm/cm2 de surface dissoute. Les tests sur les surfaces totalement protégées ont été comparés à ceux sur surfaces nues, avec la même formulation chimique et de mêmes conditions expérimentales (hydrodynamique, température, etc.). On the other hand, the surfaces protected by the polyphosphazene film are perfectly free of dissolution. Indeed, it was carried out in solutions to detect traces or "ultra-traces" of indium and phosphorus dissolved in solution by "ICP-OES" (Inductively Plasma Coupled Optical Emission Spectrometry) with a threshold of detection approaching a few nm / cm 2 of dissolved surface. The tests on the totally protected surfaces were compared to those on bare surfaces, with the same chemical formulation and the same experimental conditions (hydrodynamics, temperature, etc.).
Il a été observé un différentiel de plusieurs ordres de grandeurs : les surfaces protégées donnent lieu à des solutions non détectées ou en limites basses de détection des appareils de mesure. La protection des surfaces recouvertes du film de polyphosphazène est donc complète. A differential of several orders of magnitude has been observed: the protected surfaces give rise to undetected solutions or to low detection limits of the measuring devices. The protection of the surfaces covered with the polyphosphazene film is therefore complete.
La protection des surfaces a pu être montrée par une analyse XPS des surfaces soumises à traitement de recouvrement par un film de polyphosphazène. L'analyse XPS (spectroscopie de photoélectron pour l'analyse chimique de surface) donne une signature chimique absolue. En référence à la figure 2, le signal représentatif d'une surface d'InP recouverte d'un film de polyphosphazène (et d'un pré-masque) du type présenté à l'étape S3 de la figure 1A peut consister en une combinaison de signaux caractéristiques spécifiques à : l'azote, The surface protection could be shown by XPS analysis of surfaces subjected to polyphosphazene film overlap treatment. XPS analysis (photoelectron spectroscopy for surface chemical analysis) gives an absolute chemical signature. With reference to FIG. 2, the signal representative of a surface of InP covered with a polyphosphazene film (and a pre-mask) of the type presented in step S3 of FIG. 1A may consist of a combination characteristic signals specific to: nitrogen,
le phosphore à haute énergie, le carbone lié essentiellement à la contamination carbonée et l'oxygène aussi liés à la contamination du film de polyphosphazène lors de son exposition à l'air, puis au phosphore à basse énergie et à l'indium qui sont liées quant à eux à la réponse de la matrice de l'alliage InP qui passe au travers du film du fait de son épaisseur nanométrique. En référence à la figure 2, les signaux sont parfaitement complémentaires le long de la ligne comportant une succession de masques, l'ensemble de ces signaux traduisant bien l'existence d'un film couvrant une surface "enterrée" d'InP qui reste néanmoins visible. Ainsi, un film d'épaisseur nanométrique est bien présent. high energy phosphorus, the carbon essentially linked to the carbon contamination and oxygen also linked to the contamination of the polyphosphazene film during its exposure to air, then to low energy phosphorus and indium, which are linked to the response of the matrix of the InP alloy which passes through the film because of its nanometric thickness. With reference to FIG. 2, the signals are perfectly complementary along the line comprising a succession of masks, all of these signals well reflecting the existence of a film covering a "buried" surface of InP which nevertheless remains visible. Thus, a film of nanometric thickness is present.
Par ailleurs, le niveau de détection du signal de matrice est un outil de mesure qualitative de l'épaisseur du film de passivation. En particulier, la constance de la réponse XPS dans le temps a été observée et démontre une stabilité remarquable du film en présence de la solution oxydante acide à base de di-brome aqueux, et ce en accord avec l'absence de détection de produits de dissolution en solution sur les échantillons protégés sur la totalité de la surface immergée. Moreover, the detection level of the matrix signal is a qualitative measurement tool for the thickness of the passivation film. In particular, the constancy of the XPS response over time has been observed and demonstrates a remarkable stability of the film in the presence of the aqueous oxidizing solution based on aqueous di-bromine, and this in agreement with the absence of detection of products of dissolution in solution on the protected samples on the entire immersed surface.
La détection par XPS permet de montrer en outre la totale stabilité de la surface d'InP. La surface dissoute donne une signature XPS très facilement repérable avec la croissance d'un oxyde en couche mince qui donne des contributions de phosphore et surtout d'indium parfaitement répertoriées. L'analyse des surfaces protégées par le polyphosphazène montre une absence totale de tels signaux liés à la dissolution. Les analyses XPS donnent donc deux preuves de l'absence totale de réactivité aux solutions oxydantes sur les surfaces passivée. Les surfaces recouvertes par le polyphosphazène sont donc totalement protégées d'une gravure chimique, ce qui fait du polyphosphazène un matériau de choix pour une utilisation en tant que masque chimique. The detection by XPS makes it possible to show in addition the total stability of the InP surface. The dissolved surface gives a very easily identifiable XPS signature with the growth of an oxide in a thin layer which gives contributions of phosphorus and especially of indium perfectly indexed. The analysis of surfaces protected by polyphosphazene shows a complete absence of such signals related to dissolution. The XPS analyzes thus give two proofs of the total absence of reactivity to the oxidizing solutions on the passivated surfaces. Surfaces coated with polyphosphazene are thus completely protected from chemical etching, making polyphosphazene a material of choice for use as a chemical mask.
Il convient d'indiquer qu'en général, le polyphosphazène s'est avéré stable en pH acide (HBr et/ou H2S04), mais aussi basique (en cas d'attaque à base de ferricyanure par exemple), ou neutre (en présence de H202 par exemple). Il s'agit donc d'un matériau de choix pour les masques intervenant dans les procédés de gravure par attaque chimique (notamment par des solutions oxydantes quelconques). It should be noted that, in general, polyphosphazene has been found to be stable in acidic pH (HBr and / or H 2 SO 4 ), but also basic (in the case of ferricyanide etching for example), or neutral (in the presence of H 2 0 2 for example). It is therefore a material of choice for masks involved in etching processes (especially by any oxidizing solutions).
L'utilisation d'un film de polyphosphazène en tant que masque de gravure par attache chimique peut être mise en œuvre en contexte de microélectronique et/ou d'optoélectronique impliquant des masquages localisés pour générer en miroir des gravures localisées, des passivations localisées, des reprises de contact ou de croissance elles aussi localisées. Il a été montré ci-dessus qu'une nouvelle famille de matériaux de masquage à base de polyphosphazène est compatible avec de telles applications. The use of a polyphosphazene film as a chemical bond etching mask can be implemented in the context of microelectronics and / or optoelectronics involving localized masking to mirror localized etchings, localized passivations, resumption of contact or growth also localized. It has been shown above that a new family of polyphosphazene-based masking materials is compatible with such applications.
En procédé « electroless » ou par électrochimie, des zones de croissance localisée de polyphosphazène peuvent être créées en appliquant des masquages préalables des surfaces de semiconducteur par dépôt de motifs par exemple d'oxynitrure de silicium SiOxNy. In the "electroless" or electrochemical process, areas of localized growth of polyphosphazene can be created by applying prior maskings of the semiconductor surfaces by deposition of, for example, silicon oxynitride SiO x N y units .
Ainsi, en référence à la figure 1A, lors d'une première étape S0, on obtient une surface de semiconducteur SC (III-V ou II-VI ou autre) à traiter, par exemple nettoyée préalablement par décapage chimique, désoxydant, ou autre. Thus, with reference to FIG. 1A, during a first step S0, a semiconductor surface SC (III-V or II-VI or other) to be treated, for example cleaned beforehand by chemical etching, deoxidizing, or other, is obtained. .
Ensuite, à l'étape SI, des pré-masques PM de SiOxNy peuvent être déposés par zones sélectives selon des techniques connues en soi pour ce type de matériau de masquage. Ces masquages PM de premier niveau sont compatibles avec l'ammoniac liquide et les formulations associées de traitement « electroless ». Ces masques sont en outre compatibles avec les croissances de films de polyphosphazène par électrochimie. Ainsi, à l'étape S2, la surface de l'étape SI avec les prémasques PM est couverte d'ammoniac liquide AL, sur lequel est déposé le polyphosphazène PLP. En fin de réaction, à l'étape S3, on obtient des films très minces (de l'ordre de quelques nanomètres) de polyphosphazène PLP recouvrant les surfaces du semiconducteur SC laissées libres par les pré-masques PM. En revanche, le polyphosphazène PLP ne s'est pas déposé sur les pré- maques PM. Sur la figure 1A à l'étape S3, on a représenté le film PLP plus mince que l'épaisseur des pré-masques PM à base de SiOxNy. En réalité, le film PLP (quelques nanomètres) est beaucoup plus mince que les pré-masques (quelques micromètres). Ces motifs complémentaires de polyphosphazène PLP dans les zones non masquées de la surface SC forment alors un masquage « en négatif ». Ensuite, l'élimination sélective de la zone masquée par SiOxNy peut être opérée en dégageant ainsi toutes les zones non recouvertes par du polyphosphazène. Then, in step S1, PM pre-masks of SiOxNy can be deposited by selective zones according to techniques known per se for this type of masking material. These first level PM masks are compatible with liquid ammonia and associated electroless treatment formulations. These masks are also compatible with the growth of polyphosphazene films by electrochemistry. Thus, in step S2, the surface of the step S1 with the premasks PM is covered with liquid ammonia AL, on which the polyphosphazene PLP is deposited. At the end of the reaction, in step S3, very thin films (of the order of a few nanometers) of polyphosphazene PLP covering the surfaces of the semiconductor SC left free by the PM pre-masks are obtained. On the other hand, the polyphosphazene PLP did not deposit on PM prepads. In FIG. 1A at step S3, the PLP film is shown to be thinner than the thickness of the SiOxNy-based PM pre-masks. In reality, PLP film (a few nanometers) is much thinner than pre-masks (a few micrometers). These complementary patterns of polyphosphazene PLP in the unmasked areas of the SC surface then form a "negative" masking. Then, the selective removal of the masked zone by SiOxNy can be performed thus freeing all areas not covered by polyphosphazene.
En effet, à l'étape suivante S4, les pré-masques PM de SiOxNy peuvent être retirés par des techniques connues en soi, comme l'immersion dans du fluorure d'hydrogène HF. Il ne reste ainsi, à l'étape suivante S5, que les zones couvertes de polyphosphazène, entre lesquelles la surface du semiconducteur SC est à nu. Indeed, in the next step S4, PM pre-masks SiOxNy can be removed by techniques known per se, such as immersion in hydrogen fluoride HF. Thus, in the next step S5, only the areas covered with polyphosphazene between which the surface of the semiconductor SC is exposed are left.
En variante, la gravure de films de polyphosphazène parfaitement couvrants peut être opérée alternativement par gravure par incidence de faisceau d'électrons ou d'ions ou encore par gravure laser qui assurent de meilleures résolutions spatiales latérales. Ainsi, relativement à cette deuxième forme de réalisation exposée ci-après et en référence à la figure 1B, une première étape S21 peut consister à recouvrer complètement la surface du semiconducteur SC d'ammoniac liquide AL, puis de polyphosphazène PLP en vue du dépôt d'un film mince de ce dernier (quelques nanomètres d'épaisseur) sur l'ensemble de la surface du semiconducteur SC comme illustré à l'étape S22 de la figure 1B. As a variant, the etching of perfectly covering polyphosphazene films can be carried out alternately by electron or ion beam incident etching or else by laser etching which ensure better lateral spatial resolutions. Thus, with respect to this second embodiment described below and with reference to FIG. 1B, a first step S21 may consist in completely covering the surface of the semiconductor SC with liquid ammonia AL, and then with polyphosphazene PLP for the purpose of depositing a thin film of the latter (a few nanometers thick) over the entire surface of the semiconductor SC as illustrated in step S22 of Figure 1B.
Ensuite, à l'étape S23, un faisceau réactif par exemple un faisceau électronique eB (ou « eBeam »), ou encore un faisceau d'ions plus généralement, ou encore un faisceau laser, est utilisé pour graver sélectivement par zones le film de polyphosphazène. A l'étape S24, la gravure libère la surface à nu du semi-conducteur SC en laissant les masques PLP de polyphosphazène. Ensuite, dans l'un ou l'autre des modes de réalisation illustrés et commentés ci-avant en référence respectivement aux figures 1A et 1B, une attaque chimique HBr peut être réalisée sur les zones libres du semiconducteur SC comme illustré à l'étape S31 de la figure 1C. Par exemple dans le cas où le semiconducteur SC est constitué d'une couche mince déposée sur un substrat SUB (par exemple un substrat de verre ou métallique), l'attaque chimique peut alors éliminer le semiconducteur SC dans les zones non recouvertes et mettre à nu ainsi le substrat SUB comme illustré à l'étape S32 de la figure 1C. Then, in step S23, a reagent beam, for example an electronic beam eB (or "eBeam"), or an ion beam more generally, or a laser beam, is used to selectively etch the film of polyphosphazene. In step S24, etching releases the exposed surface of the SC semiconductor leaving the PLP masks of polyphosphazene. Then, in one or other of the embodiments illustrated and commented on above with reference to FIGS. 1A and 1B respectively, a chemical etching HBr can be carried out on the free zones of the semiconductor SC as illustrated in step S31. of Figure 1C. For example, in the case where the semiconductor SC consists of a thin layer deposited on a substrate SUB (for example a glass or metal substrate), the chemical etching can then eliminate the semiconductor SC in the uncovered areas and Thus, the substrate SUB as illustrated in step S32 of FIG. 1C.
Bien entendu, la présente invention ne se limite pas aux formes de réalisation décrites ci-avant à titre d'exemple ; elle s'étend à d'autres variantes. Ainsi, par exemple, on a décrit ci-avant un procédé de dépôt du masque PLP de type « electroless » précédé par une application d'ammoniac liquide. Néanmoins, une alternative peut consister à recouvrir des zones de la surface du semiconducteur SC par un pré-masque isolant électriquement, et appliquer ensuite un dépôt par électrochimie du polyphosphazène, ce dernier ne venant se déposer que sur les zones laissées libres de la surface du semiconducteur. Of course, the present invention is not limited to the embodiments described above by way of example; it extends to other variants. Thus, for example, there has been described above a deposition method of the PLP mask type "electroless" preceded by an application of liquid ammonia. Nevertheless, an alternative may consist in covering areas of the surface of the semiconductor SC with an electrically insulating pre-mask, and then applying an electrochemical deposit of the polyphosphazene, the latter being deposited only on the areas left free of the surface of the semiconductor.

Claims

REVENDICATIONS
1. Procédé de gravure par attaque chimique d'un matériau semiconducteur, comportant : un dépôt d'au moins un masque (PLP) sur une première zone de surface de matériau semiconducteur (SC), et A method of etching by etching a semiconductor material, comprising: depositing at least one mask (PLP) on a first surface area of semiconductor material (SC), and
une gravure (S31) par attaque chimique (HBr) d'une deuxième zone de surface du matériau semiconducteur (SC) non recouverte par le masque (PLP),  an etching (S31) by chemical etching (HBr) of a second surface area of the semiconductor material (SC) not covered by the mask (PLP),
procédé dans lequel le masque est réalisé dans un matériau comportant du polyphosphazène .  process in which the mask is made of a material comprising polyphosphazene.
2. Procédé selon la revendication 1, dans lequel le dépôt de masque (PLP) comprend un dépôt par électrochimie du polyphosphazène. The method of claim 1, wherein the mask deposition (PLP) comprises an electrochemical deposition of the polyphosphazene.
Procédé selon l'une des revendications 1 et 2, dans lequel le dépôt de masque (PLP) comprend une immersion dans de l'ammoniac liquide suivie d'un dépôt de polyphosphazène . The method of one of claims 1 and 2, wherein the mask deposition (PLP) comprises immersion in liquid ammonia followed by polyphosphazene deposition.
Procédé selon l'une des revendications précédentes, dans lequel le dépôt de masque (PLP) comprend : Method according to one of the preceding claims, wherein the mask deposition (PLP) comprises:
- un dépôt d'au moins un pré-masque amovible (PM) sur ladite deuxième zone de surface du matériau semiconducteur (SC),  a deposit of at least one removable pre-mask (PM) on said second surface area of the semiconductor material (SC),
- le dépôt de polyphosphazène, et, le polyphosphazène n' accrochant pas au pré-masque, the deposition of polyphosphazene, and the polyphosphazene not being attached to the pre-mask,
- un retrait (HF) du pré-masque amovible (PM) pour libérer ladite deuxième zone de surface du matériau semiconducteur (SC). - removal (HF) of the removable pre-mask (PM) to release said second surface area of the semiconductor material (SC).
Procédé selon la revendication 4, dans lequel le pré-masque est réalisé dans un matériau à base d'oxynitrure de silicium SiOxNy The method of claim 4, wherein the pre-mask is made of SiO x N y silicon oxynitride material
Procédé selon l'une des revendications 4 et 5, dans lequel le pré-masque amovible (PM) est retiré par immersion dans du fluorure d'hydrogène (HF). Method according to one of claims 4 and 5, wherein the removable pre-mask (PM) is removed by immersion in hydrogen fluoride (HF).
Procédé selon l'une des revendications 2 et 3, dans lequel le dépôt de polyphosphazène est gravé par faisceau pour former ledit masque recouvrant la première zone. Method according to one of claims 2 and 3, wherein the deposition of polyphosphazene is beam etched to form said mask covering the first zone.
8. Procédé selon la revendication 7, dans lequel le faisceau est un faisceau d'électrons (eB). The method of claim 7, wherein the beam is an electron beam (eB).
9. Procédé selon l'une des revendications précédentes, dans lequel l'attaque chimique est effectuée par application d'une solution oxydante (HBr). 9. Method according to one of the preceding claims, wherein the etching is performed by application of an oxidizing solution (HBr).
10. Masque de protection d'un matériau semiconducteur vis-à-vis d'une gravure par attaque chimique, réalisé dans un matériau comportant du polyphosphazène. 10. Mask for protecting a semiconductor material from etching by etching, made of a material comprising polyphosphazene.
11. Masque selon la revendication 10, comportant une épaisseur de l'ordre de quelques nanomètres. 11. Mask according to claim 10, having a thickness of the order of a few nanometers.
EP18743834.6A 2017-07-31 2018-07-31 Improved mask for protecting a semiconductor material for localized etching applications Pending EP3662506A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1757294A FR3069701B1 (en) 2017-07-31 2017-07-31 IMPROVED MASK FOR PROTECTING SEMICONDUCTOR MATERIAL FOR LOCALIZED ENGRAVING APPLICATIONS
PCT/EP2018/070687 WO2019025418A1 (en) 2017-07-31 2018-07-31 Improved mask for protecting a semiconductor material for localized etching applications

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JPH077207B2 (en) * 1987-05-16 1995-01-30 出光石油化学株式会社 Durable pattern forming member
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US6866901B2 (en) * 1999-10-25 2005-03-15 Vitex Systems, Inc. Method for edge sealing barrier films
JP2002151464A (en) 2000-11-16 2002-05-24 Nippon Telegr & Teleph Corp <Ntt> Method for making hole in semiconductor substrate
WO2003015719A1 (en) * 2001-08-17 2003-02-27 Polyzenix Gmbh Device based on nitinol with a polyphosphazene coating
US6911400B2 (en) * 2002-11-05 2005-06-28 International Business Machines Corporation Nonlithographic method to produce self-aligned mask, articles produced by same and compositions for same
US7732885B2 (en) * 2008-02-07 2010-06-08 Aptina Imaging Corporation Semiconductor structures with dual isolation structures, methods for forming same and systems including same
FR2976718B1 (en) * 2011-06-14 2013-07-05 Centre Nat Rech Scient CHEMICAL PASSIVATING PROCESS OF A SURFACE OF A III-V SEMICONDUCTOR MATERIAL PRODUCT, AND PRODUCT OBTAINED BY SUCH A PROCESS
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US20200211855A1 (en) 2020-07-02
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FR3069701A1 (en) 2019-02-01
FR3069701B1 (en) 2019-12-20

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