EP3662474A4 - A memory-based distributed processor architecture - Google Patents

A memory-based distributed processor architecture Download PDF

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Publication number
EP3662474A4
EP3662474A4 EP18841178.9A EP18841178A EP3662474A4 EP 3662474 A4 EP3662474 A4 EP 3662474A4 EP 18841178 A EP18841178 A EP 18841178A EP 3662474 A4 EP3662474 A4 EP 3662474A4
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EP
European Patent Office
Prior art keywords
memory
processor architecture
based distributed
distributed processor
architecture
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP18841178.9A
Other languages
German (de)
French (fr)
Other versions
EP3662474B1 (en
EP3662474A2 (en
Inventor
Elad SITY
Eliad HILLEL
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Neuroblade Ltd
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Neuroblade Ltd
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Priority to EP23151586.7A priority Critical patent/EP4187539A1/en
Publication of EP3662474A2 publication Critical patent/EP3662474A2/en
Publication of EP3662474A4 publication Critical patent/EP3662474A4/en
Application granted granted Critical
Publication of EP3662474B1 publication Critical patent/EP3662474B1/en
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    • G06—COMPUTING; CALCULATING OR COUNTING
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    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1658—Data re-synchronization of a redundant component, or initial sync of replacement, additional or spare unit
    • G—PHYSICS
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    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
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    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
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    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
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    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
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    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
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EP18841178.9A 2017-07-30 2018-07-30 A memory-based distributed processor architecture Active EP3662474B1 (en)

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US201762538724P 2017-07-30 2017-07-30
US201762538722P 2017-07-30 2017-07-30
US201762548990P 2017-08-23 2017-08-23
PCT/IB2018/000995 WO2019025864A2 (en) 2017-07-30 2018-07-30 A memory-based distributed processor architecture

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EP23151586.7A Division-Into EP4187539A1 (en) 2017-07-30 2018-07-30 A memory-based distributed processor architecture

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EP3662474A2 EP3662474A2 (en) 2020-06-10
EP3662474A4 true EP3662474A4 (en) 2021-07-07
EP3662474B1 EP3662474B1 (en) 2023-02-22

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US (9) US11126511B2 (en)
EP (2) EP3662474B1 (en)
JP (1) JP7242634B2 (en)
KR (1) KR20200047551A (en)
CN (2) CN113918481A (en)
TW (2) TWI779069B (en)
WO (1) WO2019025864A2 (en)

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