EP3966698A4 - Memory processing unit architecture - Google Patents

Memory processing unit architecture Download PDF

Info

Publication number
EP3966698A4
EP3966698A4 EP20803010.6A EP20803010A EP3966698A4 EP 3966698 A4 EP3966698 A4 EP 3966698A4 EP 20803010 A EP20803010 A EP 20803010A EP 3966698 A4 EP3966698 A4 EP 3966698A4
Authority
EP
European Patent Office
Prior art keywords
processing unit
memory processing
unit architecture
architecture
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP20803010.6A
Other languages
German (de)
French (fr)
Other versions
EP3966698A1 (en
Inventor
Mohammed ZIDAN
Jacob BOTIMER
Chester Liu
Fan-hsuan MENG
Timothy WESLEY
Zhengya Zhang
Wei Lu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Memryx Inc
Original Assignee
Memryx Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US16/841,544 external-priority patent/US11488650B2/en
Application filed by Memryx Inc filed Critical Memryx Inc
Publication of EP3966698A1 publication Critical patent/EP3966698A1/en
Publication of EP3966698A4 publication Critical patent/EP3966698A4/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0207—Addressing or allocation; Relocation with multidimensional access, e.g. row/column, matrix
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0607—Interleaved addressing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646—Configuration or reconfiguration
    • G06F12/0684—Configuration or reconfiguration with feedback, e.g. presence or absence of unit detected by addressing, overflow detection
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G06F2212/1024—Latency reduction
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Biophysics (AREA)
  • Mathematical Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Biomedical Technology (AREA)
  • Artificial Intelligence (AREA)
  • Neurology (AREA)
  • Computer Hardware Design (AREA)
  • Computational Linguistics (AREA)
  • Data Mining & Analysis (AREA)
  • Evolutionary Computation (AREA)
  • General Health & Medical Sciences (AREA)
  • Molecular Biology (AREA)
  • Computing Systems (AREA)
  • Software Systems (AREA)
  • Image Processing (AREA)
EP20803010.6A 2019-05-07 2020-04-23 Memory processing unit architecture Withdrawn EP3966698A4 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201962844644P 2019-05-07 2019-05-07
US16/841,544 US11488650B2 (en) 2020-04-06 2020-04-06 Memory processing unit architecture
PCT/US2020/029413 WO2020226903A1 (en) 2019-05-07 2020-04-23 Memory processing unit architecture

Publications (2)

Publication Number Publication Date
EP3966698A1 EP3966698A1 (en) 2022-03-16
EP3966698A4 true EP3966698A4 (en) 2023-01-18

Family

ID=73050861

Family Applications (1)

Application Number Title Priority Date Filing Date
EP20803010.6A Withdrawn EP3966698A4 (en) 2019-05-07 2020-04-23 Memory processing unit architecture

Country Status (3)

Country Link
EP (1) EP3966698A4 (en)
CN (1) CN114072778A (en)
WO (1) WO2020226903A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115668121A (en) * 2020-08-31 2023-01-31 麦姆瑞克斯公司 Memory processing unit architecture and configuration

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100332775A1 (en) * 2009-06-29 2010-12-30 Sun Microsystems, Inc. Hybrid interleaving in memory modules
US20120131288A1 (en) * 2006-06-21 2012-05-24 Element Cxi, Llc Reconfigurable Integrated Circuit Architecture With On-Chip Configuration and Reconfiguration
WO2019025864A2 (en) * 2017-07-30 2019-02-07 Sity Elad A memory-based distributed processor architecture

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004006103A1 (en) * 2002-07-09 2004-01-15 Globespanvirata Incorporated Method and system for improving access latency of multiple bank devices
KR20100100395A (en) * 2009-03-06 2010-09-15 삼성전자주식회사 Memory system having multiple processors
US9754056B2 (en) * 2010-06-29 2017-09-05 Exxonmobil Upstream Research Company Method and system for parallel simulation models
US10417555B2 (en) * 2015-05-29 2019-09-17 Samsung Electronics Co., Ltd. Data-optimized neural network traversal

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120131288A1 (en) * 2006-06-21 2012-05-24 Element Cxi, Llc Reconfigurable Integrated Circuit Architecture With On-Chip Configuration and Reconfiguration
US20100332775A1 (en) * 2009-06-29 2010-12-30 Sun Microsystems, Inc. Hybrid interleaving in memory modules
WO2019025864A2 (en) * 2017-07-30 2019-02-07 Sity Elad A memory-based distributed processor architecture

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO2020226903A1 *

Also Published As

Publication number Publication date
EP3966698A1 (en) 2022-03-16
WO2020226903A1 (en) 2020-11-12
CN114072778A (en) 2022-02-18

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